JPS61274456A - Detecting circuit for timing information - Google Patents

Abstract

PURPOSE:To operate at high speed and to make the scale of a circuit smaller as a whole by converting an inputted digital signal series which is in an orthogonal phase relation to a phase information by a conversion table and detecting a timing information included in the signal series from the output of the conversion table. CONSTITUTION:A pair of signals having the orthogonal phase relation which are converted orthogonally and are obtained from a digital modulating signal at a receiving side are inputted to terminals 1 and 2 and after converted to digital signal series at A/D converters 3 and 4, they are inputted to a conversion table 5. The conversion table 5 outputs the phase information corresponded with the combination of digital values which represent the amplitudes of the inputted pair of digital signal series at every time of day as a digital signal. The output signal of the conversion table 5 is introduced to a synchronizing demodulation circuit and also, is inputted to a clock phase error detecting circuit 6 having the function of a timing information detecting means. And the output of a VCO at a clock generating circuit 7 is supplied to A/D converters 3 and 4 as a sampling clock.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a circuit that detects timing information contained in an input signal, such as a phase error of a sampling clock used when A/D converting a digital modulation signal. Person in charge,
In particular, it relates to a timing information detection circuit using digital signal processing.

[Technical background of the invention and its problems]

In recent years, digital ICs and microprocessors.

With the advancement of LSIs for digital signal processing, digital signal processing, which has features such as high functionality, system expandability, and high stability, has come to be used in various fields. For example, in the field of electronic communications, digital signal processing is increasingly used in modulation/demodulation circuits due to its high functionality, and its application to high-speed systems is desired.

When applying digital signal processing to high-speed systems,
A major challenge is how to increase the processing speed. In particular, there is a strong demand for this in demodulation circuits that handle modulated signals using digital modulation methods such as MSK and PSK. moreover,
When configuring a demodulation circuit using digital signal processing, if the sampling clock (regenerated clock) used when converting the input modulated signal into a digital signal with an A/D converter is not synchronized with the transmission clock, the phase Malfunctions of the demodulation system due to errors increase at an accelerating rate.
It is necessary to establish the phase synchronization of the reproducing device very quickly.

However, in conventional demodulation circuits using digital signal processing, the input modulated signal is converted into a digital signal by an A/D converter, and then demodulated by processing the amplitude value using trigonometric function formulas. Therefore, a multiplier was required as a component, which was an obstacle to increasing speed. Further, the multiplier is a basic calculation element with the largest circuit scale in a digital circuit, and using a large number of multipliers is not desirable in terms of hardware reduction.

(Object of the Invention) An object of the present invention is to provide a timing information detection circuit that is capable of high-speed operation and that can reduce the overall circuit scale.

[Summary of the invention]

In order to achieve this object, the present invention provides a conversion means that receives a pair of digital signal sequences as input and outputs phase information corresponding to a combination of digital values representing the amplitude of the pair of digital signal sequences at each time as a digital signal. and means for receiving the phase information output from the converting means and detecting timing information included in the pair of digital signal sequences.

〔Effect of the invention〕

According to the present invention, an input digital signal sequence, which is amplitude value information, is converted into phase information by a conversion means, and timing information such as a phase error of a sampling clock is detected from the phase information. The calculation basically does not require multiplication and can be realized by processing mainly based on addition and subtraction.

Therefore, compared to conventional circuits that detect timing information by multiplying amplitude values using trigonometric formulas, processing speed can be increased, making it possible to quickly establish phase synchronization of recovered clocks. becomes. Further, since the number of multipliers is unnecessary or reduced, the overall circuit scale can be significantly reduced.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention.

In the figure, a pair of signals having an orthogonal phase relationship obtained by orthogonally transforming a digital modulation signal - on the receiving side are input to terminal 1.2, and are converted into a digital signal sequence by A/D converter 3.4. After that, it is input into the conversion table 5. The conversion table 5 is configured using, for example, a ROM table, and outputs, as a digital signal, phase information corresponding to a combination of digital values representing the amplitude at each time of a pair of input digital signal sequences. That is, if the input signal series of the conversion table 5 are x and y, then tan'
A polar coordinate transformation of ('j/X) is performed.

The output signal of the conversion table 5 is guided to a synchronous demodulation circuit (not shown) and is also input to a clock phase error detection circuit 6 as timing information detection means. This clock phase error detection circuit 6 is a recovered clock for the transmission clock of the input digital modulation signal, that is, the A/D converter 3,
4, and its output (sampling phase error signal) is supplied to the clock generation circuit 7. The clock generation circuit 7 includes, for example, a loop filter for removing noise components from the output signal of the phase error detection circuit 6, a D/A converter for converting the output of the loop filter into an analog voltage, and a D/A converter for converting the output of the loop filter into an analog voltage.
Voltage controlled oscillation 1 (V
CO). Then, the output of the VCO is A/
It is supplied to the D converter 3.4 as a sampling clock.

Next, the configuration of the clock phase error detection circuit 6 will be explained in detail, taking as an example the case where the digital modulation signals inputted to the terminals 1 and 2 are frequency-converted to baseband and are orthogonally developed MSK signals. It is assumed that the A/D converter 3.4 samples and digitizes the orthogonally expanded MSK signal once per port using the sampling clock from the clock generating circuit 7.

An example of a change in the phase value of the output signal of the conversion table 5 in this case is shown in FIG. In FIG. 2, the phase value of the output of the conversion table 5 is at point 11 at the first sampling point in the A/D converter 3.4, and at point 12 at the next sampling point.
．． 13, or point 14 at the next sampling point.
~17, and then point 1 at the next sampling point
This indicates that any one of 8 to 23 is taken. In addition, Δ
It is assumed that T is a phase error of the sampling clock (hereinafter referred to as sampling phase error), and ΔC is a phase error of the reproduced carrier.

Here, the phase value ψ8. shown at point 11. is ψ1. =△C
The phase value ψ13, which is expressed as 10−△T + n s= T and shown at point 13, is ψ1
．． =Δc/:>111ΔT'+m2. However, n and m are arbitrary integers, and in the example shown in the figure, they are n-0 and m-1. Here, ΔT) ΔT', ΔC
Since it can be considered as 4ΔC', ψ11−ψ1. = 〒△T ten yam "π...(1). Therefore, ψ, 1-ψ, expressed by equation (1).

By taking modulo π/2 with respect to ψII
It can be seen that six sampling phase errors can be calculated from the value of Iψ13. Also, this sampling phase error Δ
Since the carrier phase error ΔC is automatically removed in the process of calculating T, ΔC does not become a factor in the detection error of the six cameras.

That is, the point 11 on the straight line 24 with a positive slope in FIG.
, 12, 17, 28, etc., and a straight line 25 with a negative slope.
If the phase values of points 13, 14, 18, etc. on the top are obtained, information on the six sampling phase errors can be obtained from them in a form that excludes the influence of the carrier phase error ΔC.

In FIG. 2, whether the phase value of the output of the conversion table 5 exists on a straight line with a positive slope or a straight line with a negative slope can be determined, for example, by the point sampled at t-nT. phase value cp(n T ) and t −(n+
1) Phase value ψ at the sampled point
((n+1)T) or the difference from the phase value ψ((n-1)T) at the point sampled at t-(n-1)T, i.e. ψ' dir=ψ((n+1)T)- ψ(nT) ψdi
This is done by focusing on f = ψ(n'r)-ψ((n-])T). For example, ψdif >0 and ψ
'dif > Q, at least ψ(nT) is on a straight line with a positive slope, and ψdif<0. and ψ'd
If if < Q, it can be seen that at least ψ(nT) is on a straight line with a negative slope.

FIG. 3 shows an example of the configuration of the clock phase error detection circuit 6 based on the above principle. The output signal of the conversion table 5 is input to the terminal 31, and is sequentially delayed by a time T corresponding to the sampling interval in the A10 converter 3.4 by the one-sample delay circuits 32.33. Signal ψ input to terminal 31
((n+1)■) and the output signal ψ(nT) of the 1-sample delay circuit 32 are input to the subtracter 34, and the subtracter 34 outputs the difference ψdif between the two signals. Further, the output signal ψ(nT) of the 1-sample delay circuit 32 and the output signal ψ((n+1)T) of the 1-sample delay circuit 33 are output to the subtracter 35.
The subtracter 35 outputs the difference ψ'dir between both signals. Output signals ψdif and ψ of the subtracters 34 and 35
'dir is input to the determination circuit 36, and it is determined whether ψ(nT) exists on a straight line with a positive slope or a straight line with a negative slope.

Then, a sampling phase error signal is generated from the error signal generation circuit 37 based on the determination result of the determination circuit 36 and, for example, the output signal of the 1-sample delay circuit 32.
is output to. That is, the error signal generation circuit 37 generates (1
), the output signal of the 1-sample delay circuit 32 when the determination circuit 36 determines that the signal exists on a straight line with a positive slope, and the output signal of the 1-sample delay circuit 32 when it is determined that the signal exists on a negative curve. 32 output signals and outputs the difference signal between the two as a sampling phase error signal. In fact, it is desirable to use the average value of the difference signals as the sampling phase error signal.

FIG. 4 shows another example of the configuration of the clock phase error detection circuit 6, and in this example, a one-sample delay circuit 42.
The output signal of 43 is directly supplied to the determination circuit 44. In this case, the subtraction function of the determination circuit 44 is built-in. Also,
The error signal generation circuit 45 inputs the output signal of the conversion table 5 inputted to the terminal 41 and the output signals of the 1-sample delay circuits 42 and 43, and selectively uses these three signals according to the determination result of the determination circuit 44. to generate a sampling phase error signal.

FIG. 5 shows another embodiment of the present invention, in which the output signal of the conversion table 5 is input to a carrier regeneration/synchronous detection circuit 51, where carrier regeneration and synchronous detection using the regenerated carrier are performed. will be carried out. A demodulated output obtained by synchronous detection from this carrier synchronization/detection circuit 51 is outputted to a terminal 52, and a signal from which the carrier phase component has been removed from the output signal of the conversion table 5 is inputted to the clock phase error detection circuit 6. . The clock phase error detection circuit 6 outputs a sampling phase error signal and supplies it to the clock generation circuit 7 in the same manner as in the previous embodiment. However, since the phase error of the reproduced carrier has been removed from the input signal of the clock phase error detection circuit 6 in this embodiment, the specific configuration for clock phase error detection can be further simplified.

FIG. 6 shows a slightly different embodiment of the present invention, in which the output signal of the conversion table 5 is input to a subtracter 61, where the phase component of the reproduced carrier output from the reproduced carrier phase generation circuit 63 is The removed invasion is input to the detection circuit 62. The detection circuit 62 performs phase error detection of the reproduced carrier, synchronous detection, and sampling clock phase error detection. The reproduced carrier phase error signal is inputted to the reproduced carrier phase generation circuit 63, the demodulated output obtained by synchronous detection is outputted to the terminal 64, and the sampling phase error signal is inputted to the clock generation circuit 7. Note that the reproduced carrier phase generation circuit includes, for example, a loop filter that removes the noise component of the reproduced carrier phase error signal, and an accumulation adder that receives the output of the loop filter as an input.
A digital signal corresponding to the reproduced carrier phase is output from the cumulative adder. In this way, the detection of timing information in the present invention, for example, the detection of the phase error of the sampling clock, can be performed simultaneously with the detection of the phase error of the reproduced carrier, the synchronous detection, etc., and thereby the 11th harmonic circuit as a whole can be The circuit scale can be more effectively reduced when

The present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, in the embodiment, the input digital signal sequence is MSK.
I will explain the case of signals, QPSK, offset QPSK, and TFM.

This is also effective for signals using modulation methods such as GMSK. Further, the specific configuration of the cross-over phase error detection circuit as the timing information detection means can also be changed in various ways depending on the type of signal input to the conversion table. Furthermore, in the embodiment, the phase error of the sampling clock was exemplified as the timing information to be detected, but it is also possible to detect clock information etc. originally included in the input signal, in other words, it is possible to detect clock information etc. that are originally included in the input signal. The gist of the present invention is to convert a digital signal sequence into phase information using a conversion table, and to detect timing information included in the signal sequence from the output of the conversion table.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of change in the phase value of the output signal of a conversion table for explaining the operation of the same embodiment, and FIGS. 3 and 4 1 is a diagram showing a configuration example of a clock phase error detection circuit in the same embodiment, and FIGS. 5 and 6 are diagrams showing other embodiments of the present invention. 1.2... Input terminal for digital modulation signals having orthogonal phase relationship, 3, 4... A/D converter, 5... Conversion table, 6... Clock phase error detection circuit, 7...・
Clock generation circuit, 32, 33, 42.43...1 sample delay circuit, 34.35...Subtractor, 36°44
...Judgment circuit, 37.45...Error signal generation circuit,
51...Carrier regeneration/synchronous detection circuit, 61...Subtractor, 62...Detection circuit, 63...Regenerated carrier phase generation circuit.

Claims (6)

[Claims] (1) A conversion means that receives a pair of digital signal sequences having an orthogonal phase relationship as input and outputs phase information corresponding to a combination of digital values representing the amplitude of the pair of digital signal sequences at each time as a digital signal; A timing information detection circuit comprising: means for receiving the phase information output from the converting means and detecting timing information included in the pair of digital signal sequences. (2) The timing information detection circuit according to claim 1, wherein the conversion means is a ROM table. (3) The timing information detection circuit according to claim 1, wherein the pair of digital signal sequences are digital modulation signals. (4) The pair of digital signal sequences are digital modulation signals, and the means for detecting the timing information detects a phase value when a temporal change in the phase information output from the converting means is on a straight line with a positive slope. 2. The timing information detection circuit according to claim 1, wherein the timing information detection circuit detects the difference between the phase value and the phase value when the phase value is on a straight line with a negative slope as timing information. (5) A patent claim characterized in that the means for detecting the timing information detects phase error information of a sampling clock supplied to an A/D converter for obtaining the pair of digital signal sequences. The timing information detection circuit according to the first or fourth range. (6) Timing information detection according to claim 1 or 4, wherein the means for detecting timing information detects clock information included in the pair of digital signal sequences. circuit.