JPS61274421A - Analog switch - Google Patents

Analog switch

Info

Publication number
JPS61274421A
JPS61274421A JP11417085A JP11417085A JPS61274421A JP S61274421 A JPS61274421 A JP S61274421A JP 11417085 A JP11417085 A JP 11417085A JP 11417085 A JP11417085 A JP 11417085A JP S61274421 A JPS61274421 A JP S61274421A
Authority
JP
Japan
Prior art keywords
switch
transistor
trs
signal source
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11417085A
Other languages
Japanese (ja)
Inventor
Kazuo Kato
和男 加藤
Hideo Sato
秀夫 佐藤
Kenkichi Yamashita
賢吉 山下
Satoru Nishimoto
西本 覚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11417085A priority Critical patent/JPS61274421A/en
Publication of JPS61274421A publication Critical patent/JPS61274421A/en
Pending legal-status Critical Current

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  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain the titled switch of a low offset voltage and also a low on-impedance by bringing transistors to an transverse-parallel connection to each other, and making an operating bias current flow to bases separately. CONSTITUTION:Transistor TRs 101 and 102 for constituting an analog switch 100 are brought to the transverse-parallel connection, and to each base, a bias circuit 50 and a switch controlling circuit 150 are connected. When turning on the switch 100, TRs 151, 152 are turned off by a control input terminal 155. As a result, the TRs 101, 102 conduct by a bias current by constant-current sources 51, 52, and a signal source 10 and a load terminal 25 become a conducting state. In this state, the TRs 101 and 102 are brought to the transverse-parallel connection, and a bias current is supplied independently to each base electrode, therefore, on TR is operated as a forward direction TR irrespective of the polarity of the difference voltage of a signal source and a load, and shows a small equivalent on-resistance. In this way, two base bias currents flow to the signal source as a reverse direction operation, and an offset voltage becomes small value.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はトランジスタスイッチπ係り、特に低オフセツ
ト電圧、低インピーダンスのアナログスイッチに関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a transistor switch π, and more particularly to a low offset voltage, low impedance analog switch.

〔発明の背景〕[Background of the invention]

従来、低オフセツト電圧のアナログスイッチとしてトラ
ンジスタのコレクタ側にベース電流を流すいわゆる逆方
向動作のスイッチが知られている(加工編:工業計測技
術大系12信号変換とデータ処理(日刊工業、昭4O−
9)P2S5 のトランジスタチョッパ)。しかし逆方
向動作時のトランジスタの電流増幅率は極めて低いため
、例えば!3図のように双方向スイッチとして容量負荷
のサンプルホールドスイッチとして用いる場合vcは、
オン時のコレクターエミッタ間の信号電流がトランジス
タの逆方向のhFlとなって大きくできず、第2図の1
で示すように充電時間が長くなシ高速化できなかった。
Conventionally, a so-called reverse-operation switch that flows a base current to the collector side of a transistor has been known as a low-offset voltage analog switch (Processing Edition: Industrial Measurement Technology System 12 Signal Conversion and Data Processing (Nikkan Kogyo, 1973). −
9) P2S5 transistor chopper). However, the current amplification factor of the transistor during reverse operation is extremely low, so for example! When using the bidirectional switch as a capacitive load sample hold switch as shown in Figure 3, vc is:
The signal current between collector and emitter when turned on becomes hFl in the opposite direction of the transistor and cannot be increased, resulting in 1 in Figure 2.
As shown in the figure, the charging time was long and the speed could not be increased.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、低オフセツト電圧でかつ低オンインピ
ーダンスのアナログスイッチを提供するにある。
An object of the present invention is to provide an analog switch with low offset voltage and low on-impedance.

〔発明の概要〕[Summary of the invention]

本発明ハ、トランジスタスイッチの逆方向動作は高オン
インピーダンスであるが低オフセツト電圧はでき、順方
向動作では高オフセツト電圧ではあるが低オンインピー
ダンス(大電流)になることに鑑み、トランジスタを互
いに逆並列接続してベースに個別に動作バイアス電流を
流すことにょリ、低オンインピーダンスと低オフセツト
電圧の複合特性が得られるようにしたものである。
The present invention is based on the fact that the reverse operation of a transistor switch has a high on-impedance but a low offset voltage, and the forward operation has a high offset voltage but a low on-impedance (large current). By connecting them in parallel and allowing operating bias currents to flow through the bases individually, it is possible to obtain the combined characteristics of low on-impedance and low offset voltage.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第1図によシ説明する。第1
図においてはサンプルホールド回路の構成例を示してお
り、信号源10と負荷コンデンサ20の間にトランジス
タのアナログスイッチ100が接続されている。スイッ
チ100けトランジスタ101と102で構成され、コ
レクタ、エミッタは互いに逆並列接続しである。各トラ
ンジスタ101.102のベースVCはパ(7ス回路(
ti源)50とスイッチ制御回路150が接続される。
An embodiment of the present invention will be explained below with reference to FIG. 1st
The figure shows an example of the configuration of a sample and hold circuit, in which a transistor analog switch 100 is connected between a signal source 10 and a load capacitor 20. The switch 100 is composed of transistors 101 and 102, and the collector and emitter are connected in antiparallel to each other. The base VC of each transistor 101 and 102 is a pass circuit (7 pass circuits).
ti source) 50 and a switch control circuit 150 are connected.

すなわち、トランジスタ101のベースvcハ定電流源
51とトランジスタ151のコレクタ力、トランジスタ
102のベースVcFi定電流源52とトランジスタ1
52のコレクタが接続されている。
That is, the base VC of the transistor 101 is the constant current source 51 and the collector power of the transistor 151, and the base VC of the transistor 102 is the constant current source 52 and the transistor 1.
52 collectors are connected.

第1図において、アナログスイッチをオンさせるには、
制御入力端子155によシトランジスタ151.152
をオフする。そうすると定電流源51.52によるバイ
アス電流はアナログスイッチ100のトランジスタ10
1,102のベースを介して流れ、トランジスタ101
,102をそれぞれ導通させて、信号源10と負荷端子
20とが導通状態になり負荷のコンデンサ20は信号源
ioの電圧が充電される。
In Figure 1, to turn on the analog switch,
Transistors 151 and 152 are connected to the control input terminal 155.
Turn off. Then, the bias current from the constant current sources 51 and 52 is applied to the transistor 10 of the analog switch 100.
1,102 flows through the base of transistor 101
, 102 are made conductive, the signal source 10 and the load terminal 20 are brought into conduction, and the load capacitor 20 is charged with the voltage of the signal source io.

ここで、トランジスタ101と102は逆並列接続され
ており、各々のベース電極VCは独立にバイアス電流を
供給しているから、信号源と負荷の差電圧の極性に係ら
ず必らず一方のトランジスタは通常のベース電流がエミ
ッタ側に流れる順方向トランジスタとして動作し、大な
るコレクタ電流が流れて小さな等価オン抵抗を示し、負
荷コンデンサ20は急速に信号源10の端子電圧に充電
される。そして、最終的に二つのベースバイアス電流は
逆方向動作としてコレクタ側を通って信号源に流れ、ト
ランジスタのコレクタ、エミッタ間のオフセットを圧n
1myないしそれ以下の極めて小さい値を呈す。
Here, the transistors 101 and 102 are connected in anti-parallel, and each base electrode VC independently supplies a bias current, so regardless of the polarity of the differential voltage between the signal source and the load, one transistor is always connected. operates as a forward transistor with a normal base current flowing to the emitter side, a large collector current flows, exhibiting a small equivalent on-resistance, and the load capacitor 20 is rapidly charged to the terminal voltage of the signal source 10. Finally, the two base bias currents flow in the opposite direction through the collector side to the signal source, reducing the offset between the collector and emitter of the transistor.
It exhibits an extremely small value of 1 my or less.

第2図は、第1図と第3図に示したサンプルホールド回
路に対応した充電特性を示している。第3図の回路では
、信号電流がベースバイアス電流の逆方向トランジスタ
のhyz倍になるため大きくできず第2図の1のように
なるが、第1図の回路では充電過程で必ずペース電流が
エミッタ側に流れる順方向トランジスタとして動作する
ため高い)1y+eを呈して信号電流が大きくなう第2
図の2のように高速に充電される。すなわち、第2図の
2と1の応答の違いはスイッチトランジスタの順。
FIG. 2 shows charging characteristics corresponding to the sample and hold circuits shown in FIGS. 1 and 3. In the circuit shown in Figure 3, the signal current is hyz times the base bias current of the reverse transistor, so it cannot be increased, resulting in a situation like 1 in Figure 2, but in the circuit shown in Figure 1, there is always a pace current during the charging process. Since it operates as a forward direction transistor that flows to the emitter side, it exhibits a high
As shown in figure 2, it charges quickly. In other words, the difference in response between 2 and 1 in Figure 2 is the order of the switch transistors.

逆の増幅率の違いに相当している。This corresponds to the opposite difference in amplification factor.

ナオ、本発明の一実施例では、トランジスタスイッチを
NPNトランジスタ、バイアス電流源を定電流源で示し
たが、それぞれ、PNPトランジスタ、バイアス抵抗等
でもよい。
In one embodiment of the present invention, the transistor switch is an NPN transistor, and the bias current source is a constant current source, but they may also be PNP transistors, bias resistors, or the like.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、スイッチトランジスタが順方向動作と
逆方向動作の複合動作が得られるので、低いオン抵抗と
低いオフセット電圧を兼ねたアナログスイッチが得られ
、高速かつ高精度にできる効果がある。
According to the present invention, since the switch transistor can perform a combined forward and reverse operation, it is possible to obtain an analog switch that has both low on-resistance and low offset voltage, and has the effect of achieving high speed and high precision.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のアナログスイッチを用いた一実施例回
路図、第2図は電気的特性を示す特性図、第3図は従来
のアナログスイッチの一例を示す回路図である。 10・・・信号源、20・・・負荷コンデンサ、50・
・・バイアス電流源、100・・・アナログスイッチ、
150第1m V十 第2m 宅30 Vす
FIG. 1 is a circuit diagram of an embodiment using an analog switch of the present invention, FIG. 2 is a characteristic diagram showing electrical characteristics, and FIG. 3 is a circuit diagram showing an example of a conventional analog switch. 10... Signal source, 20... Load capacitor, 50...
...Bias current source, 100...analog switch,
150th 1st m V10th 2nd m House 30 Vsu

Claims (1)

【特許請求の範囲】[Claims] 1、信号源と負荷との間にコレクタ電極とエミッタ電極
を互いに逆並列接続した1対のトランジスタを接続し、
前記トランジスタの各ベース電極に各々電流バイアス源
と分流スイッチを設け、分流スイッチの制御により前記
トランジスタをオンオフ制御してスイッチングすること
を特徴とするアナログスイッチ。
1. Connect a pair of transistors with collector electrodes and emitter electrodes connected in anti-parallel to each other between the signal source and the load,
An analog switch characterized in that a current bias source and a shunt switch are provided on each base electrode of the transistor, and the transistor is switched on and off by controlling the shunt switch.
JP11417085A 1985-05-29 1985-05-29 Analog switch Pending JPS61274421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11417085A JPS61274421A (en) 1985-05-29 1985-05-29 Analog switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11417085A JPS61274421A (en) 1985-05-29 1985-05-29 Analog switch

Publications (1)

Publication Number Publication Date
JPS61274421A true JPS61274421A (en) 1986-12-04

Family

ID=14630923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11417085A Pending JPS61274421A (en) 1985-05-29 1985-05-29 Analog switch

Country Status (1)

Country Link
JP (1) JPS61274421A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002532883A (en) * 1998-12-07 2002-10-02 テレフオンアクチーボラゲツト エル エム エリクソン(パブル) Analog switch
JP2006101195A (en) * 2004-09-29 2006-04-13 Mitsumi Electric Co Ltd Amplifier circuit and input circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149954A (en) * 1976-06-08 1977-12-13 Mitsubishi Electric Corp Sample holding circuit
JPS548452A (en) * 1977-06-22 1979-01-22 Fujitsu Ltd Analog gate circuit
JPS56102124A (en) * 1980-01-18 1981-08-15 Victor Co Of Japan Ltd Electronic switch circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149954A (en) * 1976-06-08 1977-12-13 Mitsubishi Electric Corp Sample holding circuit
JPS548452A (en) * 1977-06-22 1979-01-22 Fujitsu Ltd Analog gate circuit
JPS56102124A (en) * 1980-01-18 1981-08-15 Victor Co Of Japan Ltd Electronic switch circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002532883A (en) * 1998-12-07 2002-10-02 テレフオンアクチーボラゲツト エル エム エリクソン(パブル) Analog switch
JP4838421B2 (en) * 1998-12-07 2011-12-14 インフィネオン テクノロジーズ アーゲー Analog switch
JP2006101195A (en) * 2004-09-29 2006-04-13 Mitsumi Electric Co Ltd Amplifier circuit and input circuit

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