JPS61269479A - Encoding and decoding device for picture signal - Google Patents

Abstract

PURPOSE:To facilitate the transmission of a refresh signal by transmitting only one bit of the refresh request signal in synchronism with the address information of the block at the same position with an error block of an opposite- directional television signal. CONSTITUTION:A register 51 stores parity information supplied from a separating circuit 20 through a down transmission line 17. A register 52 stores parity information computed by a frame memory 26. The registers 51 and 52 operate simultaneously according to am block clock for error detection supplied from a clock generating circuit 21. A comparing circuit 53 compares outputs of both registers 51 and 52 with each other. Consequently, they are discordance to each other when there is a code error and a refresh request level for removing the influence of the error is generated. A counter 58 counts the block clock for error detection supplied from a transmission-side clock generating circuit 13. The refresh request level written previously is read out by reading operation and then sent out as the refresh request level signal to a multiplexing circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a highly efficient encoding/decoding apparatus for television signals.

(Prior Art) High-efficiency encoding methods for television signals include interframe encoding and interfield encoding.

These devices store the encoded television signal one frame or one field before the input television signal in memory, and encode and transmit the difference signal between the input signal and the memory output. Since the value is very similar to the value one frame or field ago, the transmission speed is reduced by taking advantage of the fact that the value of the difference signal to be transmitted becomes smaller. On the receiving side, the television signal can be reproduced by accumulating the inter-frame (inter-field) difference values sent from the transmitting side.

Such an encoding method is based on the premise that the contents of the memories of the transmitter and receiver are the same. Therefore, when a transmission line code error occurs, erroneous decoding occurs on the receiving side, and the contents of the memory differ from those on the transmitting side. Since the effects of this error are stored in the memory, it is no longer possible to obtain normal reproduced images.

In order to escape from such a state, it is necessary to forcibly refresh the contents of the memory of the transmitter/receiver to the same value.

In the conventional method for refreshing the contents of the memory, first, a receiving unit divides one screen into multiple blocks, detects a code error in each block, and transmits the screen position information of the block where the error occurred to the transmitting unit. There is a method for requesting refresh.

Upon receiving this refresh request information, the transmitter transmits the PCM data or intraframe encoded data of the input image signal to the block where the code error has occurred without using the output of the memory, and the receiver By decoding this data, the contents of the transmitting and receiving memories are refreshed to the same value.

This type of device using this method was published in Japanese Patent Application Laid-Open No. 57-6397.
8 "Image signal transmission device".

(Problem to be Solved by the Invention) In this cited example, the number of blocks from the beginning of the screen to the error block is counted and the output data of the counter is used as the screen self-position information of the block where the code error has occurred. It is transmitting. Therefore, this position information is 9 bits when the TV signal (total number of scanning lines is 525) is divided into blocks for each line, and 75 blocks when it is divided into blocks for every 7 lines, so it is 7 bits of data. . Furthermore, in this reference, even when applied to a two-way video communication system that communicates by sending and receiving two-way video signals, the position information of the error block is asynchronous with the video signal transmitted in the opposite direction. It was transmitting. This has the disadvantage that the circuit for time-division multiplexing this position information with reverse video encoded data is complicated.

The object of the present invention is to solve the problem that the conventional technology requires 7 to 9 bits per block for the position information of the error block, and that time division multiplexing of the position information of the error block and the encoded data of the backward television signal is complicated. An object of the present invention is to provide an image signal encoding/decoding device that solves the problems.

(Means for solving the problem) The present invention does not transmit position information of error blocks,
Focusing on the block information for transmitting the encoded data of the reverse direction television signal, the present invention is characterized in that only one bit of the refresh request signal is transmitted in synchronization with the address information of the same block as the position of the error block. In the conventional technology, the information to be transmitted is not block position information but a refresh request signal, and the information to be transmitted is not transmitted asynchronously with the block address information for transmitting the encoded data of the reverse TV signal, but is transmitted synchronously. What I tried to do is different.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which J is an input terminal for a digitized video signal, 2 is a subtraction circuit, 3 and 24 are switches, 4 is a quantization circuit, and 5 and 23 are Addition circuit, 6,
25 is a 1-pixel delay circuit, 7 and 26 are frame memories, 8
1 is a variable length encoding circuit, 9 is a multiplex circuit, 10.19 is a buffer memory, 11 is an encoded data output terminal, 12 is a video signal input terminal, 13 is a clock generation circuit, 14 is an upstream transmission path, and 15 is a refresh control circuit, 17 is a downstream transmission path, 18 is an encoded data input terminal, 20 is a separation circuit, 2
1 is a clock recovery circuit, 22 is a variable length decoding circuit, 27
28 is an output terminal for a digitized video signal, and 28 is an error detection circuit.

First, the video signal inputted from the Kugata terminal 1 of the digitized video signal is subtracted by the output signal of the switch 3, that is, the prediction signal for the input signal, in the subtraction circuit 2, and the subtraction result is sent to the quantization circuit 4. Quantized. The quantization circuit 4 quantizes the output value of the subtraction circuit 2,
The quantized representative value is output to the adding circuit 5, and the quantization level representing the quantized representative value is output to the variable length encoding circuit 8. The adder circuit 5 obtains a locally decoded signal by adding the output of the switch 3 and the quantized representative value, and supplies this to the one-pixel delay circuit 6 and the frame memory 7. The one-pixel delay circuit 6 is composed of, for example, a flip-flop, and holds the input signal for one time slot period.

The frame memory 7 stores the input signal and outputs it after one frame. The switch 3 switches between the one-pixel delay circuit 6 and the frame memory 7. When the switch 3 connects the output of the one-pixel delay circuit 6, an intra-frame previous value prediction method is implemented, whereas when the switch 3 connects the output of the frame memory 7, an inter-frame prediction method is implemented. The variable length encoding circuit 8 monitors the output of the quantization circuit 4 for each block of a predetermined size (for example, a block consisting of 7 line pixels), and monitors the output of the quantization circuit 4 so that the quantization level in the block is all zero (that is, the quantization representative When the values are all zero), this is an invalid block,
Only 1 bit of block identification information is transmitted. The other blocks are treated as valid blocks, and following one bit of block identification information, a variable length code for all pixels in the block is output.

This variable length code is assigned in advance according to the probability of occurrence of the quantization level. The output of the variable length encoding circuit 8 is time-division multiplexed with other signals in a multiplexing circuit 9, smoothed in speed in a buffer memory 10, and sent to an upstream transmission line 14 via an encoded data output terminal 11. When the amount of information stored in the buffer memory 10 increases and is likely to overflow, the characteristics of the quantization circuit 4 are controlled to be roughened, for example, to compress the amount of information generated thereafter. Many.

The signals multiplexed in the multiplexed circuit 9 include, in addition to the output of the variable length encoding circuit 8, the output of the clock generation circuit 13, the output of the frame memory 7, the output of the refresh control circuit 15-7, and the error detection circuit 28. This is the output of The clock generation circuit 13 receives a video signal input from the video signal input terminal 12 (an analog video signal when the device uses an analog video signal as an input signal, and a digital video signal when the device uses a digital video signal as an input signal). A video synchronizing signal, such as a horizontal synchronizing signal, is extracted from the video synchronizing signal, and a sampling clock whose phase is synchronized with this signal and various clocks necessary for encoding are generated and supplied to each circuit. Further, sampling clock information necessary for regenerating the sampling clock on the receiving side of the communication partner is supplied to the multiplexing circuit 9, where it is multiplexed and transmitted to the receiving side. The frame memory 7 is divided into blocks of a predetermined size, for example, blocks of every seven lines, and parity information of the input signal of the frame memory 7 is calculated for each block, and the obtained parity information is sent to the multiplexing circuit 9. This parity information is transmitted to the receiving side to detect errors. The refresh control circuit 15 is a circuit that separates a refresh request signal sent from the communication partner via the downlink transmission path 17 requesting that the contents of the frame memory 7 be refreshed when an error is detected on the receiving side of the communication partner. Based on this signal, the switch 3 is controlled to connect the output of the one-pixel delay circuit 6. As a result, the encoding method becomes an intra-frame previous value prediction method, and the locally decoded signal obtained without using the output of the frame memory 7, that is, the output of the adder circuit 5, is written to the frame memory 7. Refresh content. In addition, the refresh control circuit 15 outputs forced intra-frame encoding mode information in order to convey the refreshed block of the contents of the frame memory 7 to the receiving side, which is multiplexed in the multiplexing circuit 9 and transmitted. The multiplexing circuit 9 also multiplexes the output of an error detection circuit 28, which will be described later.

On the receiving side, data input from the encoded data input terminal 18 is converted into a decoding rate in the buffer memory 19, and separated into various signals in the separation circuit 20. Of the separated signals, sampling clock information is supplied to a clock regeneration circuit 21, where a sampling clock having the same frequency as that of the transmission side of the communication partner is regenerated and supplied to each circuit required for decoding.

After the variable length encoded data is separated by the 1-separation circuit 20,
It is converted into the quantized representative value in the variable length decoding circuit 22, and added to the output of the switch 24, that is, the prediction signal, in the adder circuit 23 to become a decoded signal, which is sent to the video signal output terminal 27, the 1-pixel delay circuit 25, and the frame memory 26.
is output to.

Further, parity information calculated in the transmission side frame memory (corresponding to 7) of the communication partner and sent via the downlink transmission path 17 is separated by the separation port +l&20 and supplied to the error detection circuit 28. Parity information on the receiving side is stored in the frame memory 26 for the input signal. The parity information of both the transmitting section and the receiving section thus obtained is collated in the error detection circuit 28. If an error occurs, there will be a mismatch in the verification results, and as a result, a refresh request signal is generated to refresh the contents of the frame memory, is multiplexed in the multiplexing circuit 9, and sent to the communication partner via the uplink transmission path 14. transmitted to. In response to this refresh request, the forced intra-frame encoding mode information transmitted on the transmitting side of the communication partner is separated in the separation circuit 20, and the switch 24 is controlled to connect the output of the 1-pixel delay circuit 25, and the forced intra-frame encoding mode information is also forced on the receiving side. Intraframe decoding is performed.

The decoded signal obtained as a result is written to the frame memory 26, so that the communication partner's transmitting side frame memory (
7), and the effects of errors are removed.

Next, the configuration of the error detection circuit 28, which is a feature of the present invention, will be explained. FIG. 2 shows an embodiment of the error detection circuit 28, in which 5], 52 is a register, 53 is a comparison circuit, 54,
57 is a switching circuit, 55 is a memory, 56 and 58 are counters, and 59 is a refresh release level terminal. The register 51 calculates the transmission side frame memory (corresponding to 7) of the communication partner, which is supplied from the separation circuit 20, and outputs the downlink transmission path 1.
The parity information sent via 7 is stored. The register 52 stores parity information calculated by the frame memory 26. Both parity information is the parity information for the frame memory input signal in the same block that is agreed upon during transmission and reception, and is the 8 parity information calculated for each bit plane for the pixel value expressed by 8 bits per pixel. It may be information, or it may be one piece of parity information calculated for the entire 8 bits. Both registers 5
1.52 is an error detection block clock supplied from the clock generation circuit 21 and operates simultaneously.

Comparison circuit 53 compares the outputs of both registers 51 and 52.

As a result, if there is a code error, a mismatch occurs, and a refresh request level is generated to eliminate the influence of the error. This level signal is written into the memory 55 via the switching circuit 54. The write address at this time is supplied via the counter 56 based on the output of the clock recovery circuit z1.

On the other hand, the read address is supplied from the counter 58.

The counter 58 counts the error detection block clock supplied from the transmission side clock generation circuit 13. By this read operation, the previously written refresh request level is read out and sent to the multiplex circuit 9 as a refresh request level signal. When the output level of the memory 55 is the refresh request level, immediately after reading, the switching circuit 54 is controlled to connect the refresh cancel level terminal 59 as input data to the memory 55, and the switching circuit 57 is also controlled. The output of the counter 58 is stored in the memory 5.
By connecting as the write address of 5, the contents of the memory 55 are rewritten to the refresh release level. Alternatively, it is also possible to wait for the frame memory 26 to be refreshed and the contents of the memory 55 to be automatically rewritten to the refresh release level without performing this rewriting operation.

In this case, the switching circuits 54 and 57 are unnecessary.

Next, the multiplex signal format in the multiplex circuit 9, which is another feature of the present invention, will be explained.

FIG. 3 represents the multiple signal format. In FIG. 3, B is a block unique word that is transmitted to identify the screen position of encoded data encoded on the transmitting side;
and encoding mode information for identifying whether the block was processed in interframe encoding mode or in forced intraframe encoding mode to refresh the frame memory. R is a refresh request signal, which is a signal for requesting the communication partner to refresh the contents of the receiving side frame memory 26 for the block number. For example, when R is 110 II, refresh is requested, and when R is 11'', it is not requested. ■ is coded data on the transmitting side.

The communication partner that receives this refresh request signal R controls a switch (corresponding to 3) in the device to perform processing in the forced intra-frame encoding mode and refresh the contents of the frame memory of the block.

At this time, the refresh request level may be sent to a plurality of blocks per frame of video depending on the number of blocks with code errors. In response to the refresh requests for a plurality of blocks, refresh processing is performed as many times as there are blocks that can be refreshed per frame.

In the above explanation, a method was described in which the memory 55 was implemented as a random access memory, but it is clear that it can be implemented as a shift register type memory.

The above explanation describes the interframe coding method, but it can be applied not only to this method, but also to interframe coding methods that introduce motion compensation prediction and background prediction. It is clear that this method can also be applied to encoding methods.

Furthermore, in this explanation, we have described a method of refreshing the frame memory using the intra-frame previous value DPCM method. It is clear that the refresh can be performed using the encoding scheme.

(Effects of the Invention) As explained above, regarding the method of transmitting a refresh request signal for a block in which a transmission path code error has occurred, the refresh request signal is transmitted in an asynchronous manner in terms of frequency without transmitting the on-screen address of the block in which the error has occurred. Since the block unique word in the video frame of the directional line is used to notify the communication partner of the address of the block in which the error has occurred, there is an advantage that transmission of the refresh request signal is facilitated.

Further, since only the refresh request signal is transmitted without transmitting the address signal itself, there is an advantage that the information fee for requesting refresh can be reduced to 177 to 1/9.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, FIG. 2 shows an embodiment of an error detection circuit, and FIG. 3 shows a multiplex signal format in a multiplex circuit. 1-m-input terminal for digitized video signal, 2
-m-subtraction circuit, 3.24-m-switch, 4
-m-quantization circuit, 5.23-m-addition circuit, 6
．． 25---1 pixel delay circuit, 7.26---Frame memory, 8-m-Variable length encoding circuit, -17--Heji9-m-Multiple circuit, 10.19---Buffer memory, 11-m-encoded data output terminal, 12-m-video signal input terminal, 13-m-clock generation circuit, 14--J nili transmission line, 15-m-refresh control circuit, 17--downward transmission 18-m-encoded data input terminal, 20-m-separation circuit, 21-m-clock recovery circuit, 22-m-variable length decoding circuit, 27--output terminal for digitized video signal. ,
28-11 error detection circuit, 51.52-m-register, 53-m-comparison circuit, 54, 57--
Switching circuit, 55--Memory, 56, 58-
m-counter, 59-m-refresh release level terminal.

Claims (1)

[Claims] In a two-way video communication system in which a plurality of terminals perform communication by mutually transmitting and receiving two-way video signals, (a) a transmitting unit of an image signal encoding/decoding device on one terminal side; a storage circuit that stores a predicted signal for an input image signal that has been digitized; a circuit that encodes a relative value between the input image signal and the predicted signal;
A time division multiplexing circuit divides each block into blocks each consisting of pixels (m and n are positive integers) and time division multiplexes block information representing the position of each block in the screen and encoded data in the block. (b) a circuit in which the receiving unit receives encoded video signal data sent from a communication partner in the two-way video communication system and separates the encoded data into block information and encoded data; and a prediction signal. a decoding circuit that reproduces an image signal by decoding the encoded data supplied from the separation circuit and adding it to the output of the storage circuit;
Detects the presence or absence of code errors in the decoded signal for each block,
(c) means for generating a refresh request signal for a block containing an error; An image signal encoding/decoding device characterized in that when the refresh request signal matches an address, the refresh request signal is transmitted as command information in a transmission block.