JPS61269438A - Signal multiplexing receiver - Google Patents

Abstract

PURPOSE:To increase the number of transmittable and receivable signals without increasing the number of channels of series/parallel conversion by comparing an address in a received signal and a fixed address inputted to an address terminal, and outputting the data of m bits only when both addresses are coincident with each other. CONSTITUTION:Optical multiplexing signals transmitted through an optical fiber 5 come into a receiver continuously such as A1, D1, A2, D2, A3, D3, A4, D4.... The same signals A1, D1 are inputted to receivers A, B, C. An address A1 is compared with fixed addresses La, Lb, Lc of the receivers. Out of these addresses only one is equal to the address A1. An address terminal 4 is connected to La, Lb, Lc, and the data of m bits are outputted to the outside from a data terminal 3 only when this and address A1 coincide. For instance, supposing that A1=Lc, the data of m bits are outputted from the data terminal of the receiving circuit C. The data are not outputted from other receiving circuits A, B, and cleared. In this way, three kinds of addresses and accompanying three kinds of signal data can be received.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a signal multiplex receiver used in an optical multiplex transmission system.

A receiving device of an optical multiplex transmission system performs photoelectrical conversion and serial/parallel conversion of a digital signal sent through an optical fiber.

Photoelectric conversion is done by photodiodes.

The photocurrent is amplified and binarized compared to a threshold value.

The binarized digital signal is a multiplexed signal. This is subjected to serial-to-parallel conversion (serial/parallel conversion). Then you will get parallel signals.

(a) Conventional technology and its problems Optical data link [Sumilink-3MFII (trade name)]
The method uses two optical fiber codes to perform optical multiplex communication, and has already been put into practical use.

It combines optical transmitter and receiver circuits into one.

The optical transmitter consists of a parallel-to-serial conversion circuit, an optical transmission circuit, and an LED. The optical receiver consists of a PD1 optical receiving circuit and a last-minute conversion circuit.

The parallel signal input is 16 channels. The data transfer cycle is 4.8$■.

This is useful enough when transmitting and receiving on/off signals such as switches, but if there is a lot of data to be transmitted, 16
Channels are not enough.

←) Purpose The purpose of the present invention is to increase the number of signals that can be transmitted and received without increasing the number of channels for belly drum conversion.

However, the number of bits per signal does not increase just by increasing the number of signal types. Since the number of bits in one signal is 16 bits or less, and there are multiple types of signals instead of just one, an address is attached. It is assumed that one signal consists of an address and data.

FIG. 1 shows one frame of a received signal used in the optical receiver of the present invention. There are a total of n bits (16 bits), of which 4 bits correspond to addresses and m bits correspond to data.

In the conventional optical receiving circuit, there is no address bit, and as shown in FIG. 8, all n bits are data bits, and the same target data is repeatedly sent. Therefore, it is not possible to transmit or receive signals of n bits or more.

2) Configuration FIG. 2 is a configuration diagram of three multiplex receivers of the present invention connected in series.

There are a receiving device A, a receiving device B, and a receiving device C.

This includes a last-minute conversion circuit 2.2.2 that converts a serial signal into a parallel signal. n
It converts a bit (16 bits) serial signal into a parallel signal, and was also provided in conventional optical multiplexing signal equipment.

However, the output pins are slightly different, and among the n-bit bins,
The m bit is a data bit and the l bit is an address bit.

Each receiving circuit A, B1C corresponds to one fixed address. Let this be La1Lb1Lc.

Now, the optical multiplexed signal transmitted from the optical fiber 5 is
One frame consists of n bits), which is a combination of address and data. Ai the address of the first frame
1 data is written as Di.

The optical multiplex signal transmitted through the optical fiber 5 is AID1 M2 B2 All Ds A4 D4°°°
.

These signals are continuously input to the receiving device.

The photoelectric conversion unit 6 is a part that converts an optical signal into an electrical signal, amplifies it, binarizes it, and returns it to a digital pulse signal. If it is modulated in the transmitter, here,
A demodulation circuit is required.

Photodiodes are used to convert optical signals into electrical signals. The photocurrent is amplified. This may be binarized by comparing it with a fixed threshold and dividing it into ■ and 0, or by using a movable threshold and comparing this with the signal level.

The binarized result becomes a digital pulse train.

If the signal is modulated other than the return zero (RZ) signal,
Demodulate this.

In this way, the transmitted digital pulse train AIDIA2D2, . . . appears in the photoelectric conversion unit 6.

First, one frame of AlD is input from the RD terminal to the last-minute conversion circuit 2. The same signal passes through the buffer 7, is amplified or shaped, is output from the RDE terminal, which is an enable terminal, and is input to the RD terminal of the receiving device B at the next stage.

Therefore, the RDE terminal □ of the first-stage receiving device A and the RD terminal of the second-stage receiving device B are connected. Further, the RDE' terminal of the second-stage receiving device B and the RD terminal of the eighth-stage receiving device C are connected (here, only three receiving devices are shown).

However, many receiving devices can be connected.

2.6°,,76°/”7777Ki.,a*m*h
This is because the input of the same signal to the next receiving device at the same time is so small that it can be ignored.

In this way, the same signal A1D1 is input to the receiving devices A and B1G. At1/S A1 is compared with the fixed address La1Lb1Lc of the receiving device. Only one of these is equal to address A1. Address terminal 4 is La1Lb1
The m-bit data is output from the data terminal 3 to the outside only when this and the address A1 match.

For example, assume that A1=Lc. Then, m-bit data is output from the data terminal of the receiving circuit C. No data is output from the other receiving circuits A and B, and the data is cleared.

When the data is output, the next serial data A2D2 comes in in order. The signal enters the three receiving devices almost simultaneously, and the address A2 and the fixed address La1Lb1Lc are compared.

If A2=La. Data D2 from receiving circuit A
is output. No data is output from B and C. It will be cleared when the next signal comes in.

In this way, three types of addresses and three associated
It is possible to receive various types of signal data.

No matter how many bits the original signal has, it can be transmitted and received as long as it is 3m bits or less.

Since the receiving circuits A1B and A1C have an order, these output data are connected to form one n'
You can get a bit signal.

(n<n'<am).

More generally, since the address is l bits, 24 signals can be distinguished. Therefore, 21 receiving devices are also connected in series. The connections are in series, but, as already mentioned, functionally in parallel.

You will get 24 signals, so if you connect them in order,
It is possible to transmit and receive parallel signals of maximum (mX2') bits.

In this way, the total number of data bits received by the receiving device can be expanded.

This circuit can be used in exactly the same way as a conventional receiver. As shown in FIG. 3, there is a case where the n-bit frame is all data bits (n"ml). In this case, one receiving device is used.

No address is required. Terminal 4 of address bit l is now used as a data terminal.

Therefore, the terminals for 1 pits are used bidirectionally as data address terminals. As the address terminal, the second
It can be used as shown in the figure, or it can be used as a data terminal.
It can also be used as the same as a conventional receiving circuit.

FIG. 4 is a block diagram of such a receiving device 1. As shown in FIG.

To switch the data address terminal 40 function, the AD
Provide a terminal. By switching AD HIL, the specification is switched to the extended specification or the independent specification.

When AD=H level, it becomes extended specification.

At this time, the l pit functions as an address terminal as shown in FIG. 2, and the fixed address L is compared with the input address A, and when they are the same, data D is output. In other words, the l-bit address/data terminal 4 becomes an input state and acts as an address terminal.

When AD=L level, it becomes independent specification. At this time, the data address terminal 4 for 1 pit functions as a data terminal. There is no such thing as a fixed address, and entering a fixed address is prohibited. Therefore, there is no comparison between a fixed address and an input address. All n bits of the input signal are data signals, and this is input to the single receiving device 1. Here, only serial lv/parallel conversion is performed, and all para-V)v signals are output from the receiving device 1 at the same time.

In the above-mentioned devices, the address length is fixed.

Since 1 bit is used as an address, 21 addresses can be specified and a maximum of 21 receiving devices can be connected. However, you may not always need this many addresses.

In this case, if the address length is fixed, there will be a lot of waste.
That's what it means.

For example, when two receiving devices are connected in a one-stage extension, the address can in principle be 1 bit (l=1). In this case, if the address length is l>1, there is too much room for address bits, and (l-1) bits are wasted. This cannot be used immediately as a data bit. The remaining (l-1) may be used as data bits.

Therefore, consider making the address length variable.

FIG. 5 shows an example in which the address length is variable.

In the one shown in FIG. 4, whether the entire address of 1 pixel is used as an address or as data is specified by AD=H or AD=L.

The receiving device 1 is configured by setting the maximum bit of the address to l, and setting the address length to an arbitrary number from 0 to l. Therefore, in the example shown in FIG. 5, two addressing terminals are provided. ADl, AD21.・It is ADk. l =
2, the address length can be changed to ol 1.2, . . . l using k addressing terminals.

If the type of address length matches 2, or 2 is larger, such a specification can be made. The number of addresses may be in 2 increments instead of 1 increments, such as 0, ■, 2, . . . l. In other words, the address length changes to 012.4.6, . . . . The same is true in the case of .

For example, let the address length be 012.4.6. in this case,
It is sufficient to have two addressing terminals AD1 and AD2.

FIG. 6 shows such an example. The leftmost □ column shows the values of address designation terminals AD1 and AD2. The second column shows the corresponding address length l. The third column is the data length. This is obtained from n=16, n=m+#. The rightmost column shows the format of one frame. The shaded area is the address bit.

(3) Effects (1) The number of bits of a receivable signal can be expanded arbitrarily. The number of receivable bits can be expanded simply by connecting the same receiving devices in series without requiring an external circuit.

(2) Miniaturization and cost reduction are possible. This is because there is no need to create an external circuit, just connect the same components.

(3) It is easy for users to use. This is because no external circuit is required.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a received signal of n bits, in which l bits are used as address bits and m bits are used as data bits. FIG. 2 is an explanatory diagram of the use of three multiple receivers of the present invention connected in series. FIG. 8 is an explanatory diagram showing an example in which all n pits are data bits, which is the same as the conventional one. FIG. 4 is an explanatory diagram showing that the AD terminal can be switched to a data terminal and an address terminal. FIG. 5 is a configuration diagram of a multiplex reception device for making the address length variable. FIG. 6 is an explanatory diagram showing two address designating terminals AD1 and AD2, address length, and format. 1... Receiving device 2... Heavy duty conversion circuit 3... Data terminal 4... Data address terminal 5...
・Optical fiber 6...Photoelectric conversion section inventor Sugimoto
Tetsuo Kobayashi Yoshinobu

Claims (2)

[Claims] (1) In a signal multiplexing device that receives one frame of a bit serial signal including a multiplexed n-bit signal, performs serial-to-parallel conversion and outputs it as a parallel signal, l bits of the n-bit serial signal are When the address and m bits are data, the signal multiplex receiver has an RD terminal for receiving the serial signal, an extended output RDE terminal that outputs this signal as it is, an l-bit address terminal and m-bit data. When it receives one frame of serial signal, it compares the address in the received signal with the fixed address input to the address terminal, and outputs m-bit data only when the two match. A signal multiplex reception device characterized by the following features. (2) Of the n-bit input/output terminals of the receiving device, l bits are bidirectional terminals that can output data or input addresses, and k address designation terminals AD_1...AD_k The signal multiplex reception device according to claim 1, wherein the number of address terminals is specified by.