JPS61264444A - Data processing system for central processing unit - Google Patents

Abstract

PURPOSE:To attain the processing to reset a CPU in its normal state by utilizing the contents of a memory as the data having meaning even in case the CPU gives an access to a memory address where no program code exists owing to a malfunction. CONSTITUTION:The programs are stored in the memory addresses A-B in a program map shown here and no program code exists in the areas after the address B. Thus the normal types of EPROM are all set at '1'. In other words, the data (FF)16 is stored. In case a CPU gives an access to an area larger than the address B owing to a malfunction, the CPU executes the data (FF)16 in the form of an instruction code and has a jump to a memory address (3C)16. Here a processing routine is set previously in the address (3C)16 to reset the normal execution processing. This prevents the CPU runaway.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system for a central processing unit to be implemented next to prevent runaway of the central processing unit.

[Conventional technology]

FIG. 3 is a block connection diagram showing the relationship between the central processing unit of a conventionally used computer and a read-only memory for storing programs. In the figure, 1 is the central processing unit (hereinafter referred to as CPU), and 2 is In the read-only memory (hereinafter referred to as ROM), 3 is an address bus, and 4 is a data bus, and the CPU 1 and ROM 2 are connected by the address bus 3 and the data bus 4.

Next, the operation will be explained. ROM 2 stores programs to be executed by CPU 1, and C
The PU 1 outputs a memory address via the address bus 3, takes in the program code in the ROM 2 at this address via the data bus 4, decodes and executes the instructions of the program code.

The size of the program stored in the 17tXROM2 falls within the accessible address space. A conceptual diagram of the memory map of the ROM 2 is shown in FIG. In the figure, 28 is an area where the contents of the program body are written, and 26 is an empty area that contains meaningless data unrelated to the program code. Here, if the data bus 4 in Figure 3 is pulled up to the power supply voltage, all the data bits are "1", so this data will have a value such as (FF n 1. Set.

[Problem that the invention seeks to solve]

The conventional data processing method with CPU 1 and ROM 2 is as described above, so if CPU 1 accesses a memory address where the program code does not exist due to external noise etc., this will be an unexpected instruction. The problem is that the CPU 1 stops working properly when the code is decoded and executed, causing a runaway operation.

This invention was made in order to solve the above-mentioned problems, and the CPU 1 accesses a memory address where no program code exists, decodes data that is not an instruction code of the original program as a program code,
It is an object of the present invention to obtain a data processing method that can prevent the CPU 1 from running out of control even when executed.

[Means for solving problems]

The data processing method of the central processing unit according to the present invention is such that when the central processing unit mistakenly accesses an unwritten address other than the memory address where the program code stored in the read-only memory exists, the read-only memory The output data in the unwritten state, which is uniquely determined by the above, is interpreted by the central processing unit as a program code, thereby causing the ninth routine to return to normal processing to be executed.

[Effect]

The data processing method of the central processing unit in this invention accesses a memory address where no program code exists, uses the data of the program code at this address as meaningful data, and thereby returns to the central processing unit normally. This function is to prevent the central processing unit from running out of control.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Regarding this embodiment, as soon as it has been explained, in addition to the block connection diagram shown in Fig. 3, the program map shown in Fig. 1 and the
The flowchart in the figure will be described. Further, in this embodiment, an 8080 series CPU is used as the CPU 1. 1st
In the program map shown in the figure, programs are stored from memory address A to memory address B.

In other words, there is no program code in a large area other than the memory address, but if the data bus 4 is pre-upped to the power supply voltage as described in 5 above, a normal EPROM can be erased normally. Since the memory data output of is completely ``1'', CPU 1 can recognize all data bits as ``1''.
All areas without program code should be filled with the above (F)
F) Data called xs is stored.

Here, if the address value to be accessed changes due to noise, etc., and the above memory address = 5 contains a program code larger than B, and the address of the area is accessed, the CPU will (FF
)xs data instruction code. (FF
)□, the instruction code is, for example, 8080/8085.
In the CPU, this corresponds to a new mnemonic code called R8T7, and is one of the hardware interrupt instructions. This instruction code causes the 8080/8085 CPU to call memory address (3C) 16.

Therefore, this CPU has instruction code (FF) 1. Then, if you execute this instruction at memory address (3C) 1. If the programmer places a processing routine in advance that returns to the normal execution process before the change was made to this location, a runaway can be prevented.

Next, the process and production as described above is shown in the flowchart of FIG. While the program at the memory address shown in Figure 1 is being executed, an address value that has been changed due to noise or the like is accessed (assuming that this address value is greater than B), and the instruction code (FFLm) is executed. (3C) □ 6 (step ■). Since a processing routine for returning to normal processing is placed in memory address (3C) 1 in advance, CPU 1 steps to execute this processing routine. ■ Return to normal processing.

Note that in the above embodiment, 8-bit system 8080/8Q85 is used.
In the CPU, all data in memory addresses where no instruction code of the program in ROAi exists (FP)
□. We talk about the case where the ratio is, and the value of this data is (
If it is other than FF)*a, all data in this unused memory address may be set to (FF)us before processing the original program.

However, although the above embodiment describes the case where an 8080/8085 CPU is used, it can also be applied to other 8-bit CPUs and 16-bit CPHs.

〔Effect of the invention〕

To solve the above problem, according to the present invention, even when the CPU accesses a memory address where no program code originally exists due to a malfunction, a processing routine is executed to return the program code at that memory address to normal processing. Since I decided to use it as an object, the CPU
This has the effect of reliably preventing runaway data and allowing normal data processing to continue.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of a memory map stored in a read-only memory for implementing a data processing method according to an embodiment of the present invention, FIG. 2 is a flowchart for implementing a data processing method, and FIG. FIG. 4 is a block connection diagram showing the relationship between a central processing unit and a read-only memory used in the prior art and the implementation of the present invention. FIG. 4 is a conceptual diagram of a conventional memory map. 1 is the central processing unit t (CPU), 2 is the read-only memory (ROM), A and B are memory addresses, (3C)□6
is a memory address.

Claims (1)

[Claims] In a data processing method of a central processing unit in which a central processing unit outputs a memory address to a read-only memory for program storage, and reads a program code corresponding to this memory address to decode and execute instructions, the central processing unit outputs a memory address to a read-only memory for storing a program. When an unwritten address other than the memory address where the program code stored in the read-only memory is accessed by mistake, the output data in the unwritten state uniquely determined by the read-only memory is used as the program code in the center above. A data processing method for a central processing unit that causes the processing unit to execute a routine to return to normal processing.