JPS61263251A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a large capacity value by forming two pectinated electrodes electrically separated by the same wiring layers, and constructing to oppose the sides of the electrodes through a dielectric film, thereby reducing an occupying area of a capacity element. CONSTITUTION:A lower layer electrode 2 is formed on the surface of an insulating film 1 formed on the surface of a semiconductor substrate 9, and an interlayer insulating film 3 is coated thereon. The film 3 becomes a dielectric in case of forming a capacity. Then, a hole 4 for conducting a part of the upper layer electrode with the electrode 2 is formed at the film 3. Thereafter, an upper layer film of aluminum is coated, the upper layer film is pectinated to form an upper layer electrode 6 in which upper and lower layer electrode 5, 2 are electrically connected. Subsequently, a protective insulating film 8 of approx. thickness of the electrodes 5, 6 is coated. The film 8 becomes a dielectric of a chip protective film and a capacity element to complete the capacity element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a capacitive element.

[Conventional technology]

Conventionally, a capacitive element formed in a semiconductor device is generally l! It has the structure shown in Figures 3(a) and 3(b).

That is, as shown in FIGS. 3(a) and 3(b), the upper layer electrode 15 is removed on the interlayer insulating film 3 provided on the lower layer electrode 2, and then the entire semiconductor element protection insulation 11II8 is removed to form a capacitive element. had a parallel plate structure. Figures 1 and 3 (
a), (b) In the IC, 9 is a semiconductor substrate, and 1 is an insulating film.

[Problems that the invention helps solve]

However, the value of the capacitance of the parallel plate capacitive element formed in this way depends on the material and thickness of the interlayer insulating film 3 as a dielectric, and the area of the bulk part between the T1 electrode 2 and the upper skin lightning pole 15. is proportional to. Therefore, in order to form a capacitive element with a large capacity while keeping the thickness of the interlayer insulating film 3 constant, the area of the lower layer electrode 2 and the upper layer electrode 15 must be increased considerably, and the area of the capacitive element occupying the semiconductor device increases. The drawback is that the larger the semiconductor device becomes, the larger the semiconductor device becomes.
An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a semiconductor device 11t that occupies a small area of the semiconductor device, and includes a capacitive element that has a large capacitance value. It is about providing.

[Means for solving problems]

A semiconductor device according to the present invention has a capacitive element formed by a combination of wiring layers, in which the same wiring layer has two electrically separated comb-shaped electrodes. The side surfaces of the rectangular electrodes face each other with the current-visitor film interposed therebetween.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail using the oral surface.

FIGS. 1(a) and 1(bl) are a plan view and a sectional view along A' of an embodiment of the present invention.

A lower electrode 2t made of A4 film or the like is formed on the surface of the insulating film 1 formed on the surface of the semiconductor substrate 9 by a known method, and an interlayer insulating film 3t having a thickness of 1.0 to 1.5 μm is formed thereon. −
to adhere to. Note that this interlayer insulating film 3 is a film that becomes a dielectric when forming a capacitor. Next, an opening 4t is formed in the interlayer insulating film 3 for electrical connection with the -g5 total 5 electrodes 2 of the upper layer electrode. Thereafter, an upper layer film made of HT or the like with a thickness of approximately 15 μm was deposited by a known method, and the upper layer film was processed into a comb shape, and the independent upper layer electrode 5 was electrically connected to the lower layer electrode 2. An upper layer electrode 6 is formed.

Incidentally, the distance 7 between the opposing upper surface parts of the independent upper layer electrode 5, the lower layer electrode, and the electrically transparent upper layer electrode 6 increases the capacitance value even if the thickness area of the interlayer insulating film 3 is also reduced. The effect will be greater.

Subsequently, a protective insulating film of 8 gold is deposited to a thickness similar to that of the upper electrode 5.6. This insulating lBI3 becomes a dielectric between the chip protection film and the capacitive element, and the 'fLt element having the structure of the present invention extracts light.

According to this embodiment configured in this manner, in addition to the first vertical capacitance, there is a lateral capacitance between the upper layer electrode 5 and the upper layer electrode 6 which are electrically connected to the lower layer electrode.

The capacitive element in this embodiment is formed so that the lateral area of the upper layer electrode 5 is larger than that of a capacitive element with a conventional structure in which the capacitance value increases in proportion to the combined area of the upper layer electrode and the lower layer electrode. Because of this, the effect of spreading the electric lines of force is large.

Therefore, the vertical capacitance in this embodiment is larger than that of a capacitive element of the conventional structure having the same capacitive element area.

Regarding the lateral capacitance, the distance 7 between the opposing side surfaces of the independent upper layer electrode 5 and the upper layer electrode 6 electrically connected to the lower layer electrode 2 is determined by the processing accuracy during pattern formation, but the minimum distance is Since it can be formed, it has a large lateral capacity.

- Regarding the vertical capacitance, since the interlayer insulating film 3 used as a dielectric forming the capacitive element also serves as insulation between the lower layer wiring 2 and the upper layer wiring 5.6, the capacitance value of the capacitive element can be increased. Therefore, if the inter-glabellar insulating film 3 is made thinner, the parasitic capacitance of the wiring system will increase, which will adversely affect the electrical characteristics. Unfavorable electrical characteristics.

As described above, according to the capacitive element structure of this embodiment, the upper layer electrode 6 electrically connected to the lower layer electrode 2 in the horizontal upper layer electrode structure can be formed without changing the thickness of the vertical interlayer insulating film 3. The distance 7 between the side surface of the upper layer electrode 5 and the side surface of the independent upper layer electrode 5
Since the capacity can be made small, the capacity in the horizontal direction can be much larger than the capacity in the vertical direction. Therefore, the total of the vertical capacitance and the lateral capacitance is larger than the capacitance of the parallel plate type of the conventional structure for the same area.

As a result, according to this embodiment, a large capacitance element can be formed in a small area without increasing the parasitic capacitance of the wiring capacitance, and the proportion of the capacitor element in the semiconductor device can be extremely reduced.

Next, an embodiment of the present invention in a three-layer structure using a diffusion layer will be described with reference to the drawings.

FIG. 2(a), Φ) is a plan view and a BB' sectional view of another embodiment of the present invention.

Summary 2 As shown in (a) and (b), impurities of opposite conductivity type are introduced onto the semiconductor substrate 9 by a known method to form the diffusion layer electrode 20. Next, insulate the entire surface [1- Form the intermediate layer! An opening 4ai is formed in the insulating film 1 to make a part of the pole conductive to the diffusion layer electrode 20. Next, by the known method 1c, an intermediate layer electrode film made of an At film is coated and added in a comb shape to form an independent intermediate layer electrode 24 and a diffusion layer electrode 20.
An intermediate layer electrode 25 is formed which is electrically connected to the intermediate layer electrode 25.

Next, after an interlayer insulating film 3 having a thickness of 1.0 to 1.5 μm is deposited, an opening 4bt is formed for electrically connecting the upper layer electrode and the intermediate layer electrode 25. Thereafter, an upper layer film is deposited to a thickness of about 1.5 .mu.m by a known method and processed into a desired shape to form the upper layer electrode 26. After that, the thickness is about 0.
A protective insulating film 8t having a thickness of 5 μm is deposited to complete the capacitive element having the structure of the present invention. In this case, the insulating film 1 and the interlayer insulating film 3 act as a dielectric.

According to this embodiment, since the vertical capacitance is formed by the intermediate layer electrode 241'&tl independent of the diffusion layer electrode 20, and the double edge between the intermediate layer electrode 24 and the upper layer electrode 26, as shown in FIG.
It is possible to form a capacitive element with a larger capacity in a smaller area than in the embodiment structures shown in a) and (b).

〔Effect of the invention〕

As explained in detail above, according to the present invention, the upper layer electrode is formed into an electrically separated comb shape, and the -10,000 electrodes are connected to the lower layer electrode to increase the area of the charge storage portion. Since a semiconductor device including a capacitive element with a large capacity in a small area can be obtained, it is highly effective in increasing the density and integration of semiconductor devices.

[Brief explanation of drawings]

IEI diagrams (al, (bl) are a top view and a sectional view of one embodiment of the present invention, FIG. 2 (al), (b) are a top view and a sectional view of another embodiment of the present invention, and (l!3) a) and Φ) are a top view and a cross-sectional view of a conventional capacitive element. 1... Insulating film, 2... Lower layer electrode, 3.
・・・・・・Interlayer insulation film, 4.4am 4b・・・・・・
Opening portion, 5...Independent upper layer electrode, 6...
... Upper layer electrode, 7 ... Spacing, 8 ... Protective JIFX, 9 ... Semiconductor substrate, 15.
... Upper layer electrode, 20 ... Diffusion layer electrode, 2
4...Independent intermediate layer electrode, 25...
Intermediate layer electrode, 26... Upper layer electrode. Agent Patent Attorney Nai-MW ■゛゛ゝ, Mine 1 Sanmine Z times

Claims (1)

[Claims] In a semiconductor device having a multilayer wiring structure and having a capacitive element formed by a combination of wiring layers, the same wiring layer forms two electrically separated comb-shaped electrodes, and the side surfaces of the comb-shaped electrodes are dielectric. A semiconductor device characterized in that the semiconductor devices are configured to face each other with body membranes in between.