JPS6126267A - Bidirectional zener diode - Google Patents
Bidirectional zener diodeInfo
- Publication number
- JPS6126267A JPS6126267A JP14823284A JP14823284A JPS6126267A JP S6126267 A JPS6126267 A JP S6126267A JP 14823284 A JP14823284 A JP 14823284A JP 14823284 A JP14823284 A JP 14823284A JP S6126267 A JPS6126267 A JP S6126267A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- diffusion layer
- junction
- semiconductor substrate
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002457 bidirectional effect Effects 0.000 title claims description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 111
- 239000004065 semiconductor Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 5
- 239000008188 pellet Substances 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000011521 glass Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、双方向性ツェナーダイオードに関する。[Detailed description of the invention] <Industrial application field> The present invention relates to bidirectional Zener diodes.
〈従来の技術〉
従来、双方向性ツェナーダイオードは、第３図に示され
るように、通常の単方向性ツェナーダイオードの半導体
ペレット１，１を２つ背中合わせにしてガラス管２内に
デュメット線３，３にて封入して製作するか、あるいは
、第４図に示されるように、ウェーハ両面に同一の拡散
深さ、濃度、即ち、同一のパターンの拡散層を形成して
双方向性ツェナーダイオードの半導体ペレット５を製遺
し、この半導体ベレッＦ５をガラス管内にデュメット線
で封入して製作している。<Prior Art> Conventionally, a bidirectional Zener diode has been manufactured by placing two semiconductor pellets 1, 1 of a normal unidirectional Zener diode back to back and inserting a dumet wire 3 into a glass tube 2, as shown in FIG. , 3, or by forming diffusion layers with the same diffusion depth and concentration, that is, the same pattern, on both sides of the wafer, as shown in FIG. The semiconductor pellet F5 is manufactured by sealing the semiconductor pellet F5 in a glass tube with a dumet wire.
ところが、前者は１つの双方向性ツェナーダイオードを
製作するのに２つの半導体ペレットを必要とするために
、製造コストが高くなる等の難点があり、一方、後者は
ウェーハの両面に同一のパターンを精度よく形成しなけ
ればならず、特殊な製造装置および工程を要する等の難
点があった。However, the former method requires two semiconductor pellets to manufacture one bidirectional Zener diode, resulting in high manufacturing costs, while the latter method requires the same pattern on both sides of the wafer. There are drawbacks such as the need to form with high precision and the need for special manufacturing equipment and processes.
なお、第４図において４は半導体基板、６は酸化膜、７
はＰＮ接合用拡散層、８は電極用メタル、９はバンプで
ある。In addition, in FIG. 4, 4 is a semiconductor substrate, 6 is an oxide film, and 7 is a semiconductor substrate.
8 is a diffusion layer for a PN junction, 8 is a metal for an electrode, and 9 is a bump.
このような従来の技術的課題を解決するため、本件発明
者は、昭和５９年６月１５日提出の特許願（１）におい
て、第５図に示されるように半導体基板１１上に、該半
導体基板１１と異なる導電型のエピタキシャル層１２を
形成し、このエピタキシャル層１２の周縁部に半導体基
板１１と同導電型の拡散層１３を半導体基板１１に至る
深さまで形成し、エピタキシャル層１２上に半導体基板
１１と同導電型の第１ＰＮ接合用拡散層１４を形成する
とともに、エピタキシャル層１２と拡散層１３の両層に
またがって半導体基板１１と同導電型の第２ＰＮ接合用
拡散層１５を形成してなる双方向性ツェナーダイオード
を提案し、さらに、昭和５９年６月１５日提出の特許願
（２）において、第６図に示されるように半導体基板１
１上に該半導体基板１１と同導電型のエピタキシャル層
１２を形成し、このエピタキシャル層１２上に半導体基
板１１と異なる導電型の第１拡散層１６を形成し、この
第１拡散層１６上に、該第１拡散層１６との間でＰＮ接
合を形成するための第２拡散層１７を形成するとともに
、エピタキシャル層１２と第１拡散層１６との両層にま
たがって第１拡散層１６との間でＰＮ接合を形成するた
めの第３拡散層１８を形成してなる双方向性ツェナーダ
イオードを提案している。In order to solve such conventional technical problems, the inventor of the present invention, in the patent application (1) filed on June 15, 1980, proposed that the semiconductor An epitaxial layer 12 of a conductivity type different from that of the substrate 11 is formed, a diffusion layer 13 of the same conductivity type as the semiconductor substrate 11 is formed at the peripheral edge of the epitaxial layer 12 to a depth reaching the semiconductor substrate 11, and a semiconductor layer 12 is formed on the epitaxial layer 12. A first PN junction diffusion layer 14 of the same conductivity type as the substrate 11 is formed, and a second PN junction diffusion layer 15 of the same conductivity type as the semiconductor substrate 11 is formed spanning both the epitaxial layer 12 and the diffusion layer 13. In addition, in patent application (2) filed on June 15, 1980, a semiconductor substrate 1 is proposed as shown in FIG.
1, an epitaxial layer 12 of the same conductivity type as the semiconductor substrate 11 is formed, a first diffusion layer 16 of a conductivity type different from that of the semiconductor substrate 11 is formed on the epitaxial layer 12, and a first diffusion layer 16 of a conductivity type different from that of the semiconductor substrate 11 is formed on the first diffusion layer 16. , a second diffusion layer 17 is formed to form a PN junction with the first diffusion layer 16, and a second diffusion layer 17 is formed across both the epitaxial layer 12 and the first diffusion layer 16. A bidirectional Zener diode is proposed in which a third diffusion layer 18 is formed to form a PN junction between the two.
ところが、昭和５９年６月１５日提出の特許願（１）で
提案した双方向性ツェナーダイオードでは、エピタキシ
ャル成長によって形成されるエピタキシャル層１２の濃
度、したがって比抵抗に限界があり、このため、低い耐
圧の双方向性ツェナーダイオードを得ることが困難であ
り、一方、昭和５９年６月１５日提出の特許願（２）で
提案した双方向性ツェナーダイオードでは、ブレークダ
ウンが表面近辺で起こり易しサージに弱いという欠点が
ある。However, in the bidirectional Zener diode proposed in patent application (1) filed on June 15, 1980, there is a limit to the concentration of the epitaxial layer 12 formed by epitaxial growth, and therefore to the specific resistance. On the other hand, in the bidirectional Zener diode proposed in patent application (2) filed on June 15, 1980, breakdown tends to occur near the surface and surges occur. It has the disadvantage of being weak against
〈発明が解決しようとする問題点〉
本発明は、上述の点に鑑みて成されたものであって、特
殊な製造装置および製造工程を要せず、低い耐圧で、し
かも、サージに強い安定した双方向性ツェナーダイオー
ドを得ることを目的とする。<Problems to be Solved by the Invention> The present invention has been made in view of the above-mentioned points. The purpose of this study is to obtain a bidirectional Zener diode.
〈問題点を解決するための手段〉
本発明は、上述の目的を達成するために、半導体基板上
に、該半導体基板と異なる導電型のエピタキシャル層が
形成され、該エピタキシャル層の周縁部に前記半導体基
板と同導電型の拡散層が、半導体基板に至る深さまで形
成され、前記エピタキシャル層には、半導体基板と異な
る導電型の第１拡散層が形成されるとともに、前記拡散
層の近傍に半導体基板と異なる導電型の第２拡散層が形
成され、前記第１拡散層に、半導体基板と同導電型の第
１ＰＮ接合用拡散層が、該第１拡散層よりも浅く形成さ
れ、前記第２拡散層、エピタキシャル層および前記拡散
層の３層にまたがって半導体基板と同導電型の第２ＰＮ
接合用拡散層が、該第２拡散層よりも浅く形成されてい
る。<Means for Solving the Problems> In order to achieve the above-mentioned object, the present invention provides that an epitaxial layer having a conductivity type different from that of the semiconductor substrate is formed on a semiconductor substrate, and the epitaxial layer is formed on the peripheral edge of the epitaxial layer. A diffusion layer of the same conductivity type as the semiconductor substrate is formed to a depth reaching the semiconductor substrate, and a first diffusion layer of a conductivity type different from that of the semiconductor substrate is formed in the epitaxial layer, and a semiconductor layer is formed in the vicinity of the diffusion layer. A second diffusion layer of a conductivity type different from that of the substrate is formed, a first PN junction diffusion layer of the same conductivity type as the semiconductor substrate is formed shallower than the first diffusion layer, and the second diffusion layer has a conductivity type different from that of the substrate. A second PN of the same conductivity type as the semiconductor substrate is spread over the three layers of the diffusion layer, the epitaxial layer, and the diffusion layer.
A bonding diffusion layer is formed shallower than the second diffusion layer.
〈実施例〉
以下、図面によって本発明の実施例について詳細に説明
する。第１図は本発明の一実施例の構造断面図である。<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a structural sectional view of one embodiment of the present invention.
この実施例の双方向性ツェナーダイオ−Ｖの半導体ベレ
ット２０は、Ｐ型のシリコン基板のような半導体基板２
１上に、この半導体基板２１と異なる導電型、即ちＮ型
のエピタキシャル層２２を成長させ、さらに、エピタキ
シャル層２２の周縁部に半導体基板２１と同導電型であ
るＰ型の拡散層２３が半導体基板２１に達する深さまで
拡散形成される。The semiconductor pellet 20 of the bidirectional Zener diode-V in this embodiment is a semiconductor substrate 2 such as a P-type silicon substrate.
1, an epitaxial layer 22 of a conductivity type different from that of the semiconductor substrate 21, that is, an N type, is grown, and a diffusion layer 23 of a P type, which is of the same conductivity type as the semiconductor substrate 21, is grown on the periphery of the epitaxial layer 22. It is formed by diffusion to a depth that reaches the substrate 21.
エピタキシャル層２２には、また、その中央付近に半導
体基板２１と異なる導電型であるＮ型の第１拡散層２４
が形成されるとともに、エピタキシャル層２２の周縁部
の前記拡散層２３の近傍に半導体基板２１と異なる導電
型であるＮ型の第２拡散層２５が形成される。第１拡散
層２４には、半導体基板２１と同導電型であるＰ型の第
１ＰＮ接合用拡散層２６が、該第１拡散層２４よりも浅
く拡散形成され、第２拡散層２５、エピタキシャル層２
２および拡散層２３の３層にまたがって半導体基板２１
と同導電型であるＰ型の第２ＰＮ接合用拡散層２７が、
第２拡散層２５よりも浅く形成される。The epitaxial layer 22 also has an N-type first diffusion layer 24 having a conductivity type different from that of the semiconductor substrate 21 near the center thereof.
At the same time, an N-type second diffusion layer 25 having a conductivity type different from that of the semiconductor substrate 21 is formed near the diffusion layer 23 at the peripheral edge of the epitaxial layer 22 . In the first diffusion layer 24, a P-type first PN junction diffusion layer 26 having the same conductivity type as the semiconductor substrate 21 is diffused and formed to be shallower than the first diffusion layer 24, and a second diffusion layer 25, an epitaxial layer 2
The semiconductor substrate 21 is spread over three layers: 2 and the diffusion layer 23.
The second PN junction diffusion layer 27 of P type having the same conductivity type as
It is formed shallower than the second diffusion layer 25.
第１ＰＮ接合用拡散層２６とエピタキシャル層２２との
間のＰＮ接合および第２ＰＮ接合用拡散層２７とエピタ
キシャル層２２との間のＰＮ接合の濃度勾配は、第１Ｐ
Ｎ接合用拡散層２６と第１拡散層２４との間のＰＮ接合
および第２ＰＮ接会用拡散層２７と第２拡散層２５との
間のＰＮ接合の濃度勾配よりも大トくシている。さらに
、半導体基板２１とエピタキシャル層２２との間のＰＮ
接合および拡散層２３とエピタキシャル層２２との間の
ＰＮ接合の濃度勾配は、第１ＰＮ接合用拡散層２６と第
１拡散層２４との間のＰＮ接合および第２ＰＮ接合用拡
散層２７と第２拡散層２５との間のＰＮ接合の濃度勾配
よりも大キ＜シている。The concentration gradient of the PN junction between the first PN junction diffusion layer 26 and the epitaxial layer 22 and the PN junction between the second PN junction diffusion layer 27 and the epitaxial layer 22 is
It is higher than the concentration gradient of the PN junction between the N-junction diffusion layer 26 and the first diffusion layer 24 and the PN junction between the second PN-junction diffusion layer 27 and the second diffusion layer 25. . Furthermore, the PN between the semiconductor substrate 21 and the epitaxial layer 22 is
The concentration gradient of the PN junction between the junction and diffusion layer 23 and the epitaxial layer 22 is the same as that of the PN junction between the first PN junction diffusion layer 26 and the first diffusion layer 24 and between the second PN junction diffusion layer 27 and the second PN junction. It is larger than the concentration gradient of the PN junction with the diffusion layer 25.
これは、後述のように第１ＰＮ接合用拡散層２°６と第
１拡散層２４との間および第２ＰＮ接合用拡散層２７と
第２拡散層２５との間でそれぞれブレークダウンを生じ
させるためである。なお、２８は酸化膜、２９．３０は
電極用メタル、３１はバンブである。This is because breakdown occurs between the first PN junction diffusion layer 2°6 and the first diffusion layer 24 and between the second PN junction diffusion layer 27 and the second diffusion layer 25, as described later. It is. Note that 28 is an oxide film, 29.30 is an electrode metal, and 31 is a bump.
上記構成を有することにより、バンブ３１から電極用メ
タル３０へ電流が流れるときには、第１ＰＮ接合用拡散
層２６と第１拡散層２４とは順方向バイア、又となり、
第２拡散層２５と第２ＰＮ接合用拡散層２７とは逆方向
バイアスとなり、ブレークダウンを生じる。また、電極
用メタル３０からバンプ３１へ電流が流れるときには、
第２ＰＮ接合用拡散層２７と第２拡散層２５は順方向バ
イアスとなり、第１拡散層２４と第１ＰＮ接合用拡散層
２６とは逆方向バイアスとな１）、ブレークダウンを生
じる。With the above configuration, when a current flows from the bump 31 to the electrode metal 30, the first PN junction diffusion layer 26 and the first diffusion layer 24 function as a forward via,
The second diffusion layer 25 and the second PN junction diffusion layer 27 are biased in the opposite direction, causing breakdown. Furthermore, when current flows from the electrode metal 30 to the bump 31,
The second PN junction diffusion layer 27 and the second diffusion layer 25 are forward biased, and the first diffusion layer 24 and the first PN junction diffusion layer 26 are reverse biased (1), causing breakdown.
このように本発明の双方向性ツェナーダイオードは、Ｐ
Ｎ接合を形成する第１．第２拡散層２４゜２５が拡散形
Ｉｉ、されているので、第５図で図示の双方向性ツェナ
ーダイオードのエピタキシャル層１２と異なり、第１Ｉ
第２拡散層２４．２５の比抵抗を低くでき、これによっ
て低い耐圧の双方向性ツェナーダイオードを得ることが
可能となる。また、本発明の双方向性ツェナーダイオ−
目よ、第６図で図示の双方向性ツェナーダイオードと異
なリブレークダウンは、エピタキシャル層２２の内部で
生じるので、サージに強い安定した双方向性ツェナーダ
イオ−Ｖを得ることが可能となる。Thus, the bidirectional Zener diode of the present invention has P
The first step is to form an N junction. Since the second diffusion layers 24 and 25 are of the diffusion type Ii, unlike the epitaxial layer 12 of the bidirectional Zener diode shown in FIG.
The resistivity of the second diffusion layers 24 and 25 can be lowered, thereby making it possible to obtain a bidirectional Zener diode with a low breakdown voltage. Moreover, the bidirectional Zener diode of the present invention
Note that unlike the bidirectional Zener diode shown in FIG. 6, the rebreakdown occurs inside the epitaxial layer 22, making it possible to obtain a stable bidirectional Zener diode V that is strong against surges.
第２図は半導体ペレッ）２０の製造手順を説明するため
の断面図である。まず、Ｐ型の半導体基板２１上にＮ型
のエピタキシャル層２２を成長させ、その表面に酸化膜
２８を形成する。次に７オＦエツチングによって第２図
（Ａ）に示されるように、エピタキシャル層２２の周縁
部に拡散窓を形成する。この拡散窓からＰ型の拡散層２
３を半導体基板２１に至る深さまで拡散形成し、第２図
（Ｂ）に示されるように再び酸化膜２８を形成する。FIG. 2 is a sectional view for explaining the manufacturing procedure of the semiconductor pellet 20. First, an N-type epitaxial layer 22 is grown on a P-type semiconductor substrate 21, and an oxide film 28 is formed on its surface. Next, a diffusion window is formed at the periphery of the epitaxial layer 22 by 7-off etching, as shown in FIG. 2(A). From this diffusion window, the P-type diffusion layer 2
3 is diffused to a depth reaching the semiconductor substrate 21, and an oxide film 28 is again formed as shown in FIG. 2(B).
さらに、第２図（Ｃ）に示されるように７オＦエツチン
グによって第１．第２拡散層２４．２５の形成領域に対
応する箇所に拡散窓を形成する。これ、らの拡散窓から
Ｎ型の第１．第２拡散層２４．２５を拡散形成し、第２
図（Ｉ））に示されるように再び酸化膜２８を形成する
。このように第１．第２拡散層２４．２５を同時に拡散
形成するので、拡散濃度および深さ等を同一にすること
が可能である。Furthermore, as shown in FIG. 2(C), the first . Diffusion windows are formed at locations corresponding to the formation regions of the second diffusion layers 24 and 25. From these diffusion windows, the N-type first . A second diffusion layer 24, 25 is formed by diffusion, and a second diffusion layer 24, 25 is formed by diffusion.
As shown in Figure (I), an oxide film 28 is formed again. In this way, the first. Since the second diffusion layers 24 and 25 are simultaneously formed by diffusion, it is possible to make the diffusion concentration, depth, etc. the same.
その後、第２図（Ｅ）に示されるようにフォトエツチン
グによって、第１．第２ＰＮ接合用拡散層２６．２７の
形成領域に対応する箇所に拡散窓を形成する。これらの
拡散窓からＰ型の第１．第２ＰＮ接合用拡散層２６．２
７を第２図（Ｆ）に示されるように第１．第２拡散層２
４．２５よりも浅くそれぞれ拡散形成する。この実施例
では、第１．第２ＰＮ接合用拡散層２６．２’７も同時
に拡散形成するので、拡散濃度、深さを同一にすること
が可能である。その後、必要に応じてパシベーション膜
を形成し、さらに、電極部分の窓開けを行ない、電極用
メタル２９．３０およびバンプ３１を形成して第２図（
Ｇ）に示されるように半導体ペレット２０が製造される
。Thereafter, as shown in FIG. 2(E), the first. A diffusion window is formed at a location corresponding to the formation region of the second PN junction diffusion layer 26,27. From these diffusion windows, a P-type first . Second PN junction diffusion layer 26.2
7 as shown in FIG. 2(F). Second diffusion layer 2
4.25, each is formed by diffusion. In this example, the first. Since the second PN junction diffusion layer 26.2'7 is also formed by diffusion at the same time, it is possible to make the diffusion concentration and depth the same. Thereafter, a passivation film is formed as necessary, and a window is opened in the electrode portion, and electrode metals 29 and 30 and bumps 31 are formed, as shown in FIG.
A semiconductor pellet 20 is manufactured as shown in G).
このような構成の半導体ペレッ）２０を通常の半導体ベ
レットと同様にデエメット線とともに、ガラス管内に封
入することにより双方向性ツェナーダイオーＹが得られ
る。A bidirectional Zener diode Y can be obtained by enclosing the semiconductor pellet (20) having such a structure in a glass tube together with a Demet wire in the same way as a normal semiconductor pellet.
このように本発明の双方向性ツェナーダイオ−ＩＦ １
士、坑３ＭでＭ示の番央例の上）１こ半道儂ペレット１
，１を２つ用いる必要がなく、さらに、第４図で図示の
従来れのように特別の製造工程や装置を要せず、通常の
半導体ペレットと同様な工程で製造でき、製造コストを
低減することが可能となる。また、第５図で図示の双方
向性ツェナーダイオードと異なり、ブレークダウンを生
じさせるためのＰＮ接合層は、拡散形成されているので
、比抵抗を低くすることができ、これによって低い耐圧
の双方向性ツェナーダ・ｊオードを得ることが可能とな
る。さらに、第６図で図示の双方向性ツェナーダイオー
ドと異なり、ブレークダウンは、エピタキシャル層２２
の内部で生じるので、サージに強い安定した双方向性ツ
ェナーダイオードを得ることが可能となる。In this way, the bidirectional Zener diode-IF 1 of the present invention
(above example) 1 kohan dome pellet 1
, 1 does not need to be used, and furthermore, unlike the conventional method shown in FIG. 4, there is no need for special manufacturing processes or equipment, and it can be manufactured in the same process as ordinary semiconductor pellets, reducing manufacturing costs. It becomes possible to do so. Furthermore, unlike the bidirectional Zener diode shown in FIG. It becomes possible to obtain a tropic Zenerda j-ode. Furthermore, unlike the bidirectional Zener diode illustrated in FIG.
Since this occurs internally, it is possible to obtain a stable bidirectional Zener diode that is resistant to surges.
〈発明の効果〉
以上のように本発明によれば、半導体基板上に、該半導
体基板と異なる導電型のエピタキシャル層が形成され、
該エピタキシャル層の周縁部に前記半導体基板と同導電
型の拡散層が、半導体基板に至る深さまで形成され、前
記エピタキシャル層には、半導体基板と異なる導電型の
第１拡散層が形成されるとともに、前記拡散層の近傍に
半導体基板と異なる導電型の第２拡散層が形成され、前
記第１拡散層に、半導体基板と同導電型の第１ＰＮ接合
用拡散層が、該第１拡散層よりも浅く形成され、前記第
２拡散層、エピタキシャル層および前記拡散層の３層に
またがって半導体基板と同導電型の第２ＰＮ接合用拡散
層が、該第２拡散層よりも浅く形成されたので、特殊な
製造装置および製造工程を要せず、低い耐圧で、しかも
、サージに強い安定した双方向性ツェナーダイオードを
得ることが可能となる。<Effects of the Invention> As described above, according to the present invention, an epitaxial layer of a conductivity type different from that of the semiconductor substrate is formed on the semiconductor substrate,
A diffusion layer of the same conductivity type as the semiconductor substrate is formed at a peripheral portion of the epitaxial layer to a depth reaching the semiconductor substrate, and a first diffusion layer of a conductivity type different from that of the semiconductor substrate is formed in the epitaxial layer. , a second diffusion layer of a conductivity type different from that of the semiconductor substrate is formed in the vicinity of the diffusion layer, and a first PN junction diffusion layer of the same conductivity type as the semiconductor substrate is formed in the first diffusion layer. A second PN junction diffusion layer of the same conductivity type as the semiconductor substrate is formed to be shallower than the second diffusion layer, spanning the three layers of the second diffusion layer, the epitaxial layer, and the diffusion layer. Therefore, it is possible to obtain a stable bidirectional Zener diode that has a low breakdown voltage and is resistant to surges without requiring any special manufacturing equipment or manufacturing process.
第１図は本発明の一実施例の構造断面図、第２図は第１
図の半導体ペレットの製造手順を説明するための断面図
、第３図は従来例の簡略化した断面図、第４図は他の従
来例の半導体ペレットの構造断面図、第５図は本件発明
者が先に提案した半導体ペレットの構造断面図、第６図
は本件発明者が先に提案した他の半導体ペレットの構造
断面図である。
２０・・・半導体ペレット、２１・・・半導体基板、２
２・・・エピタキシャル層、２３・・・拡散層、２４，
２５・・・第１．第２拡散層、２６．２７・・・第１．
第２ＰＮ接合用拡散層。FIG. 1 is a structural sectional view of one embodiment of the present invention, and FIG.
3 is a simplified sectional view of a conventional example, FIG. 4 is a structural sectional view of another conventional semiconductor pellet, and FIG. 5 is a sectional view of the present invention. FIG. 6 is a cross-sectional view of the structure of another semiconductor pellet previously proposed by the inventor of the present invention. 20... Semiconductor pellet, 21... Semiconductor substrate, 2
2... epitaxial layer, 23... diffusion layer, 24,
25... 1st. 2nd diffusion layer, 26.27... 1st.
Diffusion layer for second PN junction.
Claims (1)
エピタキシャル層が形成され、該エピタキシャル層の周
縁部に前記半導体基板と同導電型の拡散層が、半導体基
板に至る深さまで形成され、前記エピタキシャル層には
、半導体基板と異なる導電型の第１拡散層が形成される
とともに、前記拡散層の近傍に半導体基板と異なる導電
型の第２拡散層が形成され、前記第１拡散層に、半導体
基板と同導電型の第１ＰＮ接合用拡散層が、該第１拡散
層よりも浅く形成され、前記第２拡散層、エピタキシャ
ル層および前記拡散層の３層にまたがって半導体基板と
同導電型の第２ＰＮ接合用拡散層が、該第２拡散層より
も浅く形成されてなる双方向性ツェナーダイオード。(1) An epitaxial layer having a conductivity type different from that of the semiconductor substrate is formed on a semiconductor substrate, and a diffusion layer having the same conductivity type as the semiconductor substrate is formed at the peripheral edge of the epitaxial layer to a depth reaching the semiconductor substrate, A first diffusion layer having a conductivity type different from that of the semiconductor substrate is formed in the epitaxial layer, and a second diffusion layer having a conductivity type different from that of the semiconductor substrate is formed near the diffusion layer. , a first PN junction diffusion layer having the same conductivity type as the semiconductor substrate is formed shallower than the first diffusion layer, and extends over three layers, the second diffusion layer, the epitaxial layer, and the diffusion layer, and has the same conductivity type as the semiconductor substrate. A bidirectional Zener diode in which a second PN junction diffusion layer of the type is formed shallower than the second diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14823284A JPS6126267A (en) | 1984-07-16 | 1984-07-16 | Bidirectional zener diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14823284A JPS6126267A (en) | 1984-07-16 | 1984-07-16 | Bidirectional zener diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6126267A true JPS6126267A (en) | 1986-02-05 |
Family
ID=15448217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14823284A Pending JPS6126267A (en) | 1984-07-16 | 1984-07-16 | Bidirectional zener diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6126267A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457881A (en) * | 1987-05-23 | 1989-03-06 | Thomson Brandt Gmbh | Automatic switching circuit device for regulating speed of phase control circuit |
| US5880511A (en) * | 1995-06-30 | 1999-03-09 | Semtech Corporation | Low-voltage punch-through transient suppressor employing a dual-base structure |
| WO2006022287A1 (en) * | 2004-08-27 | 2006-03-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device for surge protection |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326684A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Two-way zener diode |
-
1984
- 1984-07-16 JP JP14823284A patent/JPS6126267A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326684A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Two-way zener diode |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457881A (en) * | 1987-05-23 | 1989-03-06 | Thomson Brandt Gmbh | Automatic switching circuit device for regulating speed of phase control circuit |
| US5880511A (en) * | 1995-06-30 | 1999-03-09 | Semtech Corporation | Low-voltage punch-through transient suppressor employing a dual-base structure |
| WO2006022287A1 (en) * | 2004-08-27 | 2006-03-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device for surge protection |
| KR100898655B1 (en) | 2004-08-27 | 2009-05-22 | 파나소닉 주식회사 | Semiconductor device for surge protection |
| US8004041B2 (en) | 2004-08-27 | 2011-08-23 | Panasonic Corporation | Semiconductor device for surge protection |
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