JPS61259357A - Common bus control system - Google Patents

Abstract

PURPOSE:To improve resistance to failure by following an output of a clock oscillation circuit in a module to fluctuation of a bus clock and making the frequency and phase coincident with each other thereby using decentralized supply of the bus clock. CONSTITUTION:The module 21 becomes a supply source of a bus clock signal 24 and modules 22, 23 other than the bus master input the input signal 24, the oscillation frequency of the clock oscillation circuit is followed to the signal 24 to make the frequency and phase coincident with each other. Thus, all modules apply bus operation tuned to the bus clock. When the module 21 loses the right of use of the bus and the module 22 becomes a new bus master, the module 21 stops the supply of the bus clock and the module 22 becomes the supply source of a new clock and the phase is made coincident just before the right of use takes over and the normal operation synchronously with the bus clock is continued.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a common bus control method for improving the fault tolerance of the common bus in a data processing system in which a plurality of modules are connected by a synchronous common bus. Regarding.

[Technical background of the invention and its problems]

A common bus between a plurality of modules constituting a data processing system can be broadly classified into two types: an asynchronous bus type and a synchronous bus type. In the asynchronous bus system, when communicating between two modules connected to a bus, one module sends a signal regardless of the operation timing of the other module. Therefore, in order for the receiving module to acquire the data on the bus, a synchronization process is required, which results in some time being lost. On the other hand, in the synchronous bus system, there is a common bus clock for all modules connected to the bus, and signals are sent to and received from the bus based on this bus clock.

Usually, the bar clock and the operating clock of each module are the same or have a certain relationship. According to such a synchronous bus system, all modules are synchronized with the bus clock, so that signals can be efficiently transmitted via the bus. Furthermore, the synchronous bus method has the advantage that the interface circuit between the module and the bus is simpler than the asynchronous bus method.

By the way, the conventional synchronous bus system requires a master module, which is a special module having a bus clock generation circuit, in addition to the normal module connected to the bus. This is a serious drawback from the point of view of fault tolerance. This is because in a fault-tolerant system, the normal operation of the system.

This is because it must not be stopped by a failure of a single component in the system. Figure 6 shows this situation. 12.13.1 in Figure 6
4 is a normal module in the system, 11 is a master module having a bus clock generation circuit, and 15 is a bus clock, which is output from the bus master 11 and input to all modules 12, 13, and 14 other than the bus master.

16 is a common bus. As can be seen from the figure, in the conventional synchronous bus system, if the bus master 11 fails, the supply of the bus clock signal is cut off, and all functions of the bus system stop.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a new synchronous bus system that enables efficient bus operation using a synchronous bus system and improves fault tolerance through distributed supply of bus clocks. The purpose is

[Summary of the invention]

The present invention provides a control method for the synchronizer common bus in a data processing system in which a plurality of modules are connected by a synchronized common bus, wherein at least a module that can become a bus master internally oscillates a clock whose frequency is variable within a certain range. The clock oscillation circuit in the Mogicor is a PLL (Phase) circuit that uses the bus clock on the synchronous bus as a reference signal.
The clock oscillation circuit in the module has a first function of making the output of the clock oscillation circuit follow the fluctuation of the bus clock to match the frequency and phase, and the clock oscillation circuit in the module is configured as a oscillates at a predetermined constant frequency that matches with sufficient accuracy and is located approximately in the center of the oscillation frequency variation range, and outputs it to the bus clock line on the common bus to supply a bus clock signal. The clock oscillation circuit in the module that has acquired the right to use the bus and has become the bus master operates according to the second function, and the clock oscillation circuit in the module that has lost the right to use the bus and other bus masters operates according to the second function. The clock oscillation circuit of the non-modular module operates according to the first function, and is realized by a synchronous bus system characterized by having the above functions.

〔Effect of the invention〕

According to the present invention, even though efficient bus operation is possible using the synchronous bus method, the fault tolerance of the bus system can be improved by distributing the bus clock. For example, according to the present invention, even if any module connected to a common bus is disconnected from the bus due to a failure or the like, the normal operation of the bus system will not be hindered. In contrast, in conventional synchronous bus systems, if the only master module in the system is disconnected from the bus, the bus stops functioning.

[Embodiments of the invention]

FIG. 1 is a diagram of a data processing system using the bus method of the present invention. In the figure, 21, 22, and 23 are modules constituting the data processing system, 24 is a bus clock signal line, and 25 is a common bus including data lines and other signal lines.

A module that wishes to start communication with other modules using the bus must acquire the right to use the bus and become the bus master. Although it is beyond the scope of the present invention how a single module acquires the right to use the bus when multiple modules compete, several distributed methods are known that are suitable for fault-tolerant bus systems. . (For example, IEEE P896 bus standard FutureBu+s
).

In FIG. 1, if the module 21 is currently the bus master, according to the present invention, the module 21 becomes the source of the bus clock 24, and the modules 22 and 23 other than the bus master input the bus clock signal 24, and each The oscillation frequency of the clock oscillation circuit is made to follow the bus clock signal 24 to match the frequency and phase. This allows all modules to perform bus operations synchronized with the bus clock. Next, it is assumed that the module 21 does not lose the right to use the bus and the module 22 becomes the new bus master. At this time, the module 21 stops supplying the bus clock, and the module 22 becomes the new bus clock supply source. The frequency of the bus clock output by the module 22 matches the frequency of the bus clock output by the previous bus master, the module 21, with sufficient accuracy, and the phase remains unchanged until just before the module 22 takes over the right to use the bus. Since they also matched,
Even when the module 22 becomes a new bus master and starts outputting the bus clock signal 24, there is no major change in the frequency and phase of the bus clock, so normal bus operation synchronized with the bus clock can be continued. Such a smooth handover of the output of the bus clock signal 24 accompanying the handover of the right to use the bus can be performed between arbitrary modules 21, 22, and 23 within the data processing system.

The present invention achieves distributed supply of bus clock signals through the operations described above, and realizes a fault-tolerant bus system.

An example of implementing a PLL clock generation circuit and its operation necessary to realize the present invention will be described below.

FIG. 2 shows the clock oscillation circuit existing in each module 21, 22, 23 and its surroundings.

In the figure, 31 tri, PLL (Phase Lo
The clock oscillation circuit 32 is configured as a cked Loop) circuit, and its output signal 5CLK is used as the operation timing of the logic circuit in the module. 33 is a bus clock signal BCLK, and the PLL oscillation circuit 31
It becomes a reference input. 34 is a lock state detection signal, PL
The output 32 of the L oscillation circuit is locked to the bus clock 33,
This is to notify that the phases match. When 1 is output from the lock signal 34, the operating timing of the module and the bus clock of the common bus are synchronized, so communication with other modules via the common bus becomes possible. 35 is a signal line MASTER which inputs 1 when this module is a bus master;
When you enter 0 in .

The oscillation circuit 31 operates as a PLL oscillation circuit using the bus clock signal 33 as a reference input, but this signal $35
When inputted, @loss circuit 31 oscillates at a predetermined constant frequency located approximately at the center of the frequency variable range, and outputs output signal 32 via gate 37 as bus clock 33 onto the common bus.

FIG. M3 shows details of the PLL oscillation circuit 31 in FIG. 2. The figure includes an oscillation circuit composed of a crystal or ceramic crystal resonator 41, a CMBS type inverter 42, and switches 43 and 44 that can be controlled at a logic level. Generally, a crystal or ceramic oscillation circuit is used as a highly accurate and highly stable reference clock waste generation circuit, but as shown in the figure, the switch 43.43
By controlling the capacitor and changing the oscillation frequency, the frequency change of 10-3 is, for example, 100 ns is 10
The change is only about 0.1 ns, and even if this is used as the operation timing of the logic circuit, it will not affect the operation. In the PLL oscillation circuit 31, the switch 43 is turned off,
Switch 44 to 0NICt, low frequency, switch 4
3 is turned on, the switch is turned off to achieve an intermediate frequency, and both switches 43 and 44 are turned off to realize a high frequency. As mentioned above, the intermediate frequencies must be matched with sufficient precision in the clock oscillation circuits in all modicolls. For the remainder of FIG. 4, the 45 day divider circuit, the 46
is the final output signal 5CLK of this PLL oscillation circuit, which is the output signal 32 and [dl-, and is used as the operation timing of the logic circuit in the module. 47 is a bus clock signal BCLK, which is the same as the signal line 33. , 48 are D-flip-flops, which function as a phase comparator between 5CLK 46 and BCLK 47. 49 corresponds to the signal line 35 in FIG. 3, and if this module is a bus master, 1. If it is not the bus master, enter 0. if,
When the bus master in this module is set, input 1 to the signal line 49, and as a result, the switch 43 is turned on, and the switch 4 is turned on.
4 is turned off and the oscillation circuit oscillates at an intermediate frequency,
5CLK46, and is finally output to the bus clock on the common bus, serving as the bus clock supply source.

Now assume that this module is not a bus master. At this time, input 0 to the signal line 49 and turn the switch 43 to CUFF.
and the phase comparator 48 is operated. In this case P
The operation of the LL oscillation circuit 31 will be explained as follows.

First, as a precondition, the intermediate oscillation frequencies of the clock oscillation circuits 31 in all modules must match with sufficient precision. Therefore, the frequency of the bus clock output by the current bus master is between the high oscillation frequency and the low oscillation frequency of the clock oscillation circuits of all modules that are not bus masters. Therefore, in this module which is not a bus master, as shown in the timing diagram of FIG.
Suppose that the start-up of 46 is slightly delayed. At this time, the D-flip-flop 48 is set to 0, the switch 44 is turned off, and therefore the crystal oscillation circuit oscillates at a high frequency, and the period of 5CLK 46 is BCLK 47.
The period is slightly shorter than that of As a result, the time difference between the two rises gradually decreases. Next, Figure 4(b)
As shown in the timing diagram, it is assumed that the rise of 5CLK46 is slightly ahead of the rise of BCLK47. At this time, 1)-7 lip-flop 48 is set to 1, thereby turning on switch 44, causing the crystal oscillation circuit to oscillate at a low frequency, and the period of 5CLK 46 being slightly longer than that of BCLK 47. As a result, the time difference between the two rises gradually decreases. By the above operation, the 5CfGC 46 follows the BCLK 47, and the phases of the two coincide. However, the phases do not match completely, and the maximum is 5 etup time + hold time of D-flip frog 48.
A jitter of about e occurs.

When using 74F74 for D-7 Lip 70 Tsug 48,
A typical value of the jitter is around 4 ns, which is sufficiently small.

In FIG. 4, 50 is a lock state detection circuit, and 51 is its output signal, which is the same as the signal line 34 in FIG. i3. The lock state can be detected by detecting that the rise of 5CLK is within a certain range with respect to the rise of BCTLK, that is, within the allowable range of the lock state, as shown in the wc5 diagram. The allowable width of this locked state must be larger than the magnitude of jitter caused by the D-flip-frog 48 described above.

According to the embodiment of the present invention described above, fault tolerance is improved by distributing the bus clock while retaining the advantages of the conventional synchronous buzz method such as a high-speed and simple interface circuit synchronized with the bus clock. A synchronous bus system can be realized. For example, according to this embodiment, the bus clock is supplied by the bus master at that time, so even if any module connected to the common bus is disconnected from the bus due to a failure or the like, the supply of the bus clock will not be interrupted. Bus operations can continue. Further, according to this embodiment, it is possible to know from the lock state detection signal that the clock oscillation circuit in the module has lost synchronization with the bus clock, which is useful for detecting a failure in the clock circuit. For example, if synchronization is not restored for a long time, it can be determined that the clock circuit has failed, and this module can be disconnected from the system. Furthermore, in this embodiment, each module has a clock generation circuit that utilizes minute changes in the oscillation frequency of the crystal oscillation circuit, so noise or the like may get on the bus clock line on the common bus and temporarily change the waveform of the bus clock signal. Even if there is a disturbance or a short-term interruption of the bus clock signal, the effect on the clock generation circuit between each module is small, and the synchronization between each module is almost never lost. In this sense as well, the bus system in this embodiment has fault tolerance. Furthermore, in this embodiment, if a major temporary failure occurs in the bus clock line for some reason and the clock generation circuits in each module become out of synchronization, the phase with the bus clock signal will gradually change due to a minute frequency change in the crystal oscillator circuit. Since synchronization must be performed, it may take a long time (about several milliseconds) to recover synchronization, but this is useful as a waiting time.

That is, in general, when a temporary failure occurs, the probability of success is higher if you try again after a while than if you try again immediately, but in this embodiment, by recovering synchronization using the lock state detection signal, , you can automatically get this waiting time.

Finally, although the embodiment shows a PLL oscillation circuit using a crystal oscillation circuit, it should be noted that the present invention is not limited to a specific PLL oscillation circuit system.

[Brief explanation of the drawing]

, FIG. 1 is a diagram showing a synchronous common bus system of the present invention,
FIG. 2 is a diagram showing an example of the clock generation circuit in the module, FIG. 3 is a diagram showing a detailed configuration example of the clock generation circuit, and FIG. 4 is the operation of the PLL clock generation circuit in the embodiment of the present invention. FIG. 5 is a timing diagram for explaining the operation of the lock state detection signal in the embodiment of the present invention, and FIG. 6 is a diagram showing a conventional synchronous bus system. 21.22, 23...Module constituting the data processing system, 15...Bus clock line, 16...Common bus, 40...Oscillation circuit. 2/, >223 Figure 1 χ Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] A control method for a synchronous common bus in a data processing system in which a plurality of modules are connected by a synchronous common bus, wherein at least a module that can become a bus master has a variable frequency within an internal range. The module has a clock oscillation circuit, and the clock oscillation circuit in the module is a PLL (phas) that uses a bus clock on a synchronous common bus as a reference signal.
a first function configured as a (Locked Loop) circuit and causing the output of the clock oscillation circuit to follow fluctuations in the bus clock to match the frequency and phase;
and the clock oscillation circuit in the module oscillates at a predetermined constant frequency that matches with sufficient accuracy in all modules and is located approximately in the center of the range of variation of the oscillation frequency, and It outputs to the clock line and outputs to the bus clock line to serve as a bus clock supply source. a clock oscillation circuit in the module that has acquired the right to use the bus and has become the bus master operates according to the second function;
A common bus control system characterized in that a module that has lost the right to use the bus and other modules that are not bus masters operate according to the first function.