JPS61248105A - Controlling device inside of apparatus - Google Patents

Abstract

PURPOSE:To reduce remarkably the burden of a CPU regarding a time for processing and capacity of a program by conforming an address of a controlled system an address of a memory that stores controlling data and an address that indicates attribute of data coming from outside to each other. CONSTITUTION:The controlling device inside of an apparatus consists of a CPU 4, a memory 5, circuits 1-3 to be controlled and external interfaces 7 (remote control decoder), 8 (external interface decoder) connected by buses inside of the apparatus, and a specific controlling address is given for each functional block of the circuit to be controlled. The CPU 4 performs the transmitting and receiving of controlling data with the circuits 1-3 to be controlled based on the controlling address. The corresponding address of the memory 5 that stores controlling data conforms with the controlling address, and at the same time, the external interfaces 7, 8 are provided with a decoder that gives address that conforms with the controlling address to controlling data coming from the outside and transfers to the CPU. Thus, it is not necessary for the CPU 4 to make changing of address when the transferring data, and the burden of transmitting and receiving data can be reduced remarkably.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention reads out control data one after another from a memory and
The present invention relates to an internal control device for a digital device that digitally controls a controlled circuit under the control of a PU.

[Summary of the invention]

In an internal control device in which a controlled circuit is controlled by a CPU using control data read from a memory, a control address assigned to each function of the controlled circuit is matched with a corresponding address in the memory. With,
The control data from the external interface is assigned an address that matches the above control address, thereby greatly reducing the burden on the CPU for data transfer.

[Conventional technology]

TV receiver using digital IC circuit, V
Video equipment and audio equipment such as TRs and tape recorders are becoming widespread, and many of these digital equipment employ inner bus systems. In an inner bus system, there is a CPU, an inner bus,
By providing a memory, etc., storing operating setting values for each circuit in the memory, and during normal operation, the CPU reads out the setting values and supplies the read data to a predetermined circuit through an inner bus. Each IC is made to perform a predetermined operation.

At the same time, each IC is controlled via the CPU and inner bus by external operations such as a keyboard or remote control.

Conventionally, two-wire type and three-wire type have been the main types of inner buses used in such inner bus systems. A two-wire bus consists of a data transmission path and a clock transmission path, and this method was developed in Japanese Patent Application Laid-open No. 5
The communication method disclosed in Publication No. 7-106262 is used. The three-wire bus consists of a data transmission path, a clock transmission path, and an identification signal transmission path for identifying data blocks.

In electronic devices equipped with the above-mentioned inner bus system, not only the internal wiring is significantly simplified, but also all adjustments during manufacturing and service are controlled by software, which allows for standardization, commonality, and simplification of adjustments. This makes it possible to expect overall cost reductions, including reductions in manufacturing costs. Furthermore, by adding an IC compatible with the inner bus, multi-functionality and high performance can be easily achieved.

[Problem that the invention seeks to solve]

TV receivers and VTs that use an inner bus as described above
In R, etc., when changing control data (picture level, volume, etc.) using a remote controller or external input, the CPU receives the control data through the external interface and inner bus, and then transfers it to nonvolatile memory and stores it. . The purpose of using non-volatile memory is to maintain settings such as picture and volume immediately before the device is powered off, and to refresh control data in response to device operations and adjustments.

When control data is transferred from the outside to the CPU, the address format and data format (
If the format (format) differs from the format used within the device, the CPU must perform conversion work to match these address formats and data formats with the format used within the device.

Also, when outputting data from the CPU to memory, if the address of the data itself and the address of the memory are different, the address must be converted before being output to the memory. Must be converted to the format used.

Therefore, the problem arises that the program capacity of the CPU becomes insufficient or that the processing time becomes long and the control speed decreases.

[Means for solving problems]

As shown in FIG. 1, the in-device control device of the present invention comprises a CPU 4, a memory 5, and a controlled circuit (1) connected by an in-device bus.
~3), external interfaces (7, 8), and a specific control address is assigned to each functional block of the controlled circuit. The CPU 4 sends and receives control data to and from the controlled circuits (1 to 3) based on the control address. The corresponding address of the memory 5 that stores the control data matches the control address, and the external interface (7, 8) attaches an address matching the control address to the external control data and transfers it to the CPU. It is equipped with a decoder to

[For production]

The CPU 4 does not need to perform address conversion work when transferring data, and the burden of data transmission and reception is greatly reduced.

〔Example〕

FIG. 1 is a block diagram of the main parts of a TV receiver showing an embodiment of the present invention. The receiver is provided with a channel selection circuit 1, a video processing circuit 2, an audio processing circuit 3, etc. as a signal processor whose processing functions are digitized, and these controlled circuits are composed of several ICs, and a CPU 4 and They are interconnected through a memory 5 and an inner bus 6. Furthermore, C
The PU 4 is a microcomputer consisting of an arithmetic unit, registers, ROM, and RAM, and the memory 5 is a writable and erasable nonvolatile ROM that stores control or adjustment data.

7 and 8 are decoders connected to the ends of the inner bus 6;
The decoder 7 converts input from the remote controller into control data. The decoder 8 is for an external interface for converting control information from an external device into control data.

The control data is, for example, frequency in the channel selection circuit 1, and pictures, colors, etc. in the video processing circuit 2.
These include hue, brightness, sharpness, etc., and in the audio processing circuit 3, volume, left/right balance, etc.

The CPU 4 periodically reads control data from the memory 5, transfers this data to the channel selection circuit 1, the video processing circuit 2, and the audio processing circuit 3, and refreshes the operating points of each circuit. This is a countermeasure when the control data of each circuit 1, 2, 3 is destroyed due to noise or the like.

Further, when control data is given from the remote controller to the remote control decoder 7, the CPU 4 reads the output of the decoder 7, updates the contents of the memory 5, and further
In step 3, control data is derived.

Similarly, when control data is applied to the decoder 8 from the outside, the CPU 4 reads the output of the decoder 8, updates the contents of the memory 5, and transmits the updated contents to the circuits 1 to 3. Also, if there is a request to know control data from outside, C.
PU 4 reads the contents of memory 5 and transfers it to decoder 8, and decoder 8 derives the received data to the outside.

FIG. 2 shows the format of transfer data sent and received by the CPU 4 through the inner bus 6, and after a specific start condition S, a slave address SLV is sent out to designate one of the controlled circuits. Next, the R/W bit instructs data transmission or reception (writing/continuation if memory 5 is selected as a slave), and further sends a subaddress SUB after the accrue pit A, and sends a subaddress SUB to the control target in the slave. Identify the function (item).

For example, regarding the video processing circuit 2, brightness adjustment, contrast adjustment, hue adjustment
-- Specify one of the subaddresses. Next, control data DATA is derived after the occupancy bit A, and necessary control and adjustment are performed using this data, and then bus occupation is ended with a stop condition P.

As described above, blocks for each function in the channel selection circuit 1, video processing circuit 2, and audio processing circuit 3, which are controlled circuits, are distinguished by subaddresses. An example is shown below (H is a hexadecimal number).

Tuning circuit 1 Sub address Function 01 HVCO 02HAPT 03 HRP AGC 04H Subcarrier trap 05 HIF AGC Video processing circuit 2 Sub address Function OAH Brightness adjustment 0B) 1 Color saturation adjustment OCH Contrast adjustment ODH Hue adjustment OEH Sharpness adjustment OFHR Color temperature 10HG Color intensity IHB Color temperature 12H Vertical linearity 13H Vertical correction 14H Shift 15H Horizontal frequency 16H Vertical frequency 17H Picture level Audio processing circuit 3 Sub address Function 21 L channel volume 122
R channel volume 123 L channel volume 224 R channel volume 225 Bass control 26 Treble control memory 5 stores lock control data for each of the above functions. In this embodiment, the address of the memory 5 is made to match the above sub-address. Therefore, data read from a predetermined address in the memory 5 to refresh the control data of the circuits 1 to 3 may be transferred from the CPU 4 to the circuits 1 to 3 together with the control data using the memory address as a subaddress. That is, the address conversion work in the CPU 4 is unnecessary.

Further, when the CPU 4 receives external control data from the decoder 7.8 and updates the contents of the memory 5, the decoder 7.8 attaches an address indicating the attribute of the control data to the data and transfers the data. In this case as well, the attribute address and the above-mentioned sub-address are matched. Therefore, the CPU 4 can update the contents of the memory 5 by simply transferring the data to the memory 5 by converting the attribute address (sub-address) of the data transferred from the decoder 7 or 8 into a memory address.

Furthermore, the decoder 7.8 converts the output data format into C when sending external data from the CPU 4 to the memory 5.
Data conversion is performed so as to match the data format transferred by the PU 4 to the circuits 1 to 3 (that is, the data format for internal processing).

For example, as shown in FIG. 3, suppose that a command is given from the outside to the decoder 7 or 8 to set the picture level to the minimum value. This picture level data is 8 bits with a minimum value of 255 and a maximum value of 0. The decoder 7 or 8 converts the data format of this data to match the format of processing data inside the device (minimum value 0, maximum value 255).

Therefore, the picture minimum data OOH is transferred from the decoder 7 or 8 to the CPU 4 with an address 17H attached thereto. The CPU 4 discriminates the address 17H, designates the slave address of the video processing circuit 2, adds the same sub-address 17H to the data 00H, and outputs it to the bus 6. The video processing circuit 2 receives this data and operates to set the picture minimum to the minimum value O.

At the same time, CPU 4 transfers address 17H and data 00H to memory 5 as is, and
Picture level control data in 7H is changed to OOH.

Therefore, since the data format in the memory 5 matches the format of the data that the CPU 4 outputs to the controlled circuit, at refresh time the CPU 4 directly outputs data to the controlled circuit without changing the format or address of the read data in the memory 5. (1 to 3).

〔Effect of the invention〕

In the present invention, the address of the object to be controlled in the device controlled by the CPU, the address of the memory that stores the control data, and the address that indicates the attribute of the external data are mutually defeated.
The CPU does not need to perform address change calculations when transferring data, and the processing time and program capacity are reduced by the CPU.
The burden on the PU is greatly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of a TV receiver to which the present invention is applied, FIG. 2 is a format diagram of data transferred through an inner bus, and FIG. 3 is a data flow diagram showing the operation of FIG. 1. In addition, in the symbols used in the drawings, 1-・----1--・-----1 station selection circuit 2
−・−−−−−−1−−−−・−−−−−Video processing circuit 3−・−−−−m−−−−・−−−−−−1 Audio processing circuit 4−−−− −−−−−−−−・−−−−−CP
U5----------------'Memory 6------------Inner bus 7.
・ ・ ----- ・ ・ ・ ・ ・ ・ ・ ・ ・ Remote control decoder 8 --------------------------------------------------------------------------------------

Claims (1)

[Claims] It consists of a CPU, memory, controlled circuit, and external interface connected by an internal bus, and a specific control address is assigned to each functional block of the controlled circuit, and the CPU controls the controlled circuit based on the control address. The internal control device is configured to transmit and receive control data to and from the circuit, and the corresponding address of the memory that stores the control data matches the control address, and the external interface transmits and receives control data to the external control data. An in-device control device comprising a decoder that attaches an address that matches a control address and transfers the data to a CPU.