JPS61239793A - Frame memory device - Google Patents

Abstract

PURPOSE:To drastically simplify the overall constitution of a color television set by constituting independently a frame memory for luminance signal and a frame memory for chrominance signal, and by providing a same operational clock to the both memories or ones related by 2<n>. CONSTITUTION:A luminance signal data and a chromatic signal data are stored respectively in the Y-frame memory for luminance signal 3 and the C1-frame memory for chrominance signal/C2-frame memory (hereinafter C1/C2-frame memory) 4. In case the Y and the C1/C2 are with the same operational clock, a same address is used. But if they are with ones in a clock-ratio, 2:1, the address in the Y-frame memory 3 is not used but one shifted by one bit is used as an address in the C1/C2-frame memory 4. Likewise, with clock frequencies related by 2<n>, the address bit correspondent to the value of 2<n> is used in order to commonly utilize the addresses in the Y and the C1/C2-memories.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frame memory device as an image memory for color televisions.

Conventional technology Conventional frame memories are equipped with processing circuits before and after the memory in order to efficiently record luminance signal data and chroma signal data in the memory in terms of utilization rate and effective utilization of the memory element. Ta.

FIG. 4 shows the configuration of a conventional frame memory.

The frame memory 32 is divided into a Y frame memory and a c,/c 2 frame memory depending on the address in the memory.The data converted by the M/D converter 3o is transferred to the latch 31 (first latch!).

The data is stored once in the first latch C++ and the first latch C2), and written to the frame memory 32 when the correct address is given based on the timing.

In reading, when Y data is read out according to the address, it is stored in the second latch Y of the latches 33, and O4
/C2 data is also read out in accordance with the timing of each address, and the second latch C1 and second latch C2 of the latch 33 are read out.
When Y-C4/C2 is complete, it is sent to the D/MU converter 34, and becomes the Y signal C1 signal + c2 signal.

Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, the memory transfer configuration is complicated, and the memory control also requires writing and writing.
Complicated timing such as reading and switching of addresses to memory were required.

In FIG. 3, there are data latches 31 and 33 before and after the frame memory 32, as well as an address switching section 36, and a complicated timing processing logic is also required for the address/memory controller 36.

Means for Solving the Problems The present invention provides a method of configuring the frame memory independently of the Y frame memory for luminance signals and the C1 and C2 frame memories for color signals, and making the operating clocks of the Y memory and C memory the same. , 2 to the nth power.

According to the present invention, the frame memory for luminance signals and the frame memory for chrominance signals are configured independently, and the operating clocks of each memory are made the same or have a relationship of 2 to the nth power, thereby improving overall performance. The configuration can be greatly simplified.

Embodiment FIG. 1 shows a block diagram of a frame memory device according to an embodiment of the present invention. Each input signal from terminals 1 & t1b and 1° is converted to a predetermined bit (in this embodiment, 8
The luminance signal data is transferred to the Y frame memory 3 for luminance signals, and the chroma signal data is transferred to the G frame memory/C2 frame memory (hereinafter referred to as CG/C 2 frame memory) for color signals. 4 respectively. At this time, the input signals are Y, C,...
If C2 is also input to input terminals 11L, 1b, and 10 at the same time, the synchronous clock/memory address controller /I/
Memory addresses 6 and 7 from 6 are supplied from a common address counter and can be moved simultaneously to select bits of address data depending on the clock ratio with Y (!: C, /C2. , /C2 are the same operating clock, use the same address as is, and Y
If c, /c2 have a clock ratio of 2=1, they can operate simultaneously by not using the LSB of the address of the Y frame memory 3 but using the one shifted by 1 bit as the address of the C1/C2 frame memory 4. Similarly, when the clock frequency has a relationship of 2 to the nth power, addresses of Y, c, /c can be used in common by using corresponding address bits. The same applies to reading.

Figure 2 shows a case where the clock ratio of the Y signal and the C, /C2 signal is 2:1, but for example, the clock ratio of the Y signal is 7.1.
When setting it to 6MH2, the clock of chroma signal 0,102 is 3
．． It becomes 58MHz. - If the number of dots in the scanning period is 612 in the Y signal (including the horizontal retrace period), then C1/C
The number of 2 signals is 256. In other words! The address for one scanning period of the signal specifies each dot using 9 bits, but the c + /c 2 signal only needs 8 bits. At this time, to specify Y and C4/C2 at the same position, use the upper 8 bits of the 9 bits of the address of the Y signal as the address of the C4/C2 signal.
2 can be made to correspond.

As described above, according to this embodiment, terminals 1 &, 1 b
.

Synchronous clock/memory address controller/L15 creates all memory control from Y signal input from 1G, supplies it to Y frame memory 3*O4/C2 frame memory 4, and outputs data as needed from the same address counter. By giving the address of the number of bits to the Y frame memory at address 6 and to the C〆C2 frame memory at address 7, it has a very simple configuration for both writing and reading, and the read data is transferred to the next D.
/m converter 10, 11.12, Y signal, C1 signal I
A C2 signal is obtained.

Effects of the Invention According to the present invention, control around the frame memory is simplified, and timing design, stability, etc. are greatly improved.

Furthermore, since addresses can be shared, various operations using memory, such as noise reduction and special effects, become easier.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a frame memory device according to an embodiment of the present invention, Fig. 2 is an explanatory diagram of its operation, Fig. 3 is a block diagram showing the configuration of the counter, and Fig. 4 is a block diagram showing a conventional example. It is. 3...Y frame memory, 4...C4
/C2 frame memory, 6... Synchronous clock
Memory address control. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Y3+ Y+z YJs Figure 3 Figure 4

Claims (3)

[Claims] (1) A frame memory device in which a luminance signal frame memory and a chrominance signal frame memory are configured independently, and the operating clocks of each frame memory are the same or have a relation of 2 to the nth power. (2) The frame memory device according to claim 1, wherein a common address counter is used, and necessary bits of the address counter are used for address data to each frame memory. (3) A frame memory device according to claim 1 or 2, wherein data simultaneity is maintained by common addressing of each frame memory, and memory input and output latches can be omitted.