JPS61239352A - Microcomputer unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The object of the invention is to provide a microcomputer element of improved characteristics, particularly suitable for real-time signal processing and the like. Another purpose is to provide high speed microcomputers with enhanced capabilities.

Summary of the Invention c/) According to one embodiment, the present invention features a single-chip microcomputer having separate on-chip program ROM and data RAM with separate address and data paths for program and data. Included in devices for real-time digital signal processing using devices. The external program address bus enables off-chip program fetches in the extended mode V, and opcodes are returned by the external data bus. The bus exchange module allows transfers between separate internal program and data buses under special circumstances. The internal bus is 16 bits, but
ALσ and the accumulator are 62 bits.

The multiplier circuit generates a single state 16x16 multiplier function separate from ALσ, and a 32-bit output is provided to ALσ.

One input to ALσ passes through a 0-15 bit shifter with sign extension.

In other embodiments, the processor chip is configured as described above, but in place of the on-chip program ROM, other on-chip RAM is included, and the processor chip is configured as described above.
RAM is used as a program or data memory. Therefore, all processors have off-chip program memory and large on-chip memory. - It can either work with one that has a data memory, or it can work with program execution from on-chip RAM (downloaded from off-chip program memory).

The features of novelty that are considered characteristic of the invention are set forth in the appended claims. however.

The invention itself, as well as other features and advantages, can best be understood by reference to the following detailed description in conjunction with the accompanying drawings.

Example Microprocessor Device Although the microcomputer device described herein is used primarily for signal processing, the concept can be used in various forms of processor confectionery, and the device can be used in many different devices. A microcomputer is used in the apparatus shown in general form in FIG. This equipment may be, for example, a voice communication device, a voice analysis device, a small ``burner'' or ``home'' computer, a single-board general-purpose microcomputer, a word processor, a computer computer with local processing capabilities having a display and a typewriter/keyboard. terminal, or one of a variety of different applications. This device is a single chip MO8/
It includes a central processing unit, ie, a microcomputer 10, as well as a program or data memory 11 and an input/output unit 12. Normally standard equipment work 10
Element 12 is an analog-to-digital and/or digital-to-analog converter, modem, keypad, CRT.
Includes display, disc/r-drive, etc. Engineering 101
2 often includes a connection to a general-purpose processor, ie, the microcomputer 10 is an additional processor of a larger device with an interface connected to the microcomputer 1012. The microcomputer 10, program or data memory 11, and processor 1012 have two multi-bit parallel address and data buses D and RA, and a control bus 1.
3 to communicate with each other.

Generally speaking, the device of Figure 1 functions as follows:
The microcomputer 10 internally or to the memory 11 by accessing the poy 14 (CI) ROM
The instruction word is fetched externally by sending an address on the address bus RA (and ROLK- on the control bus 13). When executed externally, instructions are received via data bus D from addressed locations in memory 11. Is the stiff instruction the next machine that is fetching the new instruction? (Kuru (20M) Iz clock or crystal
2 0 Onθ length determined by
5 or writing the result to data RAM 15, including arithmetic or logical operations on ALσ.

In the example described below, internally in the ROM 14 or R
The 12-bit instruction address applied externally directly to the AB bus is 2'', i.e. 4 words of ROM 14 and memory 1.
Addresses a program instruction or constant in 1. When reading from memory 11, a DKIJ- (data bus enable bar) command is issued on control bus 13. It is also possible to write to the memory 11, and for this purpose a WK- (write enable per) command is issued by the element 10 on one of the control bus lines 13, the memory 11 being part of the address space. or all read/write memory elements, so the WE-command enables the write function.

I10 element 12 is addressed as a board; this interface to external elements 12 is done using address and data buses RA and D and control bus 13; do not occupy. This is the conventional memory map 10
It is compared with

Data input/output via the main unit 10 or peripheral unit 12 is via bus RA.
Peripheral circuit 1 using the 3-bit field RAp from
208 g) Select one of the 16 pit boats PQ-P7. Since each port can be defined as either input or output by DEN- or WE-, there are actually 8
There are 16 16-pit boats with 8 inputs and 8 outputs. The 16-pit boats selected are RAp and DICN.
- or WH- and then read or write accessed via bus D. This operation uses one of the two instruction processors N or 00T, and uses vn on the control bus 13.
c becomes active for writing or 0ffT, and DEN- becomes active for reading or engineering N. ROM clock R (
! T,+ is active on control bus 13 every machine cycle except when either DFJJ- or WE- is active, i.e. memory 11 receives instruction words from off-chip every machine cycle. RO to enable access
The internal architecture of the microcomputer chip microcomputer 10 is
The detailed block diagram of FIG.

The device is a single chip semiconductor integrated circuit mounted in a standard 40-pin dual-in-line package or chip carrier. Sixteen bins or terminals of the package are required for the 16-bit data bus D, 12 are used for the address bus RA, and the remaining terminals are connected to the power supply Vdd.
ss, crystal x1. x2, used for control bus 13.

Adding to the program and data memory 14.15, the microcomputer 10 includes the central processing unit, or apσ, of the apparatus of FIG. 62-bit A, accumulator A (jo, AL
σ to another multiplier M, ALσ to CI) One input, thick S1 state or flag decode y 19D, receives the current instruction word and generates control bits for the CPU and data memory portions of element 10. Contains 1 from the instruction decoder.

A program counter PC that holds the instruction address for accessing the program memory 14ttRoM14 or sending it to the bus RA to the memory 11, a stack ST that stores the program memory address, and a stack ST that receives the current instruction word and sends it to the microprocessor. The program memory section is related to the instruction decoder which generates control bits. Instruction decoders 1 and 2 can be combined into one large control ROM, or decomposed into small PLA or random logic.

Data memory 15 includes two auxiliary address registers ARO and ARI for data memory 15, registers ARQ and ARI for use as data memory addresses.
Page register ARP to select between Rl, ? - relates to a data page buffer DP which holds specific bits of a data memory address.

The CPrJ has two internal buses, a 16-bit program
bus (P bus) and 16-bit data bus (D bus)
directed towards. Therefore, program access and data access can occur at the same time, and the ageless spaces are separate. Therefore, although this microcomputer is of Barbard architecture, the bus switching module BT,
M is, for example, AQC to glogram counter PCj (1
) It is possible to access only 0M14 for constants via eI-card or P bus, B bus, M, and D paths.

Single-processing microcomputers (1) The two main requirements are high speed and flexibility. Performance is gained by using separate theoretically on-chip program and data memories 14, 15, a large single accumulator Acc, and a parallel multiplier M.

Special purpose operations, data movements, are defined within the data memory 15, which further enhances performance in composite product operations. Flexibility is gained by defining an instruction set as described with reference to Table A, including memory expansion and single level interrupts.

This device consists of an on-chip program memory 14 of, for example, no more than 2 or 211 words, but this architecture allows the memory to be expanded to 4Kj or 212 words by adding an external program memory to memory 11. . In addition, another mode allows device 10 to be configured as a device emulation device.
In "device emulation" mode, the entire memory space is external and ROM 14 is not used.

Signal Processor with Dual RAM Referring to FIG. 6, another embodiment of the 7" processor of FIGS. 1 and 2 will be described below. The elements of FIG. Similar to step 10, U.S. Patent No. 4.4
It actually executes the instruction set in Table A of No. 91.910 (with exceptions described below), and also executes the important additional 7JO instructions. Is the processor in Figure 6 the same as before? - data bus D bus and program bus P, together with the bus, arithmetic/logic unit rILALσ, multiplier M, accumulator Acc, barrel shifter S with sign extension, program counter PC,
Stack BT.

Contains auxiliary registers ARQ and ARl, data RAM 15, separate program and ? -The Ta road is the so-called Nor-
It is provided as before in Bird Architecture.

However, unlike the embodiment of FIG. 2, the fifth processor does not have an on-chip ROM 14, but instead has a 20) RA that can be used for data or programs.
-M i 5 F? : Have it. Also, six additional auxiliary registers AR2, AR3, AR4 are available.

An important feature is that the two RAMs 15, 15P are dynamically reconfigurable using the configuration instructions described below, i.e. the memory U 15F can be used to store data just like RAM 15. It can be switched between use as memory or as program memory (such as ROM 14 in FIG. 2). Program, Counter P
The processor can operate without on-chip program memory by applying the output of C to external address bus RA and receiving addressed instructions from off-chip memory via external data bus DQ. Or MOV
RAM 15 from off-chip source using Fi instruction
RAM 15 is used as a program memory for loading blocks of instruction words into F and for high-speed execution of repetitive programs.
Use F. In one embodiment, RAM 15 has 288 words (16 bits per word). This is permanently mapped into data memory space, while RAM 15F is stored between data memory IJ 22 or memory locations under program control.
Contains 256 words that can be mapped into 0-gram memory space. Therefore, all 544 words of on-chip RAM 15, 15F can be used as data memory, and instructions can be supplied at full speed from off-chip elements (first diagram memory 11), or in other configurations, the 288 words can be used as data memory. Rp, M l 5 is used as data memory, 256 words of RAM 15
F is used as a program cache memory where instructions are downloaded from slow off-chip memory confectionery to on-chip RAM and executed at full speed. Several block transfer instructions have been added for efficient management of these memory spaces, and these instructions transfer instruction words, data, Alternatively, the information can be moved.

The dual RAM architecture also allows the execution of multiply-accumulate instructions in a single cycle (MAO instructions are discussed below), in which both the data bus D bus and the program bus P bus are used to transport operands to multiplier M. During this time, the MAO command is repeated. On-chip fRAM1 for delay operation
The data movement function ported to 5 is used in the Digital Filter Alprism. The "Multiply-Accumulate with Data Move" instruction MAOII provides all the functionality needed to port the taps of a transversal filter in a single machine cycle. Overflow, which often results from multiplication, can be solved by using a right shift on the 62-bit product of the ALσ output, or by using the ALσ output as in Figure @2.
This can be dealt with by using the saturation mode of the σ output.

The processor of FIG. 3 has six main memory address modes: direct, indirect, and immediate.

In direct mode, the address is defined in the instruction. In indirect mode, the address is generated by one of five 16-bit auxiliary registers ARQ-AR4. This auxiliary register file ARO-ARA is supported by a 16-bit auxiliary register arithmetic unit ARA;
is programmable to index addresses upward or downward simultaneously with data operations. The processor selects the auxiliary register ARO-A using the father arithmetic unit ARA.
It is programmable to branch upon comparison of RA contents. The processor has a series of immediate instructions where data is defined as constants in the program, often used in filter algorithms. During program execution at a rate of one word per machine cycle using table read instructions, a table of constants is stored in external program memory (first
A note is written in the memory 11) in the figure. Data is also data.
Moved from memory space to program memory space at the same speed. A repeat instruction RPT is provided to reduce code-to-accumulation ratio and branch overhead, and an RPTK n instruction allows the next instruction to be executed n+1 times. For example, a 50-tap traverse filter code requires two instructions, RP
It can be defined by TK 49 and MAOD.

The processor of FIG. 3 communicates with off-chip program, data, processing elements or other processors via a single external data bus D, address bus RA, and control bus 13. Wait states are stored in memory as required by the device.
External elements (first diagram memory 1) are inserted into the cycle.
1 or 1012) have different access times.

Hard processors have some additional facilities for supporting multiprocessing interfaces, in that part of the external data memory can be shared by several processors, i.e. This is the case when the processors are connected to a single device. A holding bin and three interrupt bins in control bus 13 provide host/slave device configuration and multitasking. Additionally, some of these processors are synchronized to each other at the clock level via synchronization bins.

Memory Map The memory map for the embodiment of FIGS. 1 and 2 is shown in FIG. 4a, and the memory map for the embodiment of FIG. 3 is shown in FIG. 4b. Since the second processor 10 has a 12-bit address bus RAQ, the program memory space is 4
There are 4096 words in total, and the ROM 14 is located in the second part of the space. Similarly, address area 4 of data memory can also contain 288 words of R.
AM 15 is located. The 10 address space is 8 words defined by the 6-bit address on the second design line RA. In a similar manner, the third diagram element stores the program memory, ?, as shown in Figure 4b. - data memory, I1
The six 0 ICs have separate address spaces, and these spaces are identified externally by the program strobe, data strobe, and process 10 strobe signals on the control bus 13. On-chip memory block is RAM
15 and RAM 15 F, the total contains 544 words. 7''' Program/Data RAM 7'' C1 (
256 words Vtt? - Located on page 4.5 of the data memory map when configured as JRAM and on pages 510 and 511 when configured as program RAM. The block containing RAM 15 (always data RAM) is in the top 62 words of page 6°7 and page 0σ].

The rest of the data/memo IJ/map is the memory/memory/map.
Note that it consists of registers and reserved areas.

Reserved areas are not used for storage and their contents are undefined when read.

RAM 15 using configuration 0NFD, 0NFF instructions
Configure P to be either data or program memory. Use the BLKP instruction (move a block from program memory to data memory) to download program information to RAM 15F when configured as data RAM and move the block as 0NFF (7 degrees program memory). (configuration) command and convert it to program RAM. 0NFD or C! Note that the first instruction fetch after the NFP instruction is taken from the previous memory configuration. Also, reset is RAM 15P data RA
Note also that it is configured as M.

The processor in FIG.
It has six registers that are mapped into memory space. These are DRR, DXE, TIM, and PRD.

These registers are named IMR and GREG. The DRR register is a 16-bit serial boat data transmission register. The TIM register is a 16-bit timer register and the PRD is a 16-bit period register used for timing functions. Interrupt mask register MRkl
Turn off the 6-bit interrupt mask. The GREG location is an 8-bit global memory allocated register. These registers are accessed like other data memory locations, except that block moves using BLKD are not available for these memory locations.

Processor has configurable on-chip RAM 15P
Provides instructions for effective use of data and program block movement and data movement functions. The BLKD command moves Zorotsuku within the data memo + J 27 and returns BLK.
The P instruction moves blocks from program memory space to data memory space. These instructions perform block movements from on- or off-chip memory.

The data movement command DMOV is suitable for porting algorithms that use so-called two-delay operations, such as synthetic products and digital filters in which data passes through a time window. Data movement instructions are continuous across on-chip data memory block boundaries, but off-chip
It cannot be used when data memory 1d is referenced. When ported to on-chip RAM 15 or 15F, the %DMOV functionality is equivalent to that of the device of FIG. D
MOV is an on-chip RAM U) that copies words from the currently addressed data memory location to the next high location.
It is possible to operate on data at an addressed location in the same cycle (for example, by ALσ). Operations in the auxiliary arithmetic unit σ are also performed in the same cycle using indirect addressing mode. MAOD (sum of products with data movement)
and IJTD (0-do-T register, sum of previous products, ?-ta move) instructions can also use data movement functions.

Program Counter and Stack The processor of FIG. 3 includes a 16-bit program counter pc and a four position hardware stack for storing the contents of the PC. The program counter PC (via the P bus) addresses internal and external program memory during instruction fetches.
Rules for calls, returns, and transferring data between programs and data memory space BLKP/BI, KD
(f program/block move from data memory to data memory), TBLR/TBI, W (table read/
Used for special purpose commands such as write. The program counter PC is a program counter where instructions are fetched from program memory and placed into the instruction register.
Addressing program memory on-chip or off-chip via address bus Pbus.

xfits:cz- Once loaded, the program counter PC is ready to begin the next instruction fetch cycle. PC has on-chip RAM 15 When P is configured as program memory, on-chip RAM
15 P, or a 16-bit address
Off-chip program memory is addressed via bus RA and external data bus D.

The program counter also uses a data desk.
The data memory is also addressed during BLKD instructions that move from one side of memory to the other. Accumulator Aaa
U) The content is "Calculation type Go" using B engineering M as before.
Program counter P to port the To J instruction
CVcc+- is read.

PotXPa+1 or a branch address (instruction like branch, call or interrupt) is loaded and a new fetch
Start the cycle. If a branch is taken and it is a conditional branch, pc is again incremented beyond the location of the branch address.
That is, P'O+2.

The processor also executes the next single instruction c/) N+1 times, where NG is the repetition counter RPT of the 8-bit counter.
It has a repeat command function that allows for When using this repeat function,
The instruction is executed and RPTO is decremented until RPTO becomes zero. This feature is NORM (normalization of accumulator contents), MACD (product sum with data movement), 5UB
Useful for many instructions such as O (conditional subtraction).

The stack 8T is accessible through the use of the PσBH and POP instructions; when the contents of PC are pushed onto the stack, the previous contents of each level are pushed down and the fourth position of the stack is lost.

Therefore, if more than four consecutive hits occur before a pop, data is lost. The opposite occurs with pop operations. Bof after 6 consecutive repetitions is a! Resulting in a value of 4 stack levels.

All four levels of the stack now contain the same value.

Two separate instructions PSHD and POPD k@RAM
15 to CI) Stack S of different data/memory values
Bush to T or pop a value from the stack to data memory. These instructions allow software to construct a stack in data memory RAM 15 for nesting of subroutines/interrupts of four or more levels.

The interface to local memory is an external 16-bit parallel data bus D, a 16-bit program address bus,
It is composed of bus FA, six bins PS, DB, S, and various other device control signals in the control bus 13 for memory space selection. The R/W signal controls the direction of transfer, and 5TRB provides a timing signal to control transfer. Use of the READY signal allows a wait state to be generated for slower off-chip memory communication. CPU The CPU has a 16-bit scaling shifter, a 5162-bit arithmetic logic fc[1l (AL path, 32 pits) Accumulator ACIC% enriches another shifter available at the output of both the accumulator and the multiplier.

The following steps occur when implementing a standard ALσ instruction. (
1) Data is fetched from RAM 15 on data path D path, (2) Data passes through scaling shifter S and ALσ where arithmetic is performed, (31 result is moved to accumulator Ace. One input of is always transferred to the accumulator Acc, and the other input is sent from the product register P of the multiplier M or from the scaling shifter S loaded from the data memory via the D bus.

The scaling shifter S has a 16-bit input connected to the data bus D bus and a 62-bit output connected to ALσ, and inputs ? as programmed into certain bits of the instruction. - Generate a left shift of 0 to 15 bits in the evening.

Is the output L8B zero? R'I'S, the MSB is filled with zeros or sign extended depending on the state programmed into the state register STQ (sign extension mode bit) SXM.

The 32-bit wide arithmetic logic 111tALσ and accumulator AOC execute a wide range of arithmetic and logic instructions, most in a single clock cycle. Overflow saturation mode is programmed through the SOVM and ROVM (Set or Reset Overflow Mode) instructions. When the accumulator is in overflow saturation mode and an overflow occurs, the accumulator Acc
is loaded with maximum pressure or a negative number depending on the direction of overflow. ALσrC manually inputted data is scaled by a scaling shifter S.

The processor executes a branch instruction according to the state of the ALU.
Ru. The BAOO (branch to address in accumulator) instruction provides the ability to branch to an address pointed to by the accumulator. The BIT and BITT (test the bits pointed to by the T register) instructions test data memory,
For example, it is possible to test the % constant bits of a word in RAM 15.

Zorocessor supports floating point arithmetic for applications that require large dynamic ranges. The normal ratio (NORM) instruction is used to normalize the fixed-point number that enriches the accumulator by performing a left shift. LACT (T
The register-directed load accumulator with shift instruction denormalizes a floating point number by arithmetic left-shifting the mantissa through an input scaling shifter. In this case, the shift count is the value of the exponent indicated by the lower four bits of the T register. ADDT
and SσBT (addition or subtraction from accumulator with shift in T register direction) instructions are also provided to enable other arithmetic operations. Floating point numbers with a 16-bit mantissa and a 4-bit exponent can be processed in this way.

32-bit accumulator Acc has two 16-bit segments for storage in data memory, AOOH
ACOL (accumulator high) and ACOL (accumulator low). Another thick on the output of the accumulator gives a 0.1 or 4 im shift to the left. This shift is performed while the data is transferred to the data bus D bus for storage, and the contents of accumulator Acc remain unchanged. When ACOH data is left shifted, LSB t!
forwarded from ACOL, MSB is lost. ha6L
When is shifted left, the LSB is zero-padded and the MSB is lost.

Accumulator Acc also provides an in-place 1-bit shift left or right (B
FXr or SFR command). SXM I? A shift or SFR (shift accumulator right) instruction affects the υ definition. When SXM = 1, SFR retains the sign of the accumulator data and performs an arithmetic right shift.

When 8XM = 00, SFR performs a logic shift and %L
BB is shifted out and a zero is shifted into the MSB. The 8FL (shift accumulator left) instruction is unaffected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in zero. RPT or RPTC for multiple shift counts! is used with these instructions.

2 ct) Complement 16x 16-bit nodeware multiplier M is capable of computing 32-bit products in a single machine cycle. Two registers are associated with the multiplier, ′″f′
A 16-bit temporary register TR holds one operand for the multiplier, and a 62-bit product register P holds the output resulting from the multiplication operation. Typically the LT (load T register) instruction loads T and provides one operand (from the data bus), and the MPY (multiply) instruction provides the second operand (also from the data bus).

In this case, a product is obtained every two cycles (one cycle is load T, one cycle is multiplication).

The two multiply-accumulate instructions (MAO and MAOD) fully utilize the bandwidth of multiplier M, allowing both operands to be processed simultaneously. As for MAC and MAOD,
2 via program and data buses P-bus and D-bus.
One operand is transferred to multiplier M every cycle. It performs a single cycle multiply-accumulate when used with RPT and RPTK instructions.

The t9Q,l (square/add) and SQ,R8 (square/subtract) instructions pass the same value to both inputs of the multiplier when squaring the data memory.

After multiplication of the two by 16-bit 2c/) complements, the 32-bit product is loaded into the 32-bit product register P.

The product may be transferred directly to the ALU or optionally shifted before being transferred to the ALU-manpower. The PM field specifies this shift mode P, with 00 for no shift, 01 for a 1-bit left shift, and 10 for a 4-bit left shift. Left shift, 117c et al. 6
This is a right shift of bits. Left shifts dictated by h values are useful in implementing fractional operations. right shift PM
Using values allows performing the C/) multiply-accumulate 127 times (or more) without accumulator overflow.

The lower 4 bits of the T register are also LAOT/ADDT/B.
A variable shift via a scaling shifter S is defined for UBT (accumulator row with shift 1/7111 addition/subtraction of T register indication). These instructions are useful for floating point operations when a number needs to be denormalized, ie, a floating point to fixed point conversion is required. The bit test instruction (TT,l) allows the testing of a single bit of a word in data memory based on the value contained in the lower four bits of the T register.

The CPU has two status registers STQ and STi containing various statuses and modes. The SST and 5sr1 instructions store the status register in data memory.

The LET and LST1 instructions load the status register from data memory. In this way, the current state of the element is saved on interrupts and calls. See below for information regarding the state register organization and the function of the state bits.

WIt-Control and Interface Device Control operations are provided on the processor chip by on-chip timers, repetition counters, external and internal interrupts, and external reset signals.

The memory map 16-bit timer used for external control operations is a down counter that is continuously clocked by an internal clock. This clock is 0LKOσT
It is obtained by dividing one frequency ft4. Reset sets the timer to its maximum value (FFFF), but
Period registers 'PF and '0 are not compared. After the reset is released, the timer begins to decrease. Following this, the timer or period register PRD is reloaded by instructions under program control.

A timer interrupt TINT is generated each time the timer decrements to zero. Within the same cycle that the timer reaches zero, the timer is loaded with the value contained in the period register PRD, thus causing an interrupt)'! 4 X (PRD)OLKO+77
One cycle σ is programmed to occur at regular intervals. This feature is useful for synchronously sampling or writing to peripherals. The timer register T and period register PRD are accessed at any time by a command. A period register value of zero is not allowed.

The repeat function allows a single instruction ff to be executed up to 256 times. The repetition counter RPTO is configured to store data memory values (via RPT instructions) or immediate values (R
PTK instruction) is loaded. The value of this Q operand is one less than the number of times the error instruction is executed. Repetition functions are sum of products, block movement, work 10 transfer, table resistance collection/
It can be used with commands like Sogo. These instructions, which are normally multi-cycle, are pipelined using the repeat function and become essentially single-cycle instructions. For example, a table read command normally requires six cycles, but when repeating, the table position can be read every cycle due to overlap.

The processor chip has three maskable interrupts available for external devices to interrupt the processor.
Has an engineering NTO. Internal interrupts are serial ports (R type NT and X type NT), tie-f (TINT), 7
7 Generated by the TRAP instruction.

Interrupts are prioritized such that reset has the highest priority and serial boat transfer interrupts have the lowest priority. Since all interrupt locations in the memory map are on two-word boundaries, branch instructions can also be accommodated at these locations if necessary. The control circuit captures multi-cycle instructions from interrupts; if an interrupt occurs in the middle of a multi-cycle instruction, the interrupt is not processed until the instruction is completed. This mechanism is applied to both repeat commands and commands V which are multi-cycled due to the READY signal.

Control bus upstream R8 signal may be used to asynchronously l/l.
You can force the counter pc to zero. For device operation on power-up, the Reset (Re) signal must be held open for at least five clock cycles to ensure device reset. Processor execution begins at location 0 in Figure 4b, which typically contains a branch instruction that directs program execution to the device initialization routine.

The data, program, and process 10 address spaces of FIG. 4b provide an interface to the memory and process 10. The local memory interface includes a 16-bit parallel data bus D, a 16-bit address bus RA,
Data, program and engineering 10 space selection (DA, P
It consists of S, engineering S) signals, and other c/) device control signals. The R/W signal controls the transfer direction, and 5TRB provides a timing signal to control the transfer.

The engineering 10 design can be easily compared by treating the engineering 10 like a memory. The processor elements are similar to memory memory elements, but are mapped into the processor address space using select signals and using the processor's external address and data buses. A 10-element memory interface with varying speeds is implemented at the READY line. When dealing with a slow element, the processor waits until the other element completes its function and signals the processor via the RKA, DY lines. The processor chip then continues executing O. The serial port communicates with serial elements such as codecs, serial A/D converters, and other serial devices with minimal external hardware. Serial ports are also used for intercommunication between processors in multiprocessing applications.

The serial port has the following two memory registers: a data transmitting register DIR and a data receiving register DRRQ. These registers are memory mapped, so they can be accessed like any other data memory location. Both the DRR and DIR registers have shift registers associated with each that define the bits to be received or transmitted (starting from CMSB). External clock 0LKX is applied to DXR, mode bit TX
M determines whether the framing pulse is generated on-chip or comes from off-chip. DRR is serial boat clock C! Provided with TXR and FSR pulses.

Serial ports operate in either byte mode or 16-bit word mode.

The flexibility of this architecture allows the processor chip to function as a stand-alone processor, multiple processors with parallel elements, and slave/host processors with a total memory space.
' - processors, allowing configurations to meet a wide range of device requirements, including devices that are peripheral processors interfaced via processor-controlled signals to other devices. Various multiprocessing configurations are described below.

For multiprocessing applications, processor chips can
It has the ability to allocate memory space and communicate with this space via BR (bus request) and READY control signals. Global memory is data memory that is shared by one or more processors. Global data memory accesses must be arbitrated. 8-bit memory matsubuto
Memory allocation register GR'EG designates a portion of the data memory space as global external memory. register GRK
The contents of G determine the dimensions between the global memo IJ Zp. If the current instruction addresses an operand in this space, a bus request BR is issued to request control of the bus. The length of the memory cycle is controlled by the READY line.

The processor uses the HOLD and HOLDA signals to
Supports DMA (Direct Memory Access) to FBf program/data memory. By driving HOLD low and tristating the processor's address, data, and control lines, other processors have full control of the external memory.

Interrupts The processor of FIG. 3 has seven priority vector ratio interrupts (listed in order of priority from highest to lowest), reset, user interrupt +0. Middle school 1. +2. It has an internal timer interrupt, serial boat reception interrupt, and serial boat transmission interrupt. All interrupts except reset are maskable.

Reset is used at any time to put the chip in a known state.ciJ
Function 71 is a non-maskable external interrupt, and reset is typically applied after startup when the machine is in a random state. A reset operation, when activated by applying a low level to the RA (reset) input bin of control bus 13, asynchronously terminates the current instruction and resets the program counter PCff.
Force it to zero. 7'-gram memory location 0 contains a program CI) normally containing a branch instruction to direct execution to the device initialization routine. Reset compares various registers and status bits to their initial values.

Upon receiving the R8 signal, the following occurs: a logic O is loaded into the ONF bit of the status register STi and all R
AM is used as data memory, program counter P○ is set to 0, address bus island is driven to 0 with R3 being low, and data bus D is tri-stated by the 10 buffer. and R8 is low state snack memory and engineering/○ space control signal (Pa, DB
, Engineering S jR/W, 8TRB.

BR) are not output by setting them high, and all interrupts are disabled by setting the NTM bit high (R8 is non-maskable).
(Note that all PRs are reset to 0), status bits are reset to 0, and RPTO is cleared.
The X-bin is tristated to terminate transmit and receive operations on the serial board, the TXM bit is reset low to release the R8X pin as an input, and the timer register T is set to FFFF to allow R8 to output. The period register is unaffected, the AOK signal is generated, and the serial port format bit II'0 is reset to logic zero, similar to a maskable interrupt.

When the R8 signal goes high, the external program memory location [! Execution begins at 110. R when in standby mode
Note that if an 8 is rolled, a normal reset operation occurs internally, but all buses and control lines remain tristated. After releasing HOLD and R8, execution begins at position 110.

The vector locations and priorities of all internal and external interrupts are shown below. As shown in this table, reset has the highest priority and serial boat transmit interrupt has the lowest priority. Although the TRAP instruction used for software interrupts is not given priority, it is included here because it has its own vector location. Since each interrupt address is two words apart, branch instructions can be accommodated in intermediate unnumbered locations.

Interrupt Memory name Location Priority Function R8Q 1 (highest) External reset signal NT
O22 External user interrupt 0 work NT1 4 3 External user interrupt 1 work NT2 6 4 External need interrupt 2T work NT245 Internal timer interrupt R work NT26<5 Serial boat reception interrupt XI
NT 28 7 (minimum) Serial port transmission interrupt TRAP 30 N/A TRA
When a P-instruction address interrupt occurs, it is stored in the 6-bit interrupt flag xpxyx. This register contains external user interrupts (2-0) and internal interrupts (2-0).
.

Set by X-engine NT and T-engine NT. Each interrupt is stored until it is acknowledged, interrupt acknowledgment 1 on control bus 13.
It is cleared by the 0 signal or the R8 signal. It is not stored in the RB double signal engineer FH. No commands are given to read or write to the FR.

The processor has a memory map interrupt mask register MR which masks external and internal interrupts. Only <SI, SB of the 16-bit space is used in the engineering MR. “1” from bit position 5 to 0 of engineering MH is engineering NTM =
If it is 0, the corresponding interrupt is enabled. The engineering MR can be accessed from the D bus for both read and write operations, but cannot be read using BLKD. R8 was not told about TMRIc,
Therefore, one plate has no effect on resetting.

Interrupt mode sphere TM which is bit 9 of status register STQ
enables or disables all maskable interrupts. Engineering NT
M's rOJ masks all non-adjacent interrupts and activates ``
1” disables these interrupts.

NTM is set to rIJ by the interrupt confirmation signal ACjK, DNT command, or reset. This bit is reset to "0" by the E-IT instruction.

The NTM does not actually change the MR or the interrupt flag register PR.

The control circuit protects multi-cycle instructions, ie, if an interrupt occurs during a multi-cycle instruction, the interrupt will not be processed until the instruction completes. The control circuit is also RPT or t
-j, disables processing of interrupts when the instruction is being repeated by the RPTK instruction. Repetition counter R
The interrupt is stored in the FH until PTO is reduced to 0, and the interrupt is processed at the next interrupt. Even if an interrupt is retracted while processing an RPT or RPTK instruction, the interrupt will be latched by the FH and will remain pending until RPTO is reduced to zero. Interrupts cannot be processed between E/NT and the next instruction in the program sequence.

For example, if an interrupt occurs during execution of an E/NT instruction,
This device also completes the next instruction with HTE before processing any pending interrupts. This means that the RET command is
RI! before processing the next interrupt.
Ensure that iT is viable. The state of the machine at the time of receiving an interrupt is saved and restored. State registers The processor has two state registers 8TQ and 8T1 containing the states of various states and modes. Note that in the processor block diagram of FIG. 3, the DP, ARP, and ARB registers are shown as separate registers. These registers are referred to as status registers because they do not have separate instructions to store in RAM. The ability to store state registers in data memory and load them from data memory allows machine state to be saved and restored for interrupts and subroutines.

All status bits are LST, LSTl, SST
, can read and write using the 5ST1 command (LS
Except for NTM, which cannot be loaded via the T command]
. However, some other instructions or functions overshadow these bits as instructed in the table! #do.

Context switching Context switching is generally required when processing a context switching subroutine call or interrupt. In the processor context switch of FIG. 3, several mechanisms are used to save the current state of the processor. For example, the program counter PC is automatically stored on the hardware stack ST. If there is important information in other registers, such as status or auxiliary registers, these must be serviced by software instructions. Auxiliary register A
The stack in data memory 15 identified by RQ-AR4 is useful for storing machine state during interrupt processing. The selected AR acts as a stack pointer. Machine registers are saved in RAM 15K and restored in the same order, i.e. the registers saved are AOOHjACOL, ARQ to AR3, P
R, STO, ST1, TR, and a 4-level hardware stack +9T.

Memory Management @41) The structure of the memory map shown in the figure is programmable and can be changed for each task of the processor. Instructions are provided for moving blocks of external data memory or program memory to data memory, configuring blocks of on-chip data RAM as program memory, and defining portions of external data memory as gamut. bl. Examples of memory movement, organization, and handling are briefly described below. The processor addresses two areas of memory directly to the 64, so blocks of data or programs are stored off-chip in slower memory and executed quickly. loaded on-chip. The BLKD and BLKP instructions facilitate processor TMS 32020 upstream memory-to-memory block movement. The BI, KD instructions move blocks in data memory, usually preceded by an RPTK instruction containing a number such as 255 to move 256 words.

The capability of on-chip RAM and extensive external memory allows down-reading of data or program memory to the chip 10. Also, RAM 15? - RAM is dynamically configurable for both data and program memory since data is saved when redefining the on-chip RJLM. Figure 4b shows the unit 7'R when changing the configuration.
The 0ONFD and 0ONFP instructions, which illustrate AM changes, in particular, change the effective address of RAM 15F and change its address and data bus. On-chip memory is reset, again t'! It is composed of ONF'D and 0NFF instructions. RAM 15p is configured as data memory by performing an 0NFD or reset, and an 0NFF instruction configures this block as program memory. For example, the zologram code is B
is loaded into RAM 15 I' using LKD, then the ONFF instruction is executed to reconfigure it, and then RAM
15 The code is executed from F.

0NFP or (1! The first instruction fetch after an NFD instruction is learned from the previous memory configuration, i.e. RAM 15P at position 1165280 after another external memory fetch.
(1) If execution starts from the first word, the 0NFF instruction must be placed in external program memory location 65.278. If the instruction placed in e1 location 65.279 is a two-word instruction, then the A second word is fetched from the first location. Alternatively, the user can execute from external program memory 12 if all of the on-chip RAM is used as data memory. RAM 15 is for data/
Always mapped into memory space. For almost all commands? - Assuming that the data is in internal RAM, the execution time of a program in on-chip RAM is the same as a program in external memory operating without wait states. The exceptions to this are the N and OUT instructions. When executed from on-chip RAM, these instructions execute in one cycle.

Global memory is memory that is shared by more than one processor, so access to it must be arbitrated. When using global memory.

The processor's address space is divided into local and global parts. The local portion is used by the processor to perform its individual functions, and the global portion is used to communicate with other processors. memory map, register GRE
G is provided in the processor, which allows a portion of the data memory to be designated as global external memory. GRKG, which is memory massaged at data memory address location 5, is an 8-bit register connected to the LSB 8 bits of the internal D bus. The contents of GREG determine the dimensions between the global notes IJ and ZJ. The legal values of GREG and the corresponding global memory spaces are shown below.

If an instruction azores data in global memory, a BR bus request signal BR on control bus 13 is issued requesting use of global memory. Before performing memory access,
The control circuit checks to see if RIICADY is asserted. If RFaDY is issued, a global memory access is performed.

If the bus arbitration logic continues to issue IADY after completing a global memory access cycle, the processor
global memory every machine cycle until Y is removed.
Perform access.

Timer Operations Processors use on-chip timers and their associated interrupts to perform various functions at regular time intervals. By loading the period register PRD with a value from 1 to 65.535 (FFFF), the timer interrupt T can be generated every 4 to 262.144 cycles. Two memory mapped registers are used to operate the timer. Timer register at data memory location 2
holds the current count of the timer. 4th 0L each
For every cycle of KOσT, T and M are decreased by 1.

The data memory (n rlt 3 cv period register holds the starting count of the timer. When T_M decreases to 0, a timer interrupt T_NT occurs. In the same cycle, the contents of the PRD register are In this way, TINT &'!0LKOσ
Generated every 4X(PRD) cycles of T1. The timer and period registers can be read or written in any cycle via the D bus. The count can be monitored by reading the T and M registers. A new counter period can be written to the period counter without causing the current timer count to become out of order. The timer begins a new period after the current count completes. If a new period is loaded into both the PRD and T-M registers, the timer will begin subtracting the new period without generating an interrupt. Therefore,
The programmer has complete control of the current and next period of the timer. The T/M register is set to the maximum warpage value (F
FFF ) and begins subtracting only after R8 is pulled.

The period register is not set on reset. If the timer is not used, TINT should be masked. PRD is then available as a general purpose data memory location. When using TINT, the PRD and T-M register should be programmed before the TINT mask is removed.

When programming high computational tasks where single instruction loop time is an issue, it is often necessary to repeat the same operation many times. Processors have a high degree of parallelism, so many of the instructions perform complete operations (like the MACD instruction). In these cases, a repeat instruction is provided that allows execution of the next single instruction -N+1 times. N is defined by an 8-bit repetition counter PRTo, which is connected to RPT via the D bus.
Or loaded by RPTK instruction. When the following instructions are executed, the RPT (3 registers are decremented until they reach zero. If the repeat function is used, the repeated instruction is 1
Q) is fetched. As a result of this, many multi-cycle instructions will take one or two cycles when repeating. This is a process 1 like TBLR, TBLW, process N, OσT.
Particularly useful for 0 instructions. Programs such as filter implementations require controllable loops in as little time as possible.

External branch control processors have externally controlled branch instructions that give system designers an alternative to interrupts for monitoring external conditions. The external gin named B 0 (branched at 10) is B
Tested by the engineering O2 instruction, which branches if the pin is low. The ability to branch at step 10 is useful for polling a single interrupt separately from the interrupt register. 710, B work O bin is not latched. This makes B-work commands useful for monitoring equipment that needs to be serviced only when certain conditions are true or become true.

External read/write operations The processor provides program, data, and processor address space for interfacing to external memory and the processor. Access to these address spaces is controlled by PS, Da, (program, data and I10 selection) f processor signals on the control bus 13. The devices are straightforward because the processor processes each address space in the same way.

The order of external read cycles is as follows.

1) In phase 3, the processor begins driving the address bus and one of the memory space select signals. R/W is driven high to indicate an external memory read.

2) ``/4 At the start of phase 4, generate 5TRB to indicate that the address bus is correct.8TR
B is used for r-) the read activation signal in conjunction with R/W.

6) After decoding the addressed memory area, the user's memory interface must set the appropriate READY signal during phase 4 (1).

l/, R1! by the processor at the beginning of phase 1!
ADY is sampled.

4) If REA and DY are high at the appropriate time, 1/4
At the end of phase 1cI), data is timed input.

5) '/4 Phase 2c/) Start RIC8TRB
k'! It gets pulled in. Address bus and PS, DB
, or each time S is deenergized, the processor terminates the memory access.

The control signals PS, Ds, 5TRBj and R/W are issued only when accessing the external Azores location ai.The order of the external write cycle is as follows.

1) At clock 4 phase 3, the processor begins driving the address bus and one of the memory space select signals. R/W is driven low to indicate an external memory write.

2) l/, at the beginning of phase 4, 8TRB is asserted to indicate that the address bus is correct.

The 5TRB associated with R/W is used to output the write enable signal.

6) After decoding the addressed memory area, the user's memory 12 interface registers RE during l/4 phase 40.
Appropriate logic levels must be applied to the ADY signal input. R by the processor at the beginning of 1/4 phase 1
EADY is sampled.

4) At the start of l/47 aids 4, the data bus begins to be driven.

5) The processor terminates the memory access by deenergizing the O address space and PS, DB, or S, which are pulled in by 5TRB at the beginning of '/4 phase 2.

The number of cycles for memory or I10 access is determined by the state of the READY input. l/, at the beginning of phase 1, the processor samples the READY input. R.E.
If ADY is high, memory access is 0LKO.
(TT10 ends on the next falling edge. If READY is low (/,), the memory cycle is extended by one machine cycle and all other signals remain correct.

At the start of the next quarter phase 1, this order is repeated.

Although the present invention has been described with reference to illustrated embodiments,
The description is not intended to be construed in a limiting sense.

Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. It is therefore believed that the appended claims cover such modifications and embodiments as fall within the true scope of the invention 8+1.

The following sections are further disclosed in connection with the above description.

(11) In the microcomputer device, a) an L microcomputer element formed into a single integrated circuit having a data input/output terminal and an address output terminal, and (c) a memory device outside the microcomputer confectionery having an address input device and a data output device and c) an input/output peripheral device for transferring information to or from an external device, the input/output peripheral device having an address input device and a data input/output device, and 2) an address output terminal of a microcomputer element. an external address bus device coupled to an address input device of the peripheral device and an address input device of the memory device; an external data bus device coupled to a data input/output device and a data output device of the memory device; and a) an arithmetic/logic device having a data input and a data output within the integrated circuit of the microcomputer device; A first read/output device with an address input and a data input/output device.
a write memory; and an internal memory coupled to the data input and output of the arithmetic/logic unit and the data input/output device of the first read/write memory.
- a second read/write memory having an address input and a data input/output device for storing data or instruction words; and a program connected to the address input of the second read/write memory. - an addressing device; an internal program bus device coupled to the data input/output device and the data input/output terminal of the second read/write memory; and an internal program bus device coupled to the program addressing device; has an input coupled to bus vc#L;
a control device for generating microcontrol signals in response to command words, said signals defining operations in arithmetic/logic units and transfers between internal bus devices; a first block move instruction that copies the contents of a series of consecutive memory addresses from the device to a first read/write memory; and a second block move instruction that copies the contents of a series of memory addresses to a second read/write memory. A microcomputer device comprising: the control device including a device for executing a block movement command; and the microcomputer element including:

(2) In the apparatus according to paragraph 1, the timing device and program address device are configured to set a repeat operation cycle in which data is repeatedly transferred from the first memory to the data input (111c/). By applying an address to the address input of the memory of No. 2, the control unit receives command words from the program memory and the microcomputer lif! in which successive cycles of said operating cycles overlap. .

+3 Jfig Section 1 ct) A microcomputer device in which the internal data bus device t refers to a bus with a width of N bits, and the data input and the output of the arithmetic/logic unit are 2N bits wide.

(4) In the apparatus set forth in paragraph 1, the data input/output device of the second read/write memory is configured to control the data input/output device of the second read/write memory in response to a control signal from one of the instruction words (CI). A microcomputer device alternately coupled to either a data bus device or the internal program bus device.

(5) The apparatus of claim 1, wherein for each of the first and second block move instructions, the series of addresses are generated in the program address device, and
The arrival address of the read/write memory of the first and second
microcomputer device 11° generated by a data memory addressing device connected to said address input of the read/write memory of the

[Brief explanation of the drawing]

The first reason is the electrical wiring diagram of a microcontroller device block format using the features of the present invention, and FIG. The electrical wiring diagram of the microcomputer X (including the central processor unit) in block form, FIG. 6 is similar to FIG. 2, but includes the features of another embodiment of the present invention. The electrical wiring diagrams in block form, FIGS. 4a and 4b, are memory maps of the logical address space of the elements of FIGS. 2 and 3, respectively. 10...Microcomputer, 11...
...Memory, 12...Engineer 10 equipment, 13...
・・・Control bus, 14...ROM, 15・Old・
・On-chip RAM. ALσ... Arithmetic logic unit, Acσ...
accumulator. M... Multiplier, more than i, more than 2...
・Instruction decoder, PC...Program counter, ARQ, ARI...Auxiliary address register, D bus...Data bus, P bus...
...Program bus, 15P...2nd
RAM 0

Claims (1)

[Scope of Claims] A microcomputer device comprising: (a) a microcomputer element formed in a single integrated circuit having a data input/output terminal and an address output terminal; and (b) an external microcomputer element having an address input device and a data output device. c) an input/output peripheral device for transferring information to or from an external device, the input/output peripheral device having an address input device and a data input/output device; and d) a microcomputer element. an external address bus device coupled to an address output terminal and coupled to an address input device of the peripheral device and an address input device of the memory device; e) an external address bus device coupled to the data input/output terminal of the microcomputer device; an external data bus device coupled to a data input/output device of a peripheral device and a data output device of a memory device; a first read/output device having an address input and a data input/output device;
a write memory; an internal data bus device coupled to the data input and data output of the arithmetic/logic unit and the data input/output device of the first read/write memory; and an address input and data input/output device. , a second read/write memory for storing data or instructions; a program addressing device connected to an address input of the second read/write memory; and a program address device connected to an address input of the second read/write memory; an input/output device; an internal program bus device coupled to the data input/output terminal and coupled to the program address device; an input coupled to the program bus device; a controller for generating control signals, said signals determining operations of arithmetic/logic units and transfers between internal bus devices; Executing a first block move instruction that copies the contents of a series of consecutive memory addresses to a write memory and a second block move instruction that copies the contents of a series of memory addresses to a second read/write memory. A microcomputer device comprising: the control device including the control device; the microcomputer element including the microcomputer element.