JPS6123487A - Digital processor of video signal - Google Patents

Abstract

PURPOSE:To increase a sampling speed by (n) times as fast as before by performing (n)-fold time-base expansion of every scanning line of a digital video signal, performing processing at a speed 1/n time as fast as the sampling speed, and performing (n)-fold time-base compression of the processed video signal. CONSTITUTION:A time-base expanding circuit TE writes a supplied digital video signal in line memories M1-M3, line by line, at the same speed as the sampling speed under the control of a memory control circuit MCE. The circuit TE reads a video signal of one line which is already written out of the memories M1-M3 at a speed a half as fast as the sampling speed simultaneously with said writing operation. A time-base compressing circuit TC writes the video signal of one line which is already processed and supplied from digital processing circuits P1-P3 at a speed a half as fast as the sampling speed under the control of a memory control circuit MCC. The circuit TC reads out and outputs the one-line processed video signal which is written in parallel to the writing operation at a speed twice as fast as the writing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION Industrial Application The present invention relates to a digital processing device for video signals used in high definition television and the like.

BACKGROUND OF THE INVENTION In recent years, with the development of digital technology, digital processing of video signals is being carried out even in television receivers installed around the bottom of cabins. Digital signal processing of this type includes removal of noise generated in the transmission path, correction of distortion, enhancement of edges, separation of luminance signals and color signals using signal correlation between frames and lines, and interpolation of frames and lines. There are a wide variety of non-interlaced designs.

There is also a trend toward wider band video signals, such as in high-definition television.

Problems to be Solved by the Invention Regarding television video signals, it is necessary to perform the above-mentioned digital signal processing in real time, and there is a problem in that as the sampling rate increases, the signal processing cannot keep up. In particular, signal processing using a recursive digital filter such as flare correction requires a long processing time, and pipeline processing cannot be applied, so there is a problem that the sampling rate cannot be increased very much.

Structure of the Invention The digital processing device of the present invention solves the problems of the prior art as described above.
By expanding the time axis by a factor of 2, processing this time axis expanded digital video signal at a speed of 1/n of the sampling speed, and compressing the time axis by n times the processed digital video signal, the result is equivalent to that of the conventional method. It is configured to increase the sampling speed by n times compared to the conventional method while using a digital signal processing circuit having a processing speed of .

Hereinafter, the operation of the present invention will be explained in detail by way of examples.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, IN is an input terminal.

TE is a time axis expansion circuit, PI, P2 and P3 are all digital signal processing circuits of the same configuration, TC is a time axis compression circuit, OUT is an output terminal, and CLK is a clock signal supply circuit.

The time axis expansion circuit TE includes three line memories M each having a storage capacity of one line of digital video signals.
1, M2, and M3, and a memory control circuit MCE that provides a write/continuation address to each of these in-memories M1 to M3 and controls the write/continuation operation thereof. Similarly, the two time axis compression circuits TC each have a
Three line memories M4. have a storage capacity of a line's worth of digital video signals. M5 and M6, and a memory control circuit MCC that provides a write/continuation address to each of these line memories M4 to M6 and controls the write/continuation operation thereof.

A digital video signal sampled at a predetermined sampling rate and A/D converted is supplied to the time axis expansion circuit TE.

The time axis expansion circuit TE processes the supplied digital video signal at a rate equal to its sampling rate under the control of the memory control circuit MCE.

One line is written cyclically into each of the three line memories M1 to M3. In parallel with this write operation, the time axis expansion circuit TE transfers the written digital video signal for one line to three line memories M1 to M3.
is read at half the sampling speed. The digital video signals read out from the line memories M1 to M3 are supplied to three digital signal processing circuits P1 to P3 arranged at the subsequent stages, respectively.

The digital video signals processed by the digital signal processing circuits P1 to P3 are supplied to a one-time axis compression circuit TC.

The time axis compression circuit TC, under the control of the memory control circuit MCC, converts one line of processed digital video signals supplied from each of the preceding stage digital processing circuits P1 to P3 at half the sampling rate mentioned above. Write at speed. Time axis compression circuit TC.

In parallel with the above write operation, the processed digital video signal for one line that has been written is read out at twice the write speed, that is, at a speed equal to the above sampling speed, and these are output to a common output terminal. do.

The above-mentioned series of operations consists of time axis expansion, digital signal processing, and time axis compression of the processed video signal.

This is performed in synchronization with the clock signal supplied from the clock signal supply circuit CLK.
1. FIG. 2 is a timing chart for explaining the above series of operations in more detail. In this figure,
The symbols W and R indicate that the corresponding line memory operations are write and read operations, respectively.

The first line L1 of the digital video signal supplied to the time base expansion circuit TF is written into the line memory M1 at a rate equal to the sampling rate. The next line L2 is written to line memory M2 at a rate equal to the sampling rate. A third line L3 is written to line memory M3 at a rate also equal to the sampling rate. In parallel with the above writing operation, reading is performed at half the sampling speed (half the writing speed) starting from the line memory for which 1947 minutes of writing has been completed.

That is, at the same time as the writing to the line memory M1 ends, the first line L1 is read out at half the sampling speed and supplied to the digital signal processing circuit Pl. Similarly, when writing to line memory M2 ends, 1
The next line L2 is read out at half the sampling speed and supplied to the digital signal processing circuit P2. Similarly, the third line L3 is connected to the digital signal processing circuit P.
3.

In this way, in each line memory, one horizontal scanning period is spent to write one line, and two horizontal scanning periods are spent to read one written line. That is, from when each line memory starts writing one line until it finishes reading it.

A total of three horizontal scanning periods are spent. Therefore, at the time when the fourth line (2), 4 is supplied to the time axis expansion circuit TE with a delay of three horizontal scanning periods from the first line L1,
The line memory M1 finishes reading out the first line L1, and becomes ready to newly write this line L4.

The same holds true for the other line memories M2 and M3. In this way, each line memory repeats cyclic writing and reading for one line after three horizontal scanning periods.

The processed digital video signal L1° of 1947 minutes is processed by the digital signal processing circuits P1 to P3.
L2', I, 3'... are 1 time axis compression circuit TC
is supplied to line memories M4 to M6 within.

For convenience of illustration, assuming that there is no delay time in the digital signal processing circuit, reading of the first line L1 from the line memory M1 in the one-time axis expansion circuit TE is started, and at the same time, the one-time axis compression circuit TC starts reading out the first line L1. The writing of the first processed line 1,1" to the line memory M4 of All the above operations are completed at the same time, and the same is true for line memories M5 and M6.

That is, each of the digital signal processing circuits P1 to P3 processes the digital video signal of 51 sampling points in a time period twice as long as the sampling period.

Actually, each line memory M in the time axis compression circuit TC
The start point of writing from 4 to M6 is 1 time axis expansion circuit T.
The start time of reading from each line memory M1 to M3 in E is delayed by the delay time associated with digital signal processing in digital signal processing circuits PI to P3.

Therefore, in reality, the time axis showing the operations of the line memories M4 to M6 is shifted to the right in the delay time diagram above than the time axis showing the operations of the line memories M1 to M3. However, since the delay times occurring in the digital signal processing circuits P1 to P3 are the same,
The above-mentioned temporal relationships for the operation of line memories M4 to M6 remain unchanged.

In parallel with the writing of the processed digital video signal, the time axis compression circuit TC sequentially writes data at a speed twice the writing speed (
The readout is performed at a speed equal to the sampling speed).

That is, at the same time as the writing to the line memory M4 ends, the first processed digital video signal I,1'' for one line is read out at the sampling speed and supplied to the common output terminal OUT. Similarly, line memory M5
Simultaneously with the end of the writing to the second processed digital video signal L2° is read out at the sampling rate and applied to the common output terminal OUT. Third and subsequent processed digital video signals■, 3', L4', L5'...
* are output one after another to the common output terminal OUT in exactly the same way.

Above, we have shown an example of a configuration in which digital signal processing is performed by expanding the 1-time axis by 2 times, and then compressing the time axis by half after processing. However, when expanding or contracting the 1-time axis by 3 times, the 2-time axis expansion circuit T is used.
It is sufficient to add one line memory to each of E and time-base compression circuit TC, and to add one digital signal processing circuit. Generally, in order to expand or contract one time axis by n times, n+1 line memories are installed in each of the two time axis expansion circuits TE and the time axis compression circuits T and C.

It is sufficient to install n+1 digital signal processing circuits.

FIG. 3 is a block diagram showing the configuration of an embodiment of the second invention.

In this figure, IN is an input terminal, TE is a time axis expansion circuit, Pll and PI3 are digital signal processing circuits, TC is a time axis compression circuit, and OUT is an output terminal.

CLK is a clock signal supply circuit.

The time axis expansion circuit TE includes line memories Mll and MI
a first line memory pair consisting of 2;

It includes a second line memory pair consisting of line memories M13 and M14, and a memory control circuit MCE that supplies addresses and control signals to each of these line memory pairs.

This time axis expansion circuit TE inputs the digital video signal input to the input terminal IN, one line at a time, in the input order, alternately to each line memory pair, and to two line memories in each line memory pair. write at a rate equal to the sampling rate.

In parallel with the write operation, the time axis expansion circuit TE reads out the 1947-minute digital video signal that has been written at half the writing speed (sampling speed) and sends it to the digital signal processing circuits pH and PI3 in the subsequent stage. supply

The digital signal processing circuits pH and PI3 process the time-base expanded digital video signals supplied from each of the line memories in the time-base expansion circuit TE in the previous stage, and convert the processed digital video signals into time-base compressed signals in the subsequent stage. Supplies circuit TC.

The time axis compression circuit TC includes line memories M1.5 and M1.
6, a second line memory consisting of line memories M17 and M2O, and a memory control circuit MCC that supplies addresses and control signals to these line memory pairs. . Each line memory pair has one output signal from the corresponding digital signal processing circuit.
Lines of processed digital video signals are written to two line memories alternately at half the sampling speed, and one line of processed digital video signals for which writing has been completed is sampled. read at a speed equal to the conversion speed.

FIG. 4 is a timing chart for explaining the above series of operations in more detail.

The first line L1 of the digital video signal supplied to the time axis expansion circuit TE is written to one line memory Mll in the first line memory pair. The next rai,
Line L2 jumps to the second pair of line memories and is written to one of them, line memory M13. The third line L3 returns to the first line memory pair and is now written to the other line memory M12. The fourth line L4 returns to the second line memory pair again and is now written to the other line memory M14.

All of the above writes are performed at a rate equal to the sampling rate.

In parallel with the above writing operation, reading is performed at half the sampling speed (half the writing speed) starting from the line memory for which 1547 minutes of writing has been completed. That is, line memory M in the first line memory pair
Simultaneously with the completion of writing to ll, the first line L1 is read out at half the sampling speed and supplied to the digital signal processing circuit pH. Then, simultaneously with the completion of writing to the line memory M13 in the second line memory pair, this one line L2 is read out at half the sampling rate and supplied to the digital signal processing circuit P12. Similarly, the third and fourth lines L3. L4 is also read out at half the sampling speed immediately after the writing is completed, and the digital signal processing circuits pH and P L , 2
supplied to

In this way, in each line memory, one horizontal scanning period is spent to write one line, and two horizontal scanning periods are spent to read one written line. This is similar to the case of the digital processing device shown in FIG. However, in the digital processing device shown in FIG. 3, as mentioned above, one line of digital video signals is input in the order
1st.Write alternately to the second line memory pair and the two line memories in each line memory pair.

It is configured to start reading immediately after writing is completed.

Therefore, the first line memory pair is responsible for time axis expansion of the odd lines Ll, L3, 1.5, . . . , while the second line memory pair is responsible for the even line L2 . L
4. It will be in charge of extending the time axis of L6...

Since read operations do not overlap in the two line memories in each line memory pair, one line of digital video signals read from each line memory in the same line memory pair is processed by the same digital signal processing circuit. It can be processed by

FIG. 5 is a block diagram showing the configuration of another embodiment of the second invention. The digital processing device of this embodiment is configured to expand the time axis of a digital video signal by three times line by line, perform digital signal processing, and then compress the time axis to one-third. In Figure 5, the components with the same alphabetic symbols as in Figures 1 and 3 are shown in Figure 1.
This is similar to that described with reference to FIGS.

Therefore, redundant explanations regarding these will be omitted.

The time axis expansion circuit TE consists of three line memory pairs (M2
1. M22), (M2S, M24), (M2S, M
26). One line of digital video signals read out from the three line memory pairs in the time axis expansion circuit TE are supplied to three digital signal processing circuits P21 to P23 disposed in the subsequent stage of each, and are processed into one sample. Digital signal processing takes three times the sampling period per point. The processed digital video signal for one line is stored in three line memory pairs (M27, M28),
(M29.M2O) and (M31.M32) are supplied to the time axis compression circuit TC.

The operation of the video signal digital processing apparatus shown in FIG. 5 will be explained below with reference to the timing chart shown in FIG.

Digital video signals L1 and L2 input to input terminal IN
．． L3... is input one line at a time in the order of input.
The memory pairs are written cyclically and alternately to the two line memories within each line memory pair at a rate equal to the sampling rate. In parallel with the above writing operation, the time axis expansion circuit TE reads out the digital video signal for one line for which writing has been completed at a speed (sampling speed) that is 1/3 of the writing speed, and outputs the digital video signal to the subsequent digital signal processing circuit P2.
1. Supplied to P22 and P23.

The three line memory pairs in the time axis compression circuit TC store one line of processed digital video signals L1° and L output from the digital signal processing circuits 21 to 23 in the previous stage.
2', L3'...

1 of the sampling rate alternately for the two line memories.
/3, and the processed digital video signal for one line for which the writing has been completed is read out at a speed equal to the sampling speed.

As described above, in the second invention, configurations for expanding and contracting the one time axis by two times and three times are illustrated in FIGS. 3 and 5, respectively, but in general, for expanding and contracting the three time axis by n times.

It is sufficient to install n line memory pairs (2n line memos) and n digital signal processing circuits in each of the time axis expansion circuit TE and time axis compression circuit TC.

As mentioned above, in the second invention, in which the line memories of the two time axis compression circuits and the time axis compression circuit are configured as a pair to perform cyclic writing and reading, the line memory necessary for expansion and compression of the two time axis is 2(n-1) than in the case of the first invention.
) will increase by the number of pieces.

However, the number of digital signal processing circuits is only one less than in the case of the first invention, regardless of the expansion/contraction magnification n of the time axis. Therefore, the more complex and expensive the configuration of the digital signal processing circuit, the more the time axis expansion/contraction magnification n.
The smaller the value, the greater the effect of simplifying the device configuration and reducing the cost according to the second invention.

FIG. 7 is a block diagram showing an example of a more specific configuration of the digital processing device shown in FIG. 3.

This digital processing device is configured to expand one time axis twice, perform horizontal flare correction in a digital signal processing circuit, and then compress one time axis in half.

The time axis expansion circuit TE consists of two line memory pairs (M4
1. M42), (M43.M44).

The two digital signal processing circuits P53 and P54 each include two recursive digital filters REC for horizontal flare correction, and one line memory pair (M2S) for time axis inversion.

M46) and (M47.M48). In addition, the 1 time axis compression circuit/TC has two line memory pairs (M4
9. M2O), (M51.MS2).

Recursive digital filter REC for horizontal flare correction
I to REC4 are as shown in FIG.

Digital adder circuit S, three digital delay circuits DI
, D2 and D3. Three digital coefficient circuits Kl, 2 and 3 consisting of ROM etc. and a digital adder circuit A
It consists of

FIG. 9 is a timing chart for explaining the operation of the video signal digital processing apparatus shown in FIGS. 7 and 8. FIG. In this figure, the horizontal axis is the time axis, the vertical axis is the increase/decrease in addresses in each line memory M41 to M52, and W and R indicate that the operation of each line memory is a write operation and a read operation, respectively. It shows.

The write and read operations of the four line memories M41 to M44 in the time axis compression circuit TC are exactly the same as the write and read operations already explained with reference to FIGS. 3 and 4. The digital video signal for one line read from the line memories M41 and M42 belonging to the first line memory pair in the time axis compression circuit TC is passed through a 9-cycle digital filter RECI to the line memory for time axis inversion. versus M
45 and M46.

If we ignore the delay time in the two-circuit digital filter RECI for convenience of illustration, then the line.

At the same time as the reading of line L1 from memory M41 is started, digitally filtered line L1 is written to line memory M45 for time axis inversion. The line L written in the time axis reversal line memory 45 is a 1547 minute digital video signal L1 which is read out from an address in the opposite direction to that in the writing at the same speed as in the writing and whose time axis is inverted by one time. The signal is then supplied to the subsequent recursive digital filter REC2.

Line L1 processed by the cyclic digital filter RFC2 is written to line memory M49, which also serves as 2-time inversion and time axis compression, and is written from an address in the opposite direction to the writing speed at twice the writing speed. Read out. By passing the signal through the cyclic digital filter in this way, reversing the time axis, and passing it through the cyclic digital filter again, it is possible to cancel out the phase change caused by the filtering process.

As will be apparent from reference to the remainder of FIG. 9, each subsequent line L2. L3. Exactly the same digital signal processing is performed for L4....

In the embodiment shown in FIG. 7, the time axis is reversed in the 8 time axis compression circuit TC, but instead of this, a configuration may be adopted in which the time axis is reversed in the 2 time axis expansion circuit TE.

FIG. 10 is a block diagram showing the configuration of an embodiment of a digital processing device according to the third invention.

This digital processing device, like the device shown in FIG. 7, expands the time axis by two times and performs horizontal flare correction in the digital signal processing circuit.

It is designed to compress the time axis in half.

Digital video signals L1 and L2 input to input terminal IN
．． L3... is input one line at a time.

9 in the time axis expansion circuit TE at a rate equal to the sampling rate.
The data is written cyclically to the line memories M41 to M43. Immediately after writing one line to each line memory is completed, reading begins at half the sampling rate. Digital video signals read from each line memory.

The signal is alternately supplied to two digital signal processing circuits P53 and P54. That is, taking the line memory M41 as an example, the first line L1 read from there is supplied to the digital signal processing circuit P53, and the first read line L4 is in turn supplied to the digital signal processing circuit P54. , the third read line L7 is again supplied to the digital signal processing circuit P53.

One line of processed digital video signals Ll and L2 output from two digital signal processing circuits P53 and P54
．． L3 . . . are written cyclically into the three line memories M49 to M51 in the one-time axis compression circuit TC at half the sampling speed. The processed digital video signal for one line that has been written is read out from the corresponding line memories M49 to M51 at a speed equal to the sampling speed.

In the device shown in Figure 10, the control is slightly more complex than in the device shown in Figure 7, in that the signal transfer paths between each line memory for two-hour expansion and contraction and the two digital signal processing circuits are alternated. Become. however.

The device of FIG. 10 has the advantage that it requires two fewer line memories for one time axis expansion/contraction than the device of FIG. 7.

Generally, when the time axis is expanded or contracted by n times according to the third invention, n digital signal processing circuits and (n+1) time axis expansion/contraction line memories placed before and after the circuits are provided. , (n+
1) If a video signal is cyclically written in one line unit to n line memories, and the read out time-axis expanded video signal for one line is cyclically supplied to n digital signal processing circuits. good.

Effects of the Invention As explained in detail above, the video signal digital processing device according to the present invention performs time axis expansion of a digital video signal by a factor of n in line units, and processes the time axis expanded digital video signal by a factor of n. On the other hand, the configuration performs the desired digital signal processing at a speed of 1/n of the sampling speed and compresses the time axis of the processed digital video signal to 1/n, so it is possible to achieve digital signal processing with the same processing speed as the conventional one. This has the effect of increasing the sampling speed by n times compared to the conventional method while using a circuit.

In addition, since the configuration performs time axis expansion/contraction and digital signal processing on a line-by-line basis, the horizontal retrace period can be used as a preparation period from the end of one line's processing to the start of the next line's processing. Therefore, there are advantages in that the configuration is easy and stable operation is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the device shown in FIG. 1, and FIG. 3 is a block diagram of an embodiment of the second invention. FIG. 4 is a timing chart for explaining the operation of the device in FIG. 3, FIG. 5 is a block diagram showing the configuration of another embodiment of the second invention, and FIG. Timing chart 7 for explaining the operation of the device shown in FIG.
8 are block diagrams showing a more specific configuration example of the device shown in FIG. 3, FIG. 9 is a timing chart for explaining the operation of the device shown in FIGS. 7 and 8, and FIG. FIG. 10 is a block diagram showing the configuration of an embodiment of the third invention, and FIG. 11 is a timing chart for explaining the operation of the device shown in FIG.
It is a chart. IN: Input terminal, TE: Time axis expansion circuit. Pi, P2. P3. P'll, Pi2. P21. P22
, P23. P53. P54...Digital signal processing circuit, TC...Time axis compression circuit, CLK...Clock signal supply circuit, Ml to M6. Ml 1 to M18. M21-M3
2. M41~M52...Line memory, MCB, MC
C...Memory control circuit, OUT...Output terminal, RECI
to RFe5... recursive digital filter. Patent applicant: NEC Home Electronics Co., Ltd. (1 other person)

Claims (3)

[Claims] (1) In a device that processes a digital video signal sampled at a predetermined sampling rate and converted into a digital signal, (n+1) digital signal processing circuits (n is a natural number of 2 or more); The digital video signal for each scanning line is written cyclically in the input order of each scanning line at a speed equal to the sampling speed, and the digital video signal for one scanning line that has been written is written at one of the sampling speed. /n at a speed of (n+
1) A time axis expansion circuit having (n+1) line memories supplied to each of the digital signal processing circuits, and processing for one scanning line supplied from each of the (n+1) digital processing circuits. The processed digital video signal is written at a speed of 1/n of the sampling speed, and the processed digital video signal for one scanning line for which the writing has been completed is read out at a speed equal to the sampling speed to provide a common output. 1. A digital processing device for a video signal, comprising: a time-base compression circuit having (n+1) line memories output to a terminal. (2) A device that processes a digital video signal sampled at a predetermined sampling rate and converted into a digital signal, comprising n digital signal processing circuits (where n is a natural number of 2 or more); It is equipped with n line memory pairs disposed respectively in the front stage of the digital signal processing circuit, and scans the input scanning lines in the order of input, cyclically for each line memory pair, and 2 memory pairs in each line memory pair. alternately write to a line memory of at a rate equal to the sampling rate, and
a time axis expansion circuit that reads the digital video signal for one scanning line for which the writing has been completed at a speed of 1/n of the sampling speed and supplies it to the corresponding n digital signal processing circuits; It is equipped with n pairs of line memories each arranged after the signal processing circuit, and the processed digital video signal for one scanning line output from the corresponding digital signal processing circuit is stored in two memory pairs in each line memory pair. alternately for line memories of 1/1 of the sampling rate.
Write at a speed equal to n, and write 1 at the end of the write.
1. A digital processing device for a video signal, comprising: a time-base compression circuit that reads the processed digital video signal for a scanning line at a speed equal to the sampling speed and outputs the read signal to a common output terminal. (3) A device that processes a digital video signal sampled at a predetermined sampling rate and converted into a digital signal, comprising n digital signal processing circuits (where n is a natural number of 2 or more) and one scanning line. At the same time, the digital video signals for one scanning line for which writing has been completed are written cyclically in the input order of each scanning line at a speed equal to the sampling speed. a time axis decompression circuit having (n+1) line memories that are read out at a speed of The processed digital video signal for one scanning line is written cyclically at a speed of 1/n of the sampling speed, and the processed digital video signal for one scanning line that has been written is written at the sampling speed. 1. A time-base compression circuit having (n+1) line memories read at a speed equal to , and output to a common output terminal.