JPS61234447A - Bus acuisition controller - Google Patents

Abstract

PURPOSE:To eliminate the need for a communication area and a start control program by adding setting of a master designation register and write to a master identification register when a bus master accesses a memory under the management of other bus master. CONSTITUTION:When the bus master 31 accesses a memory 14, the bus master 31 sets a designation number of a bus master 30 to a master register 20, outputs a bus using request signal to a bus arbitor 33, inputs an operation permitting signal, set the content of the register 20 to an identification register 22 and outputs again a bus using request signal to the bus arbitor 33. The designation of the bus using request signal to the bus arbitor 33. The designation of the bus master 30 by the bus master 31 is identified by the master identification circuit 33 depending on the content, a bus operation managing control circuit 15 is stopped and a bus connection control circuit 28 is started. Then a bus using request control circuit 18 acquires the right of use of the bus 2, then a bus using permission signal is outputted to the bus master 31.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bus acquisition control device for a two-bus system.

2. Description of the Related Art An example of a conventional bus acquisition control device for a two-bus system is a ``graphic display device that processes graphic changes and viewpoint movements independently of the host.''

Maeda et al.9 Nikkei Electronics 1984.6゜18
It is disclosed in PP205-232.

FIG. 3 is a block diagram of a bus acquisition control device for such a conventional two-bus system. 1.2 is bus, 3 is bus 1
4.6 is a bus use arbitration control circuit that manages the use of bus 1 and bus 2, respectively. 6.7 is a bus use arbitration control circuit that outputs a bus 1 use request signal to 4. 8.9 is a bus use arbitration control circuit which outputs a bus 2 use request signal to the bus arbitration control circuit 5 and controls data transfer by receiving the use permission signal as input. This is a usage request control circuit. 1o is a bus master including a bus switch 3, a bus request control circuit 6, and a path request side control circuit 8; 11.12 is a bus request control circuit 7.9, respectively.
13 and 14 are memories connected to bus 1 and bus 2, respectively.

In the above configuration, the memory 13 is shared by the bus master 1o and the bus master 11, and the memory 14 is shared by the bus master 10 and the bus master 12. Here, the operation when the bus master 11 reads the contents of the memory 14 will be described. The bus master 11 transfers the bus master 1 to the communication area set in the memory 13.
Write 0 start command. Next, the bus master 10
After reading and decoding the instructions written in the communication area in the memory 13 and transferring the contents of the memory 14 to the memory 13, instruction execution completion information is written in the communication area in the memory 13. Finally, the bus master 11 reads the transfer end information written in the communication area in the memory 13, detects the end of the transfer from the memory 14 to the memory 13, and reads out the contents of the memory 13.

Problems to be Solved by the Invention However, such a configuration requires a communication area in the memory 13 for controlling the activation of the bus master 1o and the bus master 11. Also, memory 1 by bus master 10
4 to the memory 13 is necessary, and an area in the memory 13 to store the data after the transfer is also required.

Furthermore, there is a problem in that a startup control program for the bus master 10 and the bus master 11 that is controlled using the communication area of the memory 13 is required. This problem similarly occurs when the bus master 12 accesses the contents of the memory 13. As the number of bus masters connected to bus 1 and bus 2 increases, the increase in the communication area within the memory and the complexity of the activation control program for cooperative operation between the bus masters become more serious problems.

In view of the above problems, the present invention provides a bus acquisition control device that can eliminate the need for a communication area and a startup control program for cooperative operation with other bus masters when a bus master accesses memory on a bus to which it is not connected. The purpose is to provide.

Means for Solving the Problems The present invention provides a first bus that manages the use of two buses. A second bus arbitration control circuit, a bus switch that connects and disconnects two buses, and a first bus switch that connects the bus switches and controls data transfer between the two buses. A second bus connection control circuit, a master designation register that stores a bus master designation number, a master identification register that stores the output contents of the master designation register, and a bus master on the bus is designated by inputting the output of the master identification register. The first step is to identify whether or not there are any. a second master identification circuit; and a first master identification circuit that activates the bus connection control circuit of the designated bus master when the master identification circuit identifies that the bus master is designated. A bus acquisition control device comprising a second master use request control circuit.

Operation According to the present invention, when a bus master accesses a memory under the control of another bus master, the bus master is designated by the master designation register and a normal bus use request is made. After the contents of the master designation register are stored in the master identification register and the designated master is identified by the master identification circuit, the bus connection control circuit of the designated master is activated to establish a bus connection with the target memory. As a result, cooperative operations between bus masters are controlled by the master use request control circuit and the bus connection control circuit, eliminating the need for a communication area in memory or a startup control program. In other words, a bus master can perform the same bus acquisition control to access the memory it manages and the memory managed by another bus master, with the only difference being whether or not the master designation register is used.

Embodiment FIG. 1 is a block diagram of a bus acquisition control device in a first embodiment of the present invention. In the figure, 1.2 is the bus, 3 is the bus switch, 13.14 is the memory, and the above is the third
The configuration is the same as the one shown in the figure.

1ffi and 16 are bus use arbitration control circuits that manage the use of bus 1 and bus 2, respectively; 17 is a bus use arbitration control circuit that outputs a bus 1 use request signal to the bus use arbitration control circuit 16 and inputs a use permission signal to control data transfer. Bus use request control circuit, 1
8 is a bus use request control circuit that outputs a bus 2 use request signal to the bus use arbitration control circuit 16 and inputs a use permission signal to control data transfer; 19, 20.21 is a master that stores other bus master designation numbers; Designated register, 22.23
24.25 is a master identification register that stores the output of the master designation register; 24.25 is a master identification circuit that identifies the designated bus master based on the contents of the master identification register 22.23; 26.
27 is a master use request control circuit that outputs a connection request signal of the bus switch 3 to the bus master identified by the master identification circuit 24 and 26 and inputs a connection completion signal; 29 is a master use request control circuit which inputs a connection request signal to activate the bus use request control circuit 18 to obtain the use of the bus 2, connects the bus switch 3, and outputs a connection completion signal; A bus connection control circuit that inputs a connection request signal for the bus switch 3 from the circuit 27, activates the bus use request control circuit 17, acquires the use of the bus 1, connects the bus switch 3, and outputs a connection completion signal. be. 30.
31 is a bus master connected to bus 1, 30.32 is a bus master connected to bus 2, 30.31.32 have the same configuration, and 33.34 are bus arbiters for bus 1 and bus 2, respectively.

The operation of this embodiment will be explained below. bus master 30.3
1 accesses memory 13, bus arbiter 3
This is done after acquiring the right to use the bus with 3. When the bus masters 30 and 32 access the memory 14, they do so after acquiring the right to use the bus with the bus arbiter 34. When the bus master 31 accesses the memory 14, the bus master 31 first sets the designated number of the bus master 30 in the master designation register 2o, outputs a bus use request signal to the bus arbiter 33, inputs a usage permission signal, and then sets the designated number of the bus master 30 in the master designation register 2o. The contents of are set in the master identification register 22. Next, a bus use request signal is outputted to the bus arbiter 33 again. At this time, the master identification circuit 33 identifies that the bus master 31 has designated the bus master 30 based on the contents set in the master identification register 22, and stops the bus use arbitration control circuit 15, causing the master use request control circuit 26 to stop.
This activates the bus connection control circuit 28 of the bus master 3o. As a result, after the bus use request control circuit 18 acquires the right to use the bus 2 with the bus arbiter 34, the bus switch 3 is connected and a connection completion signal is input to the master use request control circuit 26, and the bus use arbitration control circuit continues its operation and outputs a bus 2 use permission signal to the bus master 31.

The above series of operations allows the bus master 31 to access the memory 14. When the bus master 32 accesses the memory 13, it can be accessed by the same operation as when the bus master 31 accesses the memory 14.As described above, according to this embodiment, when the bus master 31 accesses the memory 14, 32 accesses the memory 13, the bus master only needs to set the designated number of the bus master to the master designation register and write to the master identification register, and data transfer between the memories 13 and 14 by the bus master 3o, A buffer area for transfer data on the memories 13 and 14, a communication area on the memories 13 and 14 for controlling start-up between bus masters, and a start-up control program are no longer required. FIG. 2 shows a second embodiment of the present invention. FIG. 2 is a block configuration diagram of a bus acquisition control device in an example. In the figure, 36 to 42 are buses, and 43 to 60 are bus masters.
It is the same as ~32.

61 to 58 are memories, and 59 to 66 are bus arbiters.
This is the same as the bus arbiters 33 and 34 shown in the figure. This embodiment is an example in which the bus arbiter is configured hierarchically, and the bus master here is a processor having an arithmetic processing function.

The operation of this embodiment will be explained below. Processor 43 manages processors 44.46, and processors 44.45 manage processors 46.47 and 48.49, respectively.
the processor 46 manages the processor 50;
The overall configuration is to perform hierarchical processing. 4 shows memory that can be accessed by processor 46; The memory 54 managed by itself, the memory 68 by designating the lower hierarchy processor 6o as the master, the memory 65 by designating the same hierarchy processor 47 as the master, the memory 62 managed by the upper hierarchy processor 44 by accessing the bus 36. By designating the upper layer processor 44 as the master, the memory 61 managed by the two-level upper layer processor 43 can be accessed. This eliminates the need for an inter-processor activation control program for memory access between processors in a hierarchical configuration, and the burden on the control program can be reduced even in the case of a multi-level hierarchical configuration.

As described in detail, according to the present invention, when a bus master accesses memory under the control of another bus master, it is only necessary to add a setting to the master designated register and a write operation to the master identification register. The same bus acquisition control as accessing the underlying memory can be performed. Therefore, there is no need for a communication area or a data buffer area on the memory, and furthermore, there is no need for a startup control program. This effect becomes greater as the number of bus masters increases, and the practical effects of the present invention will be greater in the future when large-scale processing systems will be required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bus acquisition control device in a first embodiment of the present invention, FIG. 2 is a block diagram of a bus acquisition control device in a second embodiment of the present invention, and the taS diagram is a block diagram of a bus acquisition control device in a second embodiment of the present invention. FIG. 2 is a block configuration diagram of a bus acquisition control device of the bus system. , 1...First bus, 2...Second bus, 3.Tune/bus switch, 16...First bus use arbitration control circuit, 16... ...Second bus use arbitration control circuit, 17...First bus use request control circuit, 18...Second bus use request control circuit, 19... ...Master specification register, 22...
...First master identification register, 23...Second
master identification register, 24...first master identification circuit, 25...second master identification circuit, 2
6...First master use request control circuit, 27.
...Second master use request control circuit. Figure 1 Figure 2 4.1 Figure 3

Claims (5)

[Claims] (1) First and second buses, a bus switch that connects the first and second buses, outputs a bus use request signal to the first bus, and transfers data by inputting a bus use permission signal. a first bus use request control circuit that controls the second bus; and a second bus use request control circuit that outputs a bus use request signal to the second bus and controls data transfer by inputting a bus use permission signal. , first and second bus connection control circuits that connect the bus switch and control data transfer; a bus master consisting of a master designation register that can output to any of the buses; first and second bus use arbitration control circuits that respectively manage the use of the first and second buses; Are first and second master identification registers storing outputs to the first and second buses, respectively, and a bus master on the first bus specified by inputting the output of the first master identification register? a second master identification circuit that receives the output of the second master identification register and identifies whether a bus master on the second bus is designated; When the bus master is identified as being designated, a connection request signal of the bus switch is output to the first bus connection control circuit of the designated bus master, and a connection completion signal is input. , a first master use request control circuit that outputs a second bus use permission signal to the first bus use arbitration circuit, and an output of the second master identification circuit, and the bus master is identified as being designated. After outputting a connection request signal of the bus switch to the second bus connection control circuit of the designated bus master and inputting a connection completion signal, a first bus use permission signal is output to the second bus use arbitration circuit. a second master use request control circuit that outputs a second master use request control circuit. (2) The first bus connection control circuit activates the second bus use request control circuit when the bus switch connection request signal is input from the first master use request control circuit, and Claim 1: After inputting a second bus use permission signal from a use request control circuit and connecting the bus switch, a connection completion signal of the bus switch is output to the first master use request control circuit. The bus acquisition controller described. (3) The second bus connection control circuit activates the first bus use request control circuit when the bus switch connection request signal is input from the second master use request control circuit;
A first bus use permission signal is inputted from a bus use request control circuit of the second master use request control circuit, and after the bus switch is connected, a connection completion signal of the bus switch is outputted to the second master use request control circuit. 2. The bus acquisition control device according to claim 1. (4) The first bus use arbitration control circuit inputs the bus use request signals of all the bus masters connected to the first bus, and when outputting the bus use permission signal to one of them, the first bus use arbitration control circuit outputs the bus use permission signal to one of the bus masters. If the first master identification circuit identifies that the bus master to which the signal is output is not designated as a master, immediately outputs the bus use permission signal, and if the first master identification circuit identifies that the bus master is designated as a master. case 1
2. The bus acquisition control device according to claim 1, which outputs a bus use permission signal after inputting a bus switch connection completion signal from a master use request control circuit. (5) The second bus use arbitration control circuit inputs the bus use request signals of all the bus masters connected to the second bus and outputs the bus use permission signal when outputting the bus use permission signal to one of them. If the second master identification circuit identifies that the previous bus master has not designated the master, it immediately outputs a bus use permission signal, and if the second master identification circuit identifies that the bus has been designated as the master, the second master Claim 1: A bus use permission signal is output after inputting a connection completion signal of the bus switch from a master use request control circuit.
Bus acquisition control device as described in Section 2.