JPS61228658A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a memory element, which can sufficiently hold the withstanding voltage between a P<+> diffused layer and an N<+> diffused layer without decreasing integration density, by providing a structure, in which the P<+> diffused layer and the N<+> diffused layer are isolated in the longitudinal direction. CONSTITUTION:Boron is doped in the inner wall of a groove 44 formed by a second groove formation, and a P<+> diffused layer 6 is formed. Then, an SiO2 film 2 and an Si3N4 film 3 are selectively removed in order to form a contact hole 7 at the end part of the groove capacitor. A capacitor insulating film 8 is formed. Then, after polycrystalline silicon 9 is formed on the entire surface of a wafer in gaseous phase, the polycrystalline silicon on the surface of the Si3N4 film is removed, and the groove 44 is buried by polycrystalline silicon 9. The contact hole 7 is formed by photoetching technology again. Thereafter, a polycrystalline silicon electrode 11 is formed. By the diffusion of N-type impurities in the polycrystalline silicon electrode, an N<+> diffused layer 10 is formed on the surface of a substrate at the part of the contact hole. At this time, the N<+> diffused layer 10 and the P<+> diffused layer 6 are separated by about 0.5-1mum so that sufficient withstanding voltage is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device Knit, a dynamic RAM
[Prior art] Integrated circuits formed on semiconductor substrates, especially silicon semiconductor substrates, are becoming increasingly highly integrated and have a large capacity, and integrated circuits such as memory devices have a capacity of 1M bits or more. The degree of integration is increasing. Currently, in IC memories such as dynamic RAMs, a system consisting of a storage unit (cell) or one MOS transistor and one capacitor is suitable for increasing the capacity and is the mainstream. In order to realize a DRAM with a storage capacity of 1 megabit or more per chip, the key is how to reduce the area of one element, especially the area of the capacitor, which occupies most of the element area. Therefore, as a means to reduce the area of a capacitor, a method has been proposed in which a groove is dug in a silicon substrate and the inner wall and bottom surface of the groove are used to form a capacitor. (1
982Inferna-1ional Elecfr
ou Devices Meeting, Techui
calDigest PP, 806-808), for example #1 on the surface of the P-type silicon substrate, as shown in Figure 2 1a).
4, and after forming a Knn dispersed layer 0 in the groove, a capacitor is formed by the capacitor insulating film 8 and the electrode 9. In the cell of this structure, since the groove 1 [1 is used as a capacitor, the area covered by one element tooth is small.

However, in this method, charge is stored in the On+ diffusion region 10 on the surface of the semiconductor substrate, so if the cell spacing is made closer to achieve higher density, the stored charge may interfere with neighboring cells due to punch-through. Because of leakage and the formation of deep grooves, when a semiconductor substrate is irradiated with electromagnetic radiation such as alpha rays, the generated carriers tend to gather in cells, so they are carriers of stored information. The disadvantage is that the charge is easily lost. As a means of solving this,
As shown in Figure 2(b)K, a method has been proposed in which charges are accumulated on the electrode 9 side within the groove (Japanese Patent Laid-Open No. 59-82761).

That is, in this structure, a groove is formed on the surface of a P-type silicon substrate,
After forming the VcP+ diffusion layer 6 on the surface of the silicon substrate within the trench, a capacitor is formed between the insulating film 8 and the electrode 9.

Further, the electrode 9 is connected to an n+ diffusion layer 10 which becomes a source or drain of an n-channel MOS transistor 13. Using this cell, even if the cell spacing is brought close, mutual interference will not occur, and the substrate will be irradiated with 11-element radiation such as alpha rays.
Even if a charge is generated inside the substrate, it is difficult for this charge to enter the cell structure, so it is possible to prevent the movement of the pieces due to alpha rays, and it is considered to be extremely effective for the cell structure of a high-density, highly integrated AM.

[Problem that the invention seeks to solve]

However, in this method, when a voltage is applied to the electrodes, a depletion layer expands on the substrate surface, causing a decrease in capacitance, which needs to be prevented. That is, DRAM
It is a storage method that detects the potential difference depending on the amount of accumulated electric charge and distinguishes the information Jl and IQ#.
Since the potential difference of 'l"l"O@ makes it easy to read large group signals and prevents malfunctions, it is undesirable for the capacitance value to decrease due to a change in the voltage applied to the capacitor electrode. Therefore, it is necessary to dope a high concentration of impurity into the portion of the lacon substrate in contact with the trench capacitor to suppress the growth of the depletion layer.

That is, in the case of an n-channel device, the surface portion of the substrate in contact with the groove capacitance is coated with a high concentration of Pg (1011 to 10*oc*-
It is necessary to dope it.

- The electrode 9 of the blind groove capacitance is an n-channel MOS) transistor 1
It is necessary to make ohmic contact with one of the n0 regions 1O which will be the source or drain of No. 3. However, when the +P diffusion layer 6 and the n diffusion layer 10 come into contact, the breakdown voltage between the inner junctions is significantly lowered, resulting in a problem in that the charge stored in the groove capacitance flows out to the substrate. The most effective solution to this problem is to separate the LiP diffusion layer 6 and the n+ diffusion layer 10 in position, but separating the inner diffusion layer in a plane increases the area occupied by the l cell. undesirable.

The present invention provides a novel multi-element structure that improves the above-mentioned conventional drawbacks.
The structure is such that the diffusion layer 6 and the n-diffusion layer 10 are separated in the vertical direction.

That is, in the present invention, the memory element has the feature that the breakdown voltage of the P diffusion layer 6 and the n-doped diffusion layer 10 can be sufficiently maintained without reducing the integration density. 1 is a diagram illustrating the manufacturing process for forming the memory element structure according to the present invention shown in FIG. 1, in which a P-type substrate is used as a semiconductor substrate 1 and a channel cell is taken up. For the P-channel type, simply replace n with PKil. In the figure, 1 is a semiconductor substrate, 6 is a P+ diffusion layer, 8 is a capacitive insulating film, 9 is a polycrystalline silicon electrode, 7 is a polycrystalline silicon electrode 9 and an n+ diffusion layer 10 of an n-channel MOSFET 13
It is a contact hole that connects the 14 is MOSFET
This is a word line that also serves as the gate electrode of No. 13. Figure 3 (a
) to (h), the manufacturing process for forming a memory cell having the structure shown in FIG.
Figure (a) As shown in K&C1~5x101'cr'' impurity concentration on the surface of P type single crystal silicon substrate 1.
After forming the thick film 2 and the 8i1N4 film 3, a well-known photoetching technique is used to remove the 8i3N4 film 3 in desired areas. Stow membrane2. The silicon substrate 1 is sequentially etched to form a first groove 4. As shown in FIG. 5ins membrane 2 and 8i3N4
The preferred thickness of the membrane 3 is about 500A and 10A, respectively.
00Afi degree. Although there is no particular restriction on the depth of the groove provided in the silicon substrate 1, it is preferable that the groove be etched to about 1 to 2 .mu.m (first groove formation).

(b) Next, an 8i01 film 5 is formed on the entire surface of the wafer.

This 840g film 5 is used as a mask to prevent boron from diffusing into the groove sidewalls. The 840g film 5 needs to be formed on the side walls of the trench, and may be formed by thermal oxidation or low pressure vapor phase growth, or by thermally oxidizing the polysilicon film once formed. You can also set it as @5.

In addition, an 8i@N4 film was further formed to form an 840. and Si2N
It may be a two-layer structure film with three films. The film may have a current of about 1,000 to 3,000 A in order to prevent boron diffusion.

(C1) Next, the first groove 4 is etched deeper by reactive ion etching to form the groove 44 of @2 (second groove formation). After the etching is removed, the etching of the 84 substrate 1 proceeds, but since the 8i01 film 5 on the trench sidewall is difficult to be etched, it can be used satisfactorily as a mask for later diffusion.

(d) Add 10% boron to the inner wall of the groove 44 formed by forming the second groove.
A P layer 6 is formed by doping 1$~10m'1C11''3.

The 8i01 film 5 remaining on the side wall of the groove 4 of the static elimination 1 serves as a mask for bone diffusion, and boron is not diffused into this portion.

Therefore, the P layer 6 is formed only on the inner wall of the lower portion of the groove 44.

(e) Next, the K 8 i 0 film 2 and the 8iHN4 film 3 are selectively removed to form a contact hole 7 at the end of the trench capacitor, and then a capacitor insulating film 8 is formed. This capacitor insulating film 8 may be an 810g film obtained by thermally oxidizing the substrate, or may have a two-layer structure of a Si pseudo film and an 84HN4 film, and the choice is free. The thickness of the capacitive insulating film 8 is preferably about 100 to 200 A in terms of Sin, 11. Next, polycrystalline silicon 9 is grown in a vapor phase over the entire surface of the wafer, and then the polycrystalline silicon on the surface of the %8fN4 film 3 is removed and the grooves 44 are filled with polycrystalline silicon 9. If the groove 44 is not filled with polycrystalline silicon 9 at one time, repeat the vapor phase growth and etching several times.#i The groove is filled with polycrystalline silicon 9. During or after forming the polycrystalline silicon 9Ku film, an impurity such as phosphorus is doped to make it sufficiently n-type.

(f) Next, after forming the contact hole 7 again using photoetching technology, a polycrystalline silicon film is formed,
Subsequently, a polycrystalline silicon electrode 11 is formed by photoetching technology. The polycrystalline silicon electrode 11 is in contact with the substrate 1 through the contact hole 7, and as the n-type impurity in the polycrystalline silicon electrode diffuses, an n+ diffusion layer 10 is formed on the substrate surface in the contact hole portion. . At this time, the n+ diffusion layer 10 and the P diffusion layer 6 are separated by about 0.5 to 1 .mu.m to obtain a sufficient breakdown voltage. Next, word lines and bit lines will be formed on the polycrystalline silicon 11, so thermal oxidation will be performed! 13000 to 6000 A1 degree 8i0 gossamer 12 is formed.

(g) After etching and removing the Si3N4 film a, sto, and film 2, which are the first films, an n-channel l'140BFET 13 to be used as a transfer gate is formed using a conventional method. folded bit 1ine
type of cell structure, the relevant MOSFE71
The gate electrode 14 of No. 3 serves as a word line, and the word line of the adjacent cell is placed on the polycrystalline silicon electrode 9 via the 8i01 film 12.

(hl After forming an interlayer insulating film 15 and forming a desired contact hole, a bit line is formed using an aluminum wiring 16.

As described above, according to the present invention, after forming the first trench, a deep trench is dug by reactive ion etching to form the second trench while leaving an impurity diffusion mask on the side wall, and then P-type impurities are introduced. By forming the P diffusion layer only in the deeper part of the groove, it is possible to maintain a sufficient distance between it and the n+ diffusion layer which becomes the source or drain of the MOS 11''ET.
The withstand voltage between the P+ diffusion layer and the n+ diffusion layer is improved, and information loss can be prevented. The depth at which the P layer is formed is determined by the groove depth in the first groove forming step of the semiconductor device Fi according to the present invention. Since the groove depth can be sufficiently controlled, this skeleton device can be realized with high yield.

〔Effect of the invention〕

In the present invention, the high-concentration impurity region of the trench capacitance section and the source/drain region of the transistor section can be separated in the vertical direction, so that the breakdown voltage of this portion is improved. Mata l cell @
Since the area of the disk can be reduced, a high-density D-RAM can be realized.

[Brief explanation of drawings]

FIG. 3 is a cross-sectional view of an element schematically explaining a process. l...Silicon substrate, 2...8i0.
Membrane, 3...8i, N, membrane, 4...groove,
5...810m film (second film), 6...
・P diffusion layer, 7...contact hole, 8...
... Capacitive insulating film, 9 ... Polycrystalline silicon, 1
0...n+ diffusion layer, 11...polycrystalline silicon, 12...8fO, film, 13...
・N-channel MOSFET. 14... Word line, 15... Interlayer insulating film, 16... Al ξ wiring. Agent: Susumu Uchihara, patent attorney Figure 1

Claims (1)

[Claims] A capacitor formed by laminating an insulating film and an electrode in a groove provided on the surface of a semiconductor substrate, the inner wall of which is provided with a highly concentrated impurity layer of the same type as the semiconductor substrate, and an electrode of the capacitor as described above. In a dynamic memory element configured with a MOS transistor connected to either a source or drain impurity region provided on the surface of a semiconductor substrate, a highly concentrated impurity layer provided on the inner wall of the capacitor connects to the source of the transistor. Alternatively, a semiconductor device characterized in that the semiconductor device is provided in a deep inner wall portion away from the surface of the semiconductor substrate to the extent that it does not come into contact with an impurity region that becomes a drain.