JPS61225862A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To initialize the entire memory cells without losing an integration by providing a memory cell to control the potential of a floating gate in case of writing or erasing data by a control gate formed of a diffused layer. CONSTITUTION:A control gate (CG) 11 made of an N-type diffused region and a floating gate (FG) 12 made of a polycrystalline silicon layer are formed in a data storing MOS transistor (Tr) 2. A common region 13 has the source of a selecting MOSTr 1 and the drain of an MOSTr 2. A selecting gate (SG) 16 is formed in the MOSTr 1. An electron absorbing control gate 31 formed of a polycrystalline silicon layer is formed through an insulating layer on the electrode 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a read-only semiconductor memory device in which data can be electrically erased.

ETechnical Background of the Invention] A read-only semiconductor memory device in which data can be electrically erased is known as an EEPROM. FIG. 5 is a circuit diagram showing the basic structure of the memory cell. This memory cell is constructed by connecting in series a selection MOS transistor 1 having a selection gate SG and a data storage MOS transistor 2 having a control gate CG and a floating gate FG. The end is connected to the drain D, and the open end of the data storage MOS transistor 2 is connected to the source S, respectively.

When this cell is realized using, for example, a single-layer polycrystalline silicon process, the device structure will be as shown in the pattern plan view of FIG. In the cell shown in FIG.
The control gate (CG) of the OS transistor 2, 12 is a polycrystalline silicon layer and the floating gate (FG) of the MOS transistor 2 for data storage, and 13 is an N-type diffusion region that serves as the source of the MOS transistor for selection and data storage. a common region consisting of the drain of the MOS transistor 2; 14 the source (S) consisting of an N-type diffusion region;
15 is the train (D) consisting of an N-type diffusion region, 1B
is a selection gate (SG) of the selection MOS transistor made of a polycrystalline silicon layer, and regions 17 and 18 surrounded by broken lines in the figure are regions provided with a thin insulating film for gates.

The operating principle of such a memory cell is that data is stored by exchanging electrons between the common region 13 and the floating gate 12 using a thin insulating film in regions 17 and 18 surrounded by broken lines. MOS transistor 2 for
The threshold voltage vth of the memory is changed, thereby programming or erasing data. The bias relationship when programming or erasing this data is summarized in FIG.

By the way, sorting out (die sorting) defective chips in such a memory starts with initializing the memory. That is, the ratio of electrons stored in the floating gate is made constant for all bits, and at this time it is checked whether all bits have the same logic. Next, we check the amount of electrons stored in each bit, that is, check the read margin, and investigate the pattern dependence of each bit.

[Problems of the background art] Test functions such as those described above are indispensable in a PROM. If initialization is performed in the process of writing data into a normal FROM, no special circuit is required for the test function, but the data writing time becomes long, such as several milliseconds per bit. As a result, it takes a long time to initialize,
There is a problem that sorting efficiency deteriorates. On the other hand, if a circuit for initializing has a function that erases all bits, for example, it is possible to set all selection gates to a high potential, drop all drains to the reference potential, and raise all control gates to a high potential. In addition to the normal functions, it is necessary to add a logic gate for this initialization function to each driver. Therefore, the area of the circuit other than the memory cell portion becomes large. Furthermore, the number of circuit parts through which data passes during reading increases, and the access time for reading increases. On the other hand, when checking the read margin, data is read while adjusting the potential of the control gate, and in this case as well, it is unavoidable that additional logic gates are added due to the addition of the above-mentioned functions.

[Objective of the Invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to reduce the degree of integration of cells and peripheral circuits by performing initialization of all memory cells, margin checking, etc. The object of the present invention is to provide a semiconductor memory device that can be realized without the use of a semiconductor memory device.

[Summary of the Invention] In order to achieve the above-mentioned object, the semiconductor memory device of the present invention includes a semiconductor memory device composed of a polycrystalline silicon layer by utilizing the tunneling phenomenon of a first insulating film provided on a semiconductor substrate. Data is written or erased by injecting electrons into the floating gate or emitting electrons from the floating gate, and when writing or erasing data, the potential of the floating gate is changed to the first It has a memory cell controlled by a control gate, and a second control gate made of a polycrystalline silicon layer is provided to the floating gate via a second insulating layer, and the potential of the second control gate is By operating the floating gate and this second
Electrons are injected or emitted between the control gate and the control gate.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a pattern plan view when a memory cell of a semiconductor memory device according to the present invention is constructed of two MOS transistors as shown in FIG. 5. Note that the memory cell of this embodiment is also realized using a polycrystalline silicon process, as in the case of FIG. 6 above. The memory cell shown in FIG. 1 is different from the one shown in FIG. The point is that a control gate 31 is provided.

FIG. 2 is a cross-sectional view of the memory cell shown in FIG. 1 taken along the line AA', and 32 is an insulating layer provided between the floating gate 12 and the control gate 31 for absorbing electrons. ,3
3 is a field insulating layer, and 34 is a common area 13
This is a gate insulating layer provided between the floating gate 12 and the floating gate 12. The thickness of the gate insulating layer 34 is the same as that of the insulating layer 3.
2, and the value of the capacitance occurring between the floating gate 12 and the control gate 11 is made larger than the capacitance occurring between the floating gate 12 and the control gate 31 for electron absorption. ing.

In such a memory, the capacitive coupling between the common region 13 and the floating gate 12 is relatively large, and when the common region 13 is set to a low potential, the floating gate 12 is also pulled to a low potential. When the potential of the control gate 31 for electron absorption is increased in this state, electrons flow from the floating gate 12 to this control gate 31, and the threshold voltage vth of this cell increases.
falls and enters the program state. As is well known, there is a protrusion called an asperity on the upper surface of the polycrystalline silicon layer, and electron emission above the floating gate 12 occurs at an electric field of about 3 to 4 MV/cm. On the other hand, downward emission of electrons requires an electric field of about 8 to 9 MV/cm since no asperity exists. Therefore, the control gate 3 for electron absorption
If the potential of 1 is set to a low potential in the normal operation mode, there will be no adverse effect on the electron retention characteristics or the like. Furthermore, since the electric field at which upward emission of electrons occurs in the floating gate 12 is low, the capacitance between the floating gate 12 and the control gate 31 for absorbing electrons is small, and the effect on the normal operation of the cell can be almost ignored. can.

In addition, in order to put all bits in the initial state, that is, in the programmed state, it is sufficient to provide the above-mentioned 11J'IB gate 31 in common, and there is no need to add a logic circuit for each driver as in the conventional case. The degree of integration of peripheral circuits can be increased.

Further, the amount of electrons emitted from the floating gate 12 to the control gate 31 depends on the voltage applied to the control gate 31 and the application time of this voltage.

Therefore, by applying a pulsed voltage to the control gate 31, the amount of electrons in the floating gate 12 can be changed in an analog manner, and if a read operation is performed in this state, a read margin check of the cell can be performed. I can do it.

In this way, in the memory of the above embodiment, since the polycrystalline silicon layer is simply added to the conventional one, the control gate 31 for electron absorption made of this polycrystalline silicon layer is
As shown in the pattern plan view of FIG. 3, if it is provided in common for a plurality of upper and lower cells, the degree of integration of the cells themselves will not be impaired.

In addition, since the area to which high voltage is applied is small, there is no need to apply high voltage to the selection gate 16 at the time of initialization, for example, and therefore high voltage is not applied to its driver as well. The occurrence of leakage current can be significantly reduced compared to other devices, and the reliability of the device is also improved.

FIG. 4 is a sectional view of a memory cell according to another embodiment of the invention. This embodiment differs from the one shown in FIG. 2 in that a control gate 31 for absorbing electrons is arranged below the floating gate 12. In this case, electrons are transferred from the control gate 31 to the floating gate 12.
As a result, the cell enters a state in which electrons are forcibly injected, that is, an erased state. As for the bias conditions, since the coupling between the floating gate 12 and the control gate 11 is strong, the control gate 11 may be kept at a high potential and the control gate 31 may be kept at a low potential. At this time, selection gate 16
The potential of is irrelevant during this mode of operation.

In a memory having such a configuration, the control gate 31 may be fixed at a predetermined potential. Further, in normal operation, in a memory having such a configuration, data is written in the order of erasing byte by byte and then programming by bit, and the potential of the control gate 11 changes in units of selected bytes. Therefore, during the erasing process in the normal mode, electrons may be emitted from the control gate 31, but during the programming process, the electric field is applied in the opposite manner, so electrons are unlikely to flow out to the control gate 31. Note that due to the ease of emission due to asperity on the upper surface of the control gate 31, the floating gate 12 and the control gate 31
As in the above embodiment, the thickness of the insulating layer 32 between the two layers can be increased, and the capacitive coupling therebetween can be reduced.

[Effects of the Invention] As explained above, according to the present invention, there is provided a semiconductor memory device in which initialization of all memory cells, margin checking, etc. can be realized without impairing the degree of integration of cells and peripheral circuits than in the past. can be provided.

[Brief explanation of drawings]

FIG. 1 is a plan view of a pattern of a memory cell of a semiconductor memory device according to the present invention, FIG. 2 is a cross-sectional view of the memory cell of FIG. 1, and FIG. 3 is a case where a plurality of memory cells of the above embodiment are integrated. FIG. 4 is a pattern plan view of a memory cell of a semiconductor memory device according to another embodiment of the present invention, FIG. 5 is a circuit diagram showing the basic configuration of a memory cell of EEPRO''M, and FIG. The figure is a pattern plan view showing the conventional element structure of the cell shown in Fig. 5, and Fig. 7 is a diagram summarizing the bias relationship when programming or erasing data in the cell shown in Fig. 5.11.・Control gate, 12...Floating gate, 13・
... common region, 14 ... source, 15 ... drain, 16 ... selection gate, 31 ... control gate for electron absorption. Application fee: Patent attorney Takehiko Suzue Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (5)

[Claims] (1) By injecting electrons into a floating gate made of a polycrystalline silicon layer by utilizing the tunneling phenomenon of a first insulating film provided on a semiconductor substrate, or by emitting electrons from a floating gate. The memory cell has a memory cell in which data is written or erased, and the potential of the floating gate is controlled by a first control gate made of a diffusion layer when writing or erasing data, and A semiconductor memory device characterized in that a second control gate made of a polycrystalline silicon layer is provided with a second insulating layer interposed therebetween. (2) The semiconductor memory device according to claim 1, wherein the second control gate is arranged above the floating gate. (3) The semiconductor memory device according to claim 1, wherein the second control gate is arranged below the floating gate. (4) The value of the capacitance existing between the floating gate and the second control gate is smaller than the value of the capacitance existing between the floating gate and the first control gate. The semiconductor memory device according to item 1. (5) The semiconductor memory device according to claim 1, wherein the second control gate is provided in common to a plurality of memory cells.