JPS61224564A - Picture reader - Google Patents

Abstract

PURPOSE:To fix stably a black level signal over the entire page of the original by applying arithmetic a voltage of a prescribed value at an arithmetic circuit to an output signal of a solid-state image pickup element when it is discriminated that the output of the element at dark state is not within a set value. CONSTITUTION:A digital comparator 12 brings the level of output terminals 12a, 12b to H when a picture signal A and a comparison signal B are in the relation of A>B and A=B, and brings the level of an output terminal 12c to an H level when A<B, and brings it to an L in other cases. An AND gate 14 receives a count pulse in the cases other than A=B. When a dummy picture element of a CCD 1 is scanned A>B is established, and when a count pulse comes, the counter 16 counts up by a count pulse from an AND gate 13, the quantity of subtraction to a picture signal from the CCD 1 is increased at a substractor 10 and the signal A is decreased. When A<B, the signal A is increased. The operation above is repeated at each incoming of the signal A and it continues until A=B is established. So long as a decreasing voltage is given to the substractor 10 on the condition of A=B, the black level is fixed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image reading device using a solid-state image sensor such as a CCD image sensor, and more specifically, to an image reading device that can remove offset voltage and accurately fix the black level. The present invention relates to an image reading device configured as described above.

[Prior art]

For example, the CCD image line sensor l is shown in FIG. 3(a).
When light is uniformly irradiated onto the pixel row 1a shown in , dummy pixels 1b (pixels that are not illuminated) at both ends of the pixel row 1a
The voltage Va (black level voltage) obtained at , and the voltage vb (white level voltage) obtained at the effective pixel portion evenly irradiated with light are offset voltages V. FF! This is a voltage including ET. Therefore, its offset voltage V. FF3! When T changes due to changes in temperature or other conditions, the voltage
There is a problem that Ja and Vb fluctuate.

Therefore, conventionally, as shown in FIG. 4, the output of the CCD image line sensor 1 is input to the subtracter 2, and
A part of the output is manually supplied to the sample hold circuit 3, and the sample hold circuit 3 is used to generate a dummy pixel 1b.
The voltage Va obtained at
(horizontal scanning period), and the voltage Va is subtracted from the output voltage of the CCD image line sensor 1.

As a result, the black level of the output signal from the CCD image line sensor 1 obtained as shown in FIG. 5(a) is fixed to Ov, and the offset voltage is removed, as shown in FIG. 5(b). It becomes a signal. Vc is a white level voltage,
Corresponds to voltage vb.

However, this method cannot hold for a long time due to the hold characteristics of the sample-and-hold circuit 3, and therefore the IH period becomes long (for example, 1 ms or more).
Alternatively, when attempting to retain the text of one page of a document, there is a problem in that the black level fluctuates.

Furthermore, depending on the characteristics of the sample-and-hold circuit 3, the offset voltage may not be completely removed, and is particularly susceptible to fluctuations due to temperature characteristics and the like.

Furthermore, the dummy pixel 1b of the CCD image line sensor 1
If light leaks to a portion, an accurate black level signal Va cannot be obtained, and offset voltage removal will be incomplete.

[Purpose of the invention] The purpose of the present invention is to maintain the black level signal for a long period of time.

An object of the present invention is to provide an image reading device that is stably fixed and solves the above problems.

[Structure of the invention]

For this purpose, the image reading device of the present invention determines whether or not the dark output from the solid-state image sensor is within the set value. The voltage is calculated by an arithmetic circuit.

〔Example〕

Examples of the present invention will be described below. FIG. 1 shows one embodiment of the present invention, in which 10 is a subtracter having an amplification function, 11 is an A/D converter that converts the output analog signal of the subtracter 10 into a digital signal (for example, 8 bits),
12 is a digital comparator that compares the output signal A from the A/D converter 11 with a preset comparison signal B (for example, 8 bits); 13 to 15 are AND gates that input the output of the comparator 12; , 16 is an up-down counter (digital storage means) that inputs the outputs of AND gates 13 and 15, and 17 is a D/A that converts the output digital signal of the counter 16 into an analog signal and inputs it to the subtracter 10. It is a converter.

The comparison signal B of the digital comparator 12 has a value between the black level signal (for example, rllllllllJ) and the white level signal (for example, roooooooooJ) (for example,
lllOJ ).

Further, the digital comparator 12 outputs an image signal A and a comparison signal B.
When A>B, output terminal 12a is set to H (high level).
When A=B, the output terminal 12t is set to H, and when A<B, the output terminal 12c is set to H. At other times, it is set to L (low level).

Furthermore, the AND gate 14 is open to accept count pulses when A=B is not the case.

Now, the dummy pixel 1b of the CCD image line sensor 1
When the image signal A obtained by scanning is larger than the comparison signal B, since A>B, one input of the AND gate 13 becomes H, and when a count pulse arrives at this time, the AND gate 13 outputs that signal. A count pulse is input to the UP terminal of the counter 16, and the counter is counted up. Therefore, the output from the D/A converter 17 increases the amount of subtraction in the comparator 10 for the image signal from the CCD image line sensor 1, and the image signal A decreases. Conversely, when A x B, the counter 16 counts down and the image signal A increases.

This negative feedback operation is repeated every time a count pulse arrives, that is, every time an image signal A from a dummy pixel arrives.
Continues until =B.

However, if a count pulse is input every time a dummy pixel is scanned, it will take time until A=B, so CC
If the dark area is read by the D-image line sensor 1 and a pulse with the same period as the scanning pulse is applied as a count pulse to the AND gate 14,
A=B can be established by scanning one line of the dark area.

Alternatively, if the count pulse is made high-speed and a plurality of count pulses are inputted to the dummy pixel portion, reading scanning of the dark portion is not necessary. - Then, if A=B, the dummy pixel portion or the dark portion, that is, the black level portion (dark output) is obtained as a constant value (comparison signal B). Then, as long as the subtraction voltage (this voltage becomes the offset removal voltage) is applied to the subtracter 10 under the conditions at this time, the black level is fixed.

Since the counter has a memory function, the black level once fixed can be stably fixed.

Therefore, not only can the black level be reliably fixed during the reading scan of one line of the CCD image line sensor l, but also it is not necessary to input count pulses during image reading. Even if light leakage occurs in some dummy pixels, the black level will not change.

FIG. 2 shows another embodiment. In this embodiment, in order to keep the output signal of the subtracter 10 constant when detecting a dummy pixel or a dark area, a digital comparator is not used, and the power supply 21 of the reference voltage ■□, the analog comparator 23, and the reference voltage Comparison means using a power supply 22 with a voltage V RtF +Δ■, an analog comparator 24, and two AND gates 25 and 26 are used.

If the output voltage of the subtracter 10 is z, the output voltage of the comparator 23 is Vx, and the output voltage of the comparator 24 is vy, then VREF < V z < VBy + ΔV −
At the time of (1), Vx and Vy become L level signals and the negative feedback loop becomes stable. That is, the output signal Vz of the subtracter 10 when detecting a dummy pixel or a dark part
The system becomes stable when the condition of formula (1) is satisfied.

In this case as well, the black level is fixed by the memory function of the counter 16.

〔Effect of the invention〕

As described above, according to the present invention, since the black level is fixed by the digital storage means, it is possible to stably fix the black level not only for one line of the solid-state image sensor but also for the entire page of the original, and also for the entire page of the original. It is also possible to eliminate the influence of light leakage to the dummy pixels. Furthermore, since no sample-and-hold circuit is used, the effects of instability of that circuit do not occur.

[Brief explanation of the drawing]

FIG. 1 is a black level fixing circuit diagram of an image reading device according to one embodiment of the present invention, FIG. 2 is a black level fixing circuit diagram of another embodiment,
FIG. 3(a) is an explanatory diagram of the COD image line sensor,
(b) is an output waveform diagram of the sensor, Figure 4 is a black level fixing circuit diagram of a conventional image reading device, and Figures 5 (a) and (b).
4 is a waveform diagram for explaining the operation of the circuit of FIG. 4. FIG. DESCRIPTION OF SYMBOLS 1... COD image line sensor, 2... Subtractor, 3... Sample hold circuit, 10... Subtractor,
11...A/D converter, 12...digital comparator,
13-15...and gate, 16...counter,
17...D/A converter, 21.22...Power supply, 23
．． 24...Comparator, 25.26...And gate.

Claims (2)

[Claims] (1) Determine whether or not the dark output from the solid-state image sensor is at the set value, and if it is not at the set value, calculate a predetermined amount of voltage to the output signal of the solid-state image sensor using an arithmetic circuit. An image reading device characterized by: (2) Claim 1, wherein the arithmetic circuit has a counter, a D/A converter, and an adder/subtractor.
The image reading device described in Section 1.