JPS61219286A - Write clock generating circuit for time base correcting device - Google Patents

Abstract

PURPOSE:To easily obtain a write clock generating circuit for a time base correcting device by outputting the oscillating output of a VCO that is oscillated based upon a reproducing burst signal as a write clock signal and performing a frequency variation signal that is followed with the time base variation of a reproducing video signal. CONSTITUTION:So that a start/stop typed VCO 12 is reset at every horizontal synchronizing section by a start pulse signal STRT that is performed by a reproducing burst signal BURST, the initial phase of a write clock signal WCK coincides with the phase of a reproducing video signal VDIN. Also, the frequency of the write clock signal WCK is converted to a DC voltage signal S15 through the paths of a switching circuit 13 - a frequency discriminating circuit 14 - a peak detection circuit 15 - a witching circuit 16 and is held by a hold circuit 17. A frequency variation signal S19 is converted to a DC voltage signal 16 through the paths of the switching circuit 13 - the frequency discriminating circuit 14 - the peak detection circuit 15 - the switching circuit 16 and is held by a hold circuit 20. These are subtracted at a difference voltage detection circuit 21 and an oscillating frequency is controlled so that its difference voltage signal S21 becomes 0.

Description

DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to generate a write clock signal having accurate phase and frequency information of a reproduced video signal, particularly in a video tape recorder (VTR).

B Overview of Invention The present invention provides a write clock generation circuit for a time axis correction device that generates a write clock signal for a time axis correction memory based on a reproduced burst signal and a reproduced horizontal synchronization signal.
When the oscillation of the oscillator is started based on the reproduction burst signal by voltage control that can control the start and stop,
A frequency discrimination circuit is used to detect the difference between the frequency of the write clock signal formed from the oscillation output and the frequency of the frequency fluctuation signal formed from the reproduced horizontal synchronization signal, and piezovoltage control is performed to eliminate this frequency difference. By controlling a type oscillator, a write clock signal that accurately includes phase information and time axis variation information included in a reproduced video signal is generated with a simple configuration.

C. Conventional technology The time base correction device (TBC) of a VTR has the principle configuration as shown in FIG. The signal BUR8T is separated and input to the write clock generation circuit 2.

The write clock generation circuit 2 is synchronized with the reproduction synchronization signal 5YNC and the reproduction burst signal BUR8T, and therefore generates a write clock signal WCK and a write start pulse signal WZERO with time axis fluctuations. Write clock signal WCK
is given to the analog-digital conversion circuit 3 as a sampling pulse signal, and is also supplied to the memory control circuit 4 together with the write start pulse signal WzERO.

The memory control circuit 4 receives a write start pulse signal WZER.
When O is received, the video signal data VDIN obtained from the analog-digital conversion circuit 3 is inputted by specifying the start address of each scanning line to the memory 5, and then sequentially incrementing the address using the write clock signal WCKK. The data is sequentially written into the memory 5 one scanning line at a time.

The data written in the memory 5 is processed by a read clock generation circuit 6 which receives a reference pulse signal VDREF having a stable period.
is read out by a read clock signal RCK and a read start pulse signal RZERO generated based on the reference pulse signal VDREF.

This video signal data is converted into an analog signal in a digital-to-analog conversion circuit 7 driven by a read clock signal RCK, and a synchronizing signal 5YNCX provided from a read clock generation circuit 6 in a phase adjustment circuit 8.
, burst signal BUR8TX, blank pulse BLKX
is added and sent as the reproduced output signal VDOUT.

In the TBC having the configuration shown in FIG. 5, when writing the video signal data of each scanning line to the memory 5, the reproduced video signal VD
If it is not possible to generate the write clock signal WCK whose phase changes accurately following the jitter included in INK, the memory 5
The playback output signal V cannot be correctly written to the playback output signal V with good reproducibility, resulting in color shift.
It becomes impossible to obtain DOUT.

Problems to be Solved by the Invention Therefore, it is necessary to generate the 8-inclusive lock signal WCK so as to accurately include the phase information and frequency variation information of the reproduced video signal VDIN (Japanese Patent Application No. ω-24669).

Therefore, by simply using the reproduced burst signal BUR8T and applying phase synchronization to generate the write clock signal WCK, even if the initial phase information is satisfied, the frequency fluctuation information cannot be included in the write clock signal WCK. This is not a practical method for VTRs with large frequency fluctuations.

Therefore, conventionally, a method has been adopted in which the frequency fluctuation information is obtained from the reproduced horizontal synchronizing signal K and the phase information is obtained from the reproduced burst signal BUR8T to generate the write clock signal WCK. Then, the generator circuit converts the reproduced horizontal synchronization signal into P L L (Phase I, locked Loop
) circuit to form a signal corresponding to the frequency fluctuation of the reproduced video signal VDIN, and convert this signal into a reproduced burst signal BU.
It is configured to shift the phase so as to be forcibly synchronized with the phase of R8T.

However, this synchronization configuration digitally suppresses fluctuations in signals with frequency fluctuations to within ±172 wavelengths, and the synchronization circuit is configured in an analog manner using a 5V
c, the circuit was complicated.

The present invention has been made in consideration of the above points, and is a write clock for a time axis correction device that can obtain a write clock signal that accurately includes phase information and frequency fluctuation information of a reproduced video signal with a simple configuration. The purpose is to provide a generation circuit.

E Means for Solving Problems In order to solve these problems, the present invention provides a method for writing information into the time axis correction memory 5 based on the playback burst signal BUR8T and the playback horizontal synchronization signal H separated from the playback video signal VDIN. In the write clock generation circuit 2 of the time axis correction device that generates the clock signal WCK, the reproduced horizontal synchronizing signal H is multiplied to form a frequency fluctuation signal 819 whose frequency varies according to the time axis fluctuation of the reproduced video signal VDIN. A PLL circuit 19, a voltage controlled oscillator (VCO) 12 whose start and stop of oscillation can be controlled and which sends out an oscillation output as a write clock signal WCK, and a voltage controlled oscillator (VCO) 12 which can control the start and stop of oscillation and which stops the oscillation of VCO12 based on a reproduction burst signal BUR8T. A start pulse generation circuit 11 that generates a start pulse signal 5TRT for restarting, a frequency discrimination circuit 14 that sends out an output signal 814 whose amplitude changes depending on the frequency of the write clock signal WCK or the frequency fluctuation signal 819, and a frequency discrimination circuit 14 that generates a start pulse signal 5TRT for restarting. A peak detection circuit 16 that obtains a DC voltage signal 815 corresponding to the output signal 814 of the circuit 14, and a DC voltage signal 8 corresponding to the frequency of the write clock signal WCK.
15, a hold circuit that holds the MR voltage signal 815 according to the frequency of the frequency fluctuation signal S19, and a voltage difference between the hold circuit 17 and the held DC voltage signals. , and a differential voltage detection circuit 21 that varies the oscillation frequency of the VCO 12 based on this differential voltage.

2 action VCO1Z&'! , oscillation is started from one wave of the reproduction burst signal BUR8T based on the start pulse signal 5TRT generated by the start pulse generation circuit [1, and the oscillation output is sent out as the write clock signal WCK. Therefore, the cutting phase of the write clock signal WCK is synchronized with the phase of the reproduction burst signal BUR8T, and hence the reproduction video signal VDIN.

Further, the frequency of the write clock signal WCK is detected as an amplitude change in the frequency discrimination circuit 14, further converted into a DC voltage signal in the peak detection circuit 15, and held in the hold circuit 17. On the other hand, the hold circuit I similarly receives an m-current voltage signal corresponding to the frequency of the frequency fluctuation signal S19, which is formed by the PLL circuit I9 based on the reproduction horizontal synchronization signal H to have time axis fluctuations of the reproduction video signal VDIN. will be held.

Therefore, the difference between these held DC voltage signals is O
By giving the control signal S21 from the differential voltage detection circuit 21 to VC012 so that the write clock signal WC
K follows the time axis fluctuation of the reproduced video signal VDIN.

As a result, the write a check signal WCK is the reproduced video signal VD.
Since IN has accurate phase information and time VI axis fluctuation information, when the video signal written in the memory 5 is displayed using this write clock signal WCK, a screen with good reproducibility can be obtained. In this way, the configuration itself becomes much simpler than the conventional one.

G Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. 1st
In the figure, 10 indicates a write clock generation circuit 2 as a whole.
(FIG. 5) shows the write clock generation section.

The write clock generator 1 (l) generates a reproduced burst signal BUR8T separated by the synchronous burst separation circuit 1 (FIG. 5).
is the start pulse generating circuit [1 to 4]. The start pulse generation circuit 11 outputs 0 of the reproduction burst signal BUR8T.
Based on the cross point, one wave of a predetermined period of the burst signal is taken out, pulse-shaped, and applied to a start-stop type voltage-controlled oscillator (VCO) 12.

The start-stop type VCO 12 has a start pulse signal 5.
When TRT is applied, it is reset, the phase is forcibly shifted to the reference phase, and oscillation occurs. The oscillation frequency is selected to be 4f, 36, which is four times the subcarrier frequency fso, and this oscillation output is output as the write clock signal WCK. Also, the write clock signal WCK is the first
The signal is applied to the frequency discrimination circuit 14 via the switching circuit 13.

The frequency discrimination circuit 14 is composed of, for example, a low-pass filter, and its frequency characteristics are as shown in FIG.

A frequency 4fsc, which is four times the subcarrier frequency, is located approximately at the center of the frequency discrimination area (cutoff frequency area) AF, and a frequency band BF in which the frequency 4fsc can vary according to time axis fluctuations of the reproduced video signal VDIN is defined. It is selected to be located within the frequency discrimination area AF. Therefore,
According to this frequency discrimination circuit 14, the write clock signal WC
A discrimination signal 814 whose amplitude changes depending on the frequency of K is obtained.

The peak detection circuit 15 holds the peak voltage of the discrimination signal 814 from the frequency discrimination circuit 14 and converts it into DC voltage, and the DC voltage signal 815 is given to the first hold circuit 17 via the switching circuit 16 of g2. is held.

Here, the first switching circuit 13 and the second switching circuit 16 are switched in conjunction with each other, and the first switching circuit 13
is the first input terminal 1 to which the write clock signal WCK is applied.
3 a When the K is switched, the second switching circuit 1
6 is the first output terminal 1 connected to the hold circuit 17
Switched to 6a. Therefore, the hold circuit 17 is 1
DC voltage signal 81 representing the frequency α of the lock signal WCK
Hold 5.

In addition, in the write clock generation section 1o, the synchronization burst separation circuit 1 (FIG. 5) separates the reproduced synchronization signal 5YNC.
Of these, the reproduced horizontal synchronization signal H is given to the PLL circuit 19. The PLL circuit 19 matches the time axis fluctuation of the reproduced horizontal synchronization signal H as it is, and multiplies it by 5 to produce a subcarrier frequency of 1k.
Frequency 4f, which is four times that of fso.

A frequency fluctuation signal 819 that fluctuates around the same center is obtained and applied to the second input terminal 13b of the switching circuit 13.

Whether the second hold circuit or the switching circuit 13 is connected to the second input terminal 1
3 b K connection, and the switching circuit 16 interlocks to hold the DC voltage signal S15 of the peak detection circuit 15 when it is connected to the second output terminal 16b. Therefore, the hold circuit problem holds the DC voltage signal 815 according to the frequency of the frequency fluctuation signal S19.

The first and second hold circuits 17 and the hold outputs S17 and S20 are respectively given to a differential voltage detection circuit 21 and subtracted therein. The difference voltage signal 821 resulting from the subtraction is a start-stop type VCO.
12 as a control signal.

The VCO 12 receives this control signal S 21 ! ? :, and oscillates so that the frequency a of the write clock signal WCK has the frequency fluctuation that the frequency fluctuation signal 819 has.

Here, the switching circuits 13 and 16 are switched and controlled by a switching control circuit 18. The switching control circuit 18 is supplied with the reproduced horizontal synchronization signal H, and based on this, forms a switching control signal 818 that inverts the logic level for each horizontal synchronization section, and switches the switching circuit 13 and every 16ft horizontal synchronization section.

In the configuration shown in FIG. 1, since the start pulse signal -gsTRTK-CXCX start stop CO12 generated in the start pulse generation circuit 11 from the reproduction burst signal BUR8T is reset every horizontal synchronization period, the write clock signal WCK The initial p phase of the signal matches the phase of the reproduced video signal VDIN.

Further, the frequency of the write clock signal (@) WCK is converted into a DC voltage signal 815 through the path of switching circuit 13 - frequency discrimination circuit 14 - peak detection circuit 15 - switching circuit 16 and is held in hold circuit 17 . On the other hand, the frequency fBL number fluctuation signal 819 formed based on the reproduced horizontal synchronizing signal HK is converted into a DC voltage signal S16 through the above-mentioned path such as switching circuit 13 - frequency discrimination circuit 14 - peak detection circuit 15 - switching circuit 16. The signal is then held by a hold circuit.

These held voltage signals 817 and 820 are subtracted in the differential voltage detection circuit 21, and the differential voltage signal S2
1 is given to the VCO 12, and the rooting frequency is controlled so that the differential voltage indicated by the differential voltage signal 821 becomes zero. Thus, the write clock signal WCK is the frequency variation signal 81
Therefore, the reproduced video signal VDIN has the same time axis fluctuation as that of 9.

As described above, according to the circuit shown in FIG. 1, it is possible to obtain cut-and-paste phase information K from the reproduced burst signal BUR8T and obtain frequency fluctuation information from the reproduced horizontal synchronization signal H, which is the write clock signal WCK. Can be done. Therefore, the VCO oscillates based on the reproduction burst signal BUR8T.
12 as the write clock signal WCK to capture the phase information of the reproduced video signal VDIN, and the frequency of the write clock signal WCK is varied based on the frequency fluctuation signal 819 to generate the reproduced video signal. Since it is configured to take in VDIN frequency fluctuation information, there is no need for a complicated phase synchronization circuit to forcibly synchronize the phase after taking in the frequency fluctuation information as in the past, simplifying the circuit configuration. be able to.

Further, since the path for detecting the frequency is common for the write clock signal and the frequency fluctuation signal, there is no error due to a difference in the path, and the difference in frequency can be detected with high precision.

FIG. 3 shows a second embodiment of the invention.

It has a configuration to prevent a situation in which the difference in the number of frequencies 'tHL is not accurately detected due to the difference K in duty ratio between the write clock signal WCK and the frequency fluctuation signal 819.

For example, in FIG. 4, if the duty ratio of the write clock signal WCK is 5T [%] and the duty ratio of the frequency fluctuation signal S19 is 30C%, as shown in FIG. Even if the frequencies of WCK and S19 are the same, the fundamental wave component 'wax'' after Fourier transform is 819
The amplitude of the write clock signal WCK is greater than the amplitude Aw of the frequency fluctuation signal 819. Become bigger.

As a result, when the write clock signal WCK and the frequency fluctuation signal S19 having different duty ratios are passed through the frequency discrimination circuit 14 having the configuration shown in FIG. They will have different amplitudes even in the case of Therefore, the oscillation of the start-stop type VCO 12 is erroneously controlled.

Therefore, in the embodiment shown in FIG.
A 172 frequency dividing circuit 5 is inserted between the frequency discriminating circuit 14 and the frequency discriminating circuit 14, so that the duty ratio of the signal 825 given to the frequency discriminating circuit 14 is always set to (4).

For example, the signal 5258 obtained by frequency-dividing the write clock signal WCK of the duty ratio blade [H] shown in the 4th National Report is shown in Fig. 4 (
6) As shown in K, the signal becomes the duty ratio blade [J],
In addition, the signal 5251 obtained by frequency-dividing the frequency fluctuation signal S19 of the duty ratio blade [H] shown in FIG.
The signal becomes the duty ratio (capital) [chi] as shown in .

According to the embodiment shown in FIG. 3, even if the frequency fluctuation signal S19 and the write clock signal WCK have different duty ratios, it is possible to accurately detect the difference in frequency between the two signals 819 and WCK. The built-in clock signal WCK can be made to follow the frequency fluctuations of the reproduced video signal VDIN.

In the above embodiment, the frequency discrimination circuit 14 was constructed using a low-pass filter, but it is also possible to use a band-pass filter, a band-pass filter, or a low-pass filter. , S19. It is acceptable as long as the frequency of the fundamental wave component of these branch signals is in the cutoff frequency region of the filter. Obtainable.

Further, in the above-described embodiment, the low-pass filter 14 and the beak horizontal branch circuit 15 are used in common for the frequency fluctuation signal 819 and the write clock signal WCK, but they may be used separately, and in this case, Switching configuration can be omitted.

H Effects of the Invention As described above, according to the present invention, the oscillation output of vCO generated based on the reproduced burst signal is output as a write clock signal, and the time axis fluctuation of the reproduced video signal is controlled based on the reproduced horizontal concave signal. Fluctuations in the number of frequencies ffIL following 100 form a signal, and vCO is controlled according to the difference in frequency between this frequency fluctuation signal and the write clock 100. Therefore, the phase fluctuations and frequency fluctuations of the reproduced video signal are controlled. A simple write clock generation circuit of Jim's time base correction device that can generate a write clock signal having an accurate signal can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a route diagram showing the frequency characteristics of the cycle tHL number discrimination circuit 14 shown in FIG. 1, and FIG. 3 is a block diagram showing one embodiment of the present invention. A block diagram showing an example, FIG. 4 is a route diagram for explaining the function of the frequency dividing circuit in FIG. 3, and FIG. 5 is a block diagram showing the overall configuration of the time axis correction device. Including clock generation circuit, 5.
...Memory, 11...Start pulse generation circuit, 12
... Voltage controlled oscillator, 14... Frequency discrimination circuit,
15...Peak detection circuit, 17° distribution...Hold circuit, 19...PLL circuit, 2]...Differential voltage detection circuit, B U RS'l'...Reproduction burst signal, H...
- Reproduction horizontal open $tJ+ signal, WCK... write clock signal.

Claims (1)

[Scope of Claims] A write clock generation circuit of a time axis correction device that generates a write clock signal for a time axis correction memory based on a reproduced burst signal and a reproduced horizontal synchronization signal separated from a reproduced video signal, comprising: A PLL circuit that forms a frequency fluctuation signal whose frequency fluctuates according to the time axis fluctuation of the horizontal synchronization signal, and a voltage-controlled oscillator that can control the start and stop of oscillation and sends the oscillation output as the write clock signal. , a start pulse generation circuit that generates a start pulse signal that stops and restarts the oscillation of the voltage controlled oscillator based on the reproduction burst signal; a frequency discrimination circuit that sends out a changing output signal; a peak detection circuit that obtains a DC voltage signal according to the output signal of the frequency discrimination circuit; and a peak detection circuit that holds the DC voltage signal that corresponds to the frequency of the write clock signal. between the first hold circuit, a second hold circuit that holds the DC voltage signal according to the frequency of the frequency fluctuation signal, and the DC voltage signals held in the first hold circuit and the second hold circuit, respectively. A write clock generation circuit equipped with time axis correction, comprising: a differential voltage detection circuit that detects a differential voltage between the two and varies the oscillation frequency of the voltage controlled oscillator based on the differential voltage.