JPS61219235A - Unique word detecting circuit - Google Patents

Abstract

PURPOSE:To make the entire circuit configuration of a unique word detecting circuit simple and small in size, by providing a subtractor which subtracts the output of a counter-adder circuit from the bit number of unique words between the counter-adder circuit and a comparator. CONSTITUTION:A received data string 1 is impressed upon a shift register 3 by an n-bit amount from a certain bit and detection of the data is started. The data is compared with the parallel output of the register 3 at a dissidence detecting circuit 5. The output number of the circuit 5 is counted and added by means of a counter- adder circuit 7 and the count value is compared with the value of a floating value setting circuit 9 at a comparator 11. When the count value is smaller than the floating value, the data is judged as a proper unique word and an output 'UW' is obtained. Moreover, the output value of the counter circuit 7 is subtracted from the set value of a unique word bit value setting circuit 15 by means of a subtractor 16. The calculated results of the subtractor 16 are a value indicating that how many pieces of bits out of the bit number of the unique word coincide properly and, when the value is larger than the value (unique word bit number - floating value) of a floating value setting circuit 10, it can be judged that the fetched pulse string of the n-bit shift register 3 is an inverted unique word.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a circuit configuration that counts and adds the number of bits detected as mismatching between the unique word pattern and the received data when detecting a unique word inserted in received data. This is a unique word detection circuit that can be made compact.

[Industrial Field of Application] The present invention relates to a circuit that can efficiently detect a unique word with a long number of bits from a burst data string on a small scale, such as in a time division multiple access (TDMA) communication system.

[Prior art] Unique word is, for example, r 100100010011
...11'' is predetermined as a 24-bit pattern. For example, in the satellite communication TDMA system, it is necessary to reliably detect this unique word from data sent in bursts and to establish synchronization by finding the position of the data. FIG. 2 is a block diagram showing the configuration of a conventional unique word detection circuit. In FIG. 2, 1 is a received data string, 2 is a unique word pattern setting circuit, 3 is an n-bit shift register (n is the number of bits of a unique word), 4 is a polarity inversion circuit, and 5.6
7.8 is a counting/adding circuit that counts and adds the number of bit string mismatches detected, 9.10 is a margin value setting circuit, and 11.12 is a comparison circuit. 13 and 14 indicate unique word detected signal output terminals. The n bits of the received data string 1 are applied to the n-bit shift register 3, and detection is started. The parallel output of the register 3 is compared with the output of the unique word pattern generator 2 in a mismatch detection circuit 5. Further, the output of the unique word pattern setting circuit 2 is inverted by the phase inversion circuit 4, and is similarly compared with the output of the register 3 by the mismatch detection circuit 8. For example, if the received data is ro for the unique word pattern described above,
loloQl・-・-・-・11'',
Since the first two bits do not match, the counting/addition circuit 7
outputs "2" as the number of mismatched bits. When "3" is set in the margin value setting circuit 9, the comparison in the comparator 11 shows that the number of mismatches is small. Therefore, the comparator 11 outputs a detection pulse UW13 that can be used as a unique word. That is, since the range taken into the shift register 3 is a unique word sequence (or a unique word inverted sequence), the time standard probability of the burst data can be determined.

[Problems to be Solved by the Invention] In FIG. 2, two counting/adding circuits 7 and 8 are used, but this circuit becomes large-scale as the number of bits of the unique word pattern increases. For example, when the unique word is 24 bits, the counting/adding circuit is constructed by combining 8 1-bit full adders, 4 2-bit adders, 4 3-bit adders, 21 4-bit adders, and 1nIi. do. Then, the results detected by the eight full adders are added in the next adder and then further added in the next adder.
This is because the configuration is such that the number of discrepancies is obtained by repeating the process several times.

Therefore, an object of the present invention is to provide a unique word detection circuit with a simple configuration.

[Means for solving the problem] A subtracter that has a circuit that counts and adds the number of mismatches between the output of the unique word pattern setting circuit and the input data pit string, and that subtracts the number of stitches and the number of outputs of the addition circuit. is provided, and its output value is compared with a margin value in a margin value setting circuit. The output of the comparator is taken out as an inverted unique word detection signal.

[Operation] The value obtained by subtracting the output of the mismatch detection circuit from the number of unique word bits is related to the unique word margin value, and an inverted unique word can be detected. There is only one counting/adding circuit and one subtracter, which simplifies the overall circuit configuration.

[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In Figure 1, 1 is a received data string, 2 is a unique word pattern setting circuit, 3 is an n-bit shift register, 5 is a discrepancy detection circuit, such as an exclusive OR circuit, and 7 is a counting/adding circuit, which is a mismatch in focus rows. A circuit that counts and adds numbers, 9.10 is a margin value setting circuit, 11.12 is a comparator,
Reference numerals 13 and 14 denote terminals for taking out a unique word detected signal, 15 a unique word bit value setting circuit, and 16 a subtracter for subtracting the output value of the counting/adding circuit 7 from the number of unique word bits.

In FIG. 1, n bits of received data string 1 are applied to the shift register 3 to start detection.

The parallel output of the register 3 and the mismatch detection circuit 5 are compared. Counting and adding circuit 7 for the number of outputs of the mismatch detection circuit 5
Count and add at . The count value is compared with the value of the margin value setting circuit 9 in the comparator 11. If the value is smaller, it is determined that it is a correct unique word and outputs rUWJ.
get. Further, the output value of the counting circuit 7 is subtracted from the set value of the unique word bit value setting circuit 15 in a subtracter 16 . The calculation result of the subtracter 16 is a value indicating how many bits out of the number of unique word bits have correctly matched, and that value is the value of the margin setting circuit IO (number of unique word bits - margin value). If this is the case, it can be determined that the pulse train taken in by the n-bit shift register is an inverted unique word, which means that UW is obtained as the terminal of the comparator 12.

In FIG. 1, only one counting/adding circuit 7 is used,
As for the subtracter, it is sufficient to use only one 4-bit adder.

[Effects of the Invention] Therefore, compared to the conventional circuit, the present invention uses a subtracter and uses one less counting/adding circuit.
The overall circuit configuration is simple and compact. This has the effect of making it suitable for large scale integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a block diagram showing the configuration of a conventional circuit. l - Received data string 2 - Unique word pattern setting circuit 3 - Shift register 4 - Phase inversion circuit 5.6 - Mismatch detection circuit 7.8 - Counting/adding circuit 9.10 - Margin Value setting circuit 11.12--Comparator 13.14--Unique word detected signal extraction terminal 15-Unique word bit value setting circuit 16--Subtractor

Claims (1)

[Claims] A detection circuit (5) that detects a mismatch between a regular unique word pattern and received data having the same number of bits, and a circuit (7) and (8) that counts and adds the number of mismatches in a predetermined number of bits. , a comparator (11
) (12), between the counting/adding circuit (7) and the comparator (12),
A unique word detection circuit characterized in that a subtracter (16) is inserted for subtracting the output of a counting/adding circuit from the number of bits of a unique word.