JPS6121654A - Communication controller - Google Patents

Abstract

PURPOSE:To cope with high speed operation of a line by providing a processor section applying processing of a level over a packet level, link level control section, packet level header decoding section and a storage section storing temporarily a packet below a prescribed level to reduce the overrun probability at the reception side. CONSTITUTION:A microcontroller 6 of a link level control section 2a reads a channel command on a main memory 4 of a processor section 1 via a memory access control section 5 and transmits/receives a frame according to a link level protocol. Then the microcontroller 6 transmits a reception information frame to a packet level header decoding section 8. The decoding section 8 uses a pattern of a packet header section to judge whether or not the packet included information over a prescribed level. The packet including over the prescribed level is transmitted to a main memory 4 with high priority to the main memory 4 via the memory access control section 5, while the packet not including the information over the prescribed level is transmitted to the main memory 4 with low priority.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a communication control device that controls data transmission between a network and a terminal in a packet switching system.

[Prior art]

As shown in Figure 1, the conventional communication control equipment in this building consists of a processor unit 1 that performs processing at the packet level and higher levels, and a link level control unit 2 that performs link level processing. The section 1 is composed of a processor unit 6 and a main memory 4, and the link level control section 2 is composed of a memory access control section 5, a microcontroller 6, and a line control section 7.

To explain the operation of the above configuration, first, the processor section 1 controls the link level control section 2 by setting a channel command in the main memory 4 and having the link level control section 2 read the channel command from the main memory 4. It will be done. Transmission and reception data between the link level control unit 2 and the processor unit 1 is transferred by the link level control unit 2.
is performed by accessing the main memory 4 in accordance with the channel command. Since the above is already known, a more detailed explanation will be omitted.

The link level control unit 2 realizes these functions (secondly, it is necessary to read and interpret channel commands, calculate sending and receiving addresses, monitor command completion, etc., but these are realized by the software ζ2 of the microcontroller 6. Note that the memory access control section 5 is a circuit for writing/reading into/from the main memory 4 in accordance with memory access instructions from the microcontroller 6.

Due to this configuration, the processing capacity of the microcontroller 6 limits the maximum processing capacity of the link level control section 2. Especially (when short frames are continuously sent and received on the second line side, and when the channel command instructs to connect short buffers with chain data, the microcontroller 6 transmits and receives data to and from the line control unit 7. transmission and reception, link level protocol control, writing/continuation of transmission/reception data to main memory, and reading of channel commands from main memory 4 must be executed to avoid overruns and underruns, and under the worst conditions. The line speed was limited to about 64-Kbps.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication control device with improved processing capacity in view of the drawbacks C of the conventional example described above.

[Structure of the invention]

In order to achieve the above objects, the present invention provides (1) a communication control device that controls data transmission between a terminal of a packet switching system and a network (2) a processor section that performs processing at a level higher than the packet level, and a link a link level control section having a microcontroller that performs level processing; a packet level header interpretation section that determines whether a packet contains information at a predetermined level or higher; and a storage section that temporarily stores packets below the predetermined level. It is characterized by including.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of a communication control device showing an embodiment of the present invention, and the same components as in FIG. 1 are given the same reference numbers.

This device includes a processor section 1 and a link level control section 2.
a, a memory access control section 5, a header interpretation section 8, and a header temporary storage section 9.The processor 1 is composed of a processor unit 6 and a main memory 4, and a link level control section. 2a is composed of a microcontroller 6 and a line control section 7.

In the above configuration (2), the microcontroller 6 of the link level control unit 2a reads the channel command on the main memory 4 of the processor unit 1 via the memory access control unit 5, and transmits and receives frames according to the link level protocol. The function of the line control section 7 is the same as that in FIG.

The microcontroller 6 then sends the received information frame to the ladder interpreter 8 at the packet level.

The packet-level ladder interpreter 8 determines whether the packet contains information at a predetermined level or higher based on the pattern of a part of the packet header. Packets containing information above the predetermined level are sent to the main memory 4 with a high priority via the memory access control unit 5, while packets that do not contain information above the predetermined level are sent to the main memory 4 with a low priority. Sent. The header temporary storage section 9 temporarily stores the packet until it is sent to the main memory 4.
It is.

As described above, even if short packets that do not contain information of a predetermined level or higher arrive in succession, the possibility of overrun is reduced, making it possible to cope with higher speed lines.

〔Effect of the invention〕

As explained above, the present invention has the effects of reducing the overrun probability on the receiving side and increasing the speed of the line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional communication control device, and FIG. 2 is a block diagram of an embodiment of the present invention. 1... Processor section 2a... Link level control section 6... Microcontroller 8... Ladder interpretation section to packet level 9... Header temporary storage section

Claims (1)

[Scope of claims] A communication control device that controls data transmission between a terminal and a network in a packet switching system, comprising: a processor unit that performs processing at a level higher than the packet level; and a microcontroller that performs link level processing. A communication control device comprising: a level control unit; a packet level header interpretation unit that determines whether a packet contains information at a predetermined level or higher; and a storage unit that temporarily stores packets below the predetermined level. .