JPS61216067A - Address coding system - Google Patents

Abstract

PURPOSE:To control easily a large-scaled communications line without limiting the number of CPU's controllable communications lines by an address coding system by installing an I/O line indicating means and an address discriminating means in an I/O controller. CONSTITUTION:The register 7b of a multiplexer 7 in the I/O controller (communications controlling unit) CCU 5(1)-5(m) is composed of a control register 71 and a register 72. The former stores a control word transmitted from a central processing part, while the latter is divided into storage areas 0-n corresponding to respective communications lines L0-Ln. And each area is divided into a transmitting part S and a receiving part R. Thus contents in the register 71 can be referred, and the discrimination and specification of the communication line can be made. The address discrimination is executed through the register 72. Thus the communications circuit to be controlled is selected, whereby plural communications lines can be easily controlled up to the upper limit of CPU's processing ability without considering the prescribed limit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an addressing method that can increase the number of input/output lines that can be controlled by a central processing unit with a simple circuit configuration.

As the usage of information processing systems becomes more sophisticated and complex, information processing system networks are being built that allow data to be sent and centrally managed through communication lines, and that centrally managed data can be shared from anywhere via communication lines. It has become.

Furthermore, as these network configurations become more complex, communication control systems suitable for quickly switching and processing these complex line networks have been developed and put into practical use.

In such a communication control system, a general configuration is such that a communication line through which data is input/output is connected to a communication control device, and the central processing unit of the communication control system controls the communication line to which addresses are assigned through the communication control device. It becomes.

However, as line networks become more complex and expanded, it becomes desirable to make the control method of the central processing unit more efficient and to increase the number of communication lines that can be controlled by one central processing unit.

[Prior art and problems to be solved by the invention] Figure 4 is a schematic diagram of the configuration of a communication control system, Figure 5 is a block diagram of a conventional communication control device, and Figure 6 is a diagram of a conventional address configuration. show.

A central processing system 1 (hereinafter referred to as a control device 1) includes main storage units (hereinafter referred to as storage units) 2a and 2b that store various control programs and input/output data.

Central processing unit (hereinafter referred to as C) that manages and controls the communication control system
C) 3a, 3b.

In response to commands from the CCs 3a and 3b, data and control words from the CCs 3a and 3b are transferred to the corresponding lower devices via the common bus a.

Channel control units (hereinafter referred to as CHC) 4a and 4b communicate and control through the channel control unit 4a and 4b.

It consists of

Communication control units (hereinafter referred to as CCU) 5(1) to 5(1) are connected to the common buses a and b, and the CCU 5
Communication lines LO=Ln are appropriately distributed and connected to (1) to 5(1). In addition, CCU3(1) to CCU5(1) are a multiplexing circuit 7 consisting of a multiplexing section 7a and a register 7b (in FIG. 5(B), S indicates a transmitting area and R indicates a receiving area, respectively). , line termination units 8(1) to 8 that adjust the respective impedances in accordance with the communication line LO=Ln.
(n).

The multiplexing unit 7a has a function of multiplexing and transmitting data transmitted through the communication line LO=Ln and restoring the multiplexed data inputted through the communication lines LO to Ln. Further, the register 7b is the storage area 0 corresponding to the communication line LO=Ln.
-N (each consisting of 8 words), and each storage area 0-N is divided into a transmission control word storage part and an input control word storage part.

Here, when controlling data input/output to communication lines LO to Ln, CC3a (or CC3b, in this example, C
The address shown in FIG. 6 is first sent to the common bus a. The address to be sent consists of 16 bits, the Oth bit,
The 12th to 15th bits are not normally used, so they are always “O”.
” is set.

Next, the C portion of the 1st to 3rd bits is for specifying the register 7b, and the d portion of the 4th bit is for each storage area 0-
The part that specifies transmission or reception of N, the e part of the 5th to 11th bits, is for specifying an address corresponding to the communication line LO to Ln, and the e' part of the 5th to 8th bit is used to specify the address corresponding to the communication line LO to Ln. The e# portion of the 9th to 11th bits is used for specifying the Ln number and for specifying CCU5(1) to CCU5(m). Note that the e portion will be referred to as the I10 address portion hereinafter.

By such address designation, a predetermined communication line, for example, communication line LO, is determined, and data transmission is instructed by designation at the fourth bit (d portion). However, as mentioned above, the designation of the communication line LO is the I10 address part e
In the conventional addressing method in which the upper bits are used to specify the communication line LO and the lower bits are used to specify the communication line LO, the number of communication lines LO to Ln that can be connected to the system is limited.

That is, in this system shown in FIG. 4, only a maximum of 128 lines can be connected. If the number of lines is to be further increased, it is necessary to add CCs and make the system configuration a multi-system. Therefore, there is a problem in that the number of system components increases accordingly, and furthermore, the control thereof becomes more complicated.

[Means for solving problems]

The present invention aims to realize a new addressing method that solves the above-mentioned problems. An input/output line specifying means for specifying a line and an address identifying means for identifying an address sent from a central processing unit are provided, and the central processing unit allocates and controls addresses to each input/output control device, and controls the input/output control unit. The control device is solved by the addressing method according to the present invention in which the input/output line designating means and the address identifying means autonomously designate and control the input/output line.

[Effect]

That is, an I10 address specified by the central processing unit is assigned to each input/output control device (communication control device), and communication line identification is indirectly performed by a control word sent from the central processing unit to the input/output control device (communication control device). The input/output control device (communication control device) refers to the control word and performs the operation autonomously. By selecting the communication lines to be controlled in this manner, it becomes possible to connect and control a large number of communication lines to the maximum processing capacity of the central processing unit without being aware of a predetermined limit frame.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 and 2.

FIG. 1 is a block diagram showing an embodiment of a multiplexing device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a control register according to the present invention, and FIG. 3 is an embodiment according to the present invention. The address configuration diagrams of the common bus are shown respectively. Note that the same reference numerals indicate the same objects throughout the figures.

In the common bus address (consisting of 16 bits) of this embodiment shown in FIG. 3, the r10 address part e is from the 4th bit to the 1st
All 8 bits up to the 1st bit are allocated, and 8
It is used to specify the entire focus of CCU 3 (1) to 5 (m).

The registers 7b provided in the multiplexing device 7 in the CCUs 5(1) to 5(m) are connected to a register 72 for storing input/output data and a control register 71 for storing control words sent from the CCs 3a and 3b. As shown in FIG. 2, the control register 71 consists of 8 words, and each word consists of 16 bits.

The first word CTLO of the control register 71 is a communication line number register (including the distinction between S for transmission and R for reception), word CTLI is a command address, word CTL2 is a channel control register, device status register, etc.

The register 72 is divided into storage areas 0-N corresponding to each communication line LO-Ln, and each storage area θ-N
It is divided into an S part for transmission and an R part for reception.

Therefore, in CC3a and 3b, I10 address part e
Specify CCU5 (1) to 5 (+w) to be controlled with
The CCUs 5(1) to 5(m) continue to control the communication line L by referring to the contents of the control register 71 storing the control word sent through the connected communication line LO=Ln.
Specify and control O to Ln.

That is, for example, if the word CTLO contains an instruction to transmit data from the communication line LO, the data in the transmission portion S of the storage area O of the register 72 is read, multiplexed, and sent from the communication line LO. By adopting such an addressing method, it becomes possible to easily control a large-capacity system configuration using simple components. For example, in the case of the system of this embodiment, up to 256 communication control devices can be controlled.

〔Effect of the invention〕

According to the present invention as described above, the number of communication lines that can be controlled by the central processing unit is not limited by the addressing method, and large-scale communication lines can be easily controlled using a simple method. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a multiplexing device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a control register according to the present invention, and FIG. 3 is an embodiment according to the present invention. FIG. 4 is a schematic diagram of the configuration of a communication control system, FIG. 5 is a block diagram of a conventional communication control device, and FIG. 6 is a conventional address configuration diagram. In the figure, 1 is a control device, 2a and 2b are questions, 7a is a multiplexing unit, 7b and 72 are registers, and 8(1) to 8(n
) indicates a line termination section, 71 indicates a control register, and 71 indicates a control register. 1st zucha 2 raging grass 3 Japanese grass 4 kuchicha 5th (A) bower 5 1il (5) grass 6 danbu (=' Q '' (shirisukaj side flavor) neyrrmshiif)

Claims (1)

[Claims] In a system consisting of an input/output control device that controls a plurality of input/output lines according to instructions from a central processing unit, and a channel that is connected by a common bus and sends instructions from the central processing unit to the corresponding input/output control device. , providing in the input/output control device an input/output line designation means for specifying the input/output line connected to the input/output control device, and an address identification means for identifying the address sent from the central processing unit, The central processing unit assigns and controls addresses to each of the input/output control devices, and the input/output control device autonomously specifies and controls the input/output lines by the input/output line designation means and the address identification means. An address assignment method characterized by: