JPS61210393A - Split display control system for display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention has a plurality of screen compatible memories such as a refresh memory and an image memory, and displays image data read from different storage areas of these screen compatible memories in one screen. The present invention relates to a split display method in a display device that displays split images on a display screen of a display in combination with the above.

[Conventional technology]

As a display device of this kind capable of displaying a divided display, one having a configuration shown in FIG. 7 is conventionally known.

This device connects a processing device 1 such as a processor to a plurality of refresh memories 3a to 3 via a processor bus 2'.
d, and each refresh memory 3
The image data stored in 8 to 3d is read out via the image data bus 5 in synchronization with the scanning of the display 6, converted into a video signal, and supplied to the display 6 such as a CRT display for display.

As shown in FIG. 8, each of the refresh memories 3a to 3d includes a memory address generator 7, a memory array 8 accessed thereby, and an X address control register 9. X address counter 10, Y address control register 11. It consists of a Y address counter 12, an AND circuit 13 to which the outputs of the counters 10 and 12 are supplied, and a gate circuit 14 to which the outputs thereof are supplied.

Using the display device having the above configuration, the display screen 6 of the display 6 is displayed as shown in FIG.
Conventionally, as a split display control method in which a is divided into four divided display areas D1 to D4 and different displays are displayed in each divided display area, first, an X address register 9 is sent from the processing device 1.
The X-direction output area of the image data is set in , and then the Y-direction output area of the image data is set in the Y address register 11 . In this state, the memory address generator 7 sequentially outputs corresponding addresses to the memory array 8 in accordance with the scanning of the display 6, and the memory array 8 outputs the image data stored at the addresses.

At this time, whether or not the image data read from the memory array 8 is output to the image data bus 5 is controlled by the values of the X address counter 10 and the Y address counter 12. Normally, the X address counter 10 counts each time one pixel is output in the X direction, and the initial value is loaded by the X address control register 9 before one scan in the X direction is started. On the other hand, the Y address counter 12
is counted each time one scan in the X direction is completed, and the initial value is loaded by the Y address control register 11 before the scan of one screen starts.

In this way, the image data corresponding to the divided display areas D1 to D4 is read from each of the refresh memories 3a to 3d, and is supplied to the video signal generator 4 via the image data bus 5. A video signal is generated by a signal generator 4, and a divided display is performed on a display screen 6a of a display 6.

[Problem that the invention seeks to solve]

However, in the conventional split display control method described above, the processing device 1 sets numerical data representing the split display area in the X address control register 9 and Y address control register 11 of each refresh memory 3a to 3d, respectively. When changing the split display area of the screen, the processing device 1
Each refresh memory 38 to 3 is updated according to the changed value.
New numerical data must be set in the X address control register 9 and Y address control register 11 of d, and the amount of access to the refresh memories 3a to 3d of the processing device increases, and the values set in each counter also change. Because of the difference, the processing device 1 has to manage the processing device 1, which increases the burden on the processing device 1 and reduces the processing speed.

Therefore, the present invention has been made by focusing on the problems of the conventional example, and simplifies split display control by using a video signal generator to set the split display area where the screen is split. It is an object of the present invention to provide a divided display control method in a display device that can change the output area of display contents of each memory device based on the divided display area.

[Means for solving problems]

In order to achieve the above object, the present invention includes a plurality of screen compatible memories such as refresh memory and image memory;
A display device comprising a video signal generation device that generates a video signal according to image data from the screen compatible memory, and a display to which the video signal from the video signal generation device is supplied, the video signal generation device comprising: , has a split display area setting unit that sets a split display area of the screen, and outputs a split display control signal based on setting data stored in the split display area setting unit, and the memory corresponding to each screen corresponds to the split display control signal. image data stored in a memory corresponding to each screen based on the output control data stored in the display control unit and a split display control signal from the video signal generator; It is characterized by controlling the readout of the image data and performing split screen display.

[Effect]

The present invention includes a plurality of screen compatible memories such as a refresh memory and an image memory, a video signal generating device that generates a video signal according to image data from the screen compatible memory, and a video signal generating device that generates a video signal according to image data from the screen compatible memory. In a display device equipped with a supplied display, a display area setting unit such as a register for setting a divided display area is provided in the video signal generating device, and the display area setting unit is configured to divide the display area based on setting data stored in the display area setting unit. A display control signal is formed and supplied to each screen corresponding memory. Each screen compatible memory has a display control section such as a register that stores output control data corresponding to the split display control signal, and outputs image data when the output control data matches the split display control signal. do. Therefore, the setting of the divided display area is performed by the display area setting section of the video signal generator, and the output control of the image data of each refresh memory is
By referring to the split display control signal from the video generation device using a display control section built into these devices, it becomes possible to independently control the setting of the split display area and the reading of image data from the screen corresponding memory.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a specific configuration of the refresh memory.

In FIG. 1, 1 is a processing device such as a processor, 2 is a processor bus, 3a to 3d are refresh memories as screen-compatible memories, 4 is a video signal generator, 5 is an image data bus, and 6 is a display.

The video signal generator 4 generates each refresh memo 'J3a.
When the image data read from 3d is supplied via the image data bus 5, a corresponding video signal is generated and output to the display 6 for display, and the divided display areas D1 to D4 Split display area setting register 15.16.17 as a split display area setting unit that sets
and 18, and these divided display area setting registers 15
When desired area setting numerical data is written from the processing device 1 to 18, the divided display signal DS (DS , -DS4'') and supply these to each refresh memory 3a to 3d.

On the other hand, each of the refresh memories 3a to 3d includes a memory address generator 7, a memory array 8, and a display controller that stores output control data corresponding to the divided display control signal DS from the processing device 1, as shown in FIG. It consists of an image data output control register 23 as a section, and a comparator 24 that compares the output control data stored in the image data output control register 23 and the split display control signal DS from the video signal generation device 4, The output control data stored in the image data output control register 23 from the comparator 24 and the split display control signal DSI-D
When S and S match, for example, an output control signal having a logical value of "l" is output, whereby the image data read out from the memory array 8 is transferred to the video signal via the gate circuit 14 and the image data bus 5. It is output to the ordering device 4.

Next, the operation of this embodiment will be explained.

Now, as shown in FIG. 3 from the processing device l, the display screen 6a
When dividing display area setting data for dividing into four parts is written to the divided display area setting registers 15 to 18 of the video signal generating device 4, the signal lines 19 to 22 are set as shown in FIG. 4 in the display start state. A split display control signal DS+""DS4 is output. That is, the split display control signal DS+ has a logical value of "1" only in the section corresponding to the split display area in one period of the horizontal synchronization signal of the display 6, and the split display control signal DS2 has a logical value of "1" only in the section corresponding to the split display area within one period of the horizontal synchronization signal of the display 6. Only the section corresponding to the divided display area D2 in one cycle of is set to logical value "1", and the divided display control signal DS is set to the divided display area D++D and the divided display area Dz from the time when the display device 2 starts scanning. , the logical value is "1" only until the boundary position of Da is scanned, and the split display control signal Ds4 is the logical value "1" only until the lower position of the screen is scanned from the boundary position. Become. Therefore, the video signal generator 4
From then on, the scanning line of the display 6 is divided into the divided display area D1.
When scanning the split display area D2, the split display control signal DS of rl 010J is scanning the split display area D2, and the split display control signal DS of rl OOIJ is scanning the split display area D2. , ro 110J
When the divided display control signal DS of "0101" is scanning the divided display area D4, the divided display control signal DS of "0101"
are output respectively.

Further, the processing device 1 inputs "1010" to the image data output control register 23 of the refresh memory 3a, for example, and inputs "1010" to the image data output control register 23 of the refresh memory 3b.
3, rl 001J to the image data output control register 23 of the refresh memory 3C, ro 110J to the image data output control register 23 of the refresh memory 3d.
"0101" is written to each as output control data.

In this state, when the display 6 starts displaying,
When the scanning line is scanning the upper part of the display screen 6a and also scanning the divided display area, the divided display control signal DS becomes rl 010J, as shown in FIG. Therefore, since it matches the display control data stored in the image data output control register 23 of the refresh memory 3a, a match signal is output from the comparator 24.
This opens the gate circuit 14, and the memory address generator trough of the memory array 8 causes the display 6 to open.
The image data stored at the address generated in response to the scanning is supplied to the video signal generator 4 via the image data bus 5, and the video signal generator 4 generates a corresponding video signal to be displayed. 6 display screen 6
The image data stored in the memory array 8 of the refresh memory 3a is displayed in the divided display area above a.

Similarly, when the scanning line of the display 6 is in a state where it scans the divided display area D3, in this state, the divided display control signal DS becomes ro 110J, so that it is stored in the image data output control register 23 of the refresh memory 3C. The image data is read out from the memory array 8 of the refresh memory 3C, and is supplied to the video signal generation circuit 4 via the gate circuit 14 and the image data bus 5 to be output on the display 6. Image data stored in the memory array 8 of the refresh memory 3c is displayed in the divided display area on the display screen 6a.

Furthermore, the scanning lines of the display 6 are divided into the divided display areas Di(
), the image data stored in the memory array 8 of the refresh memory 3b (or 3d) is displayed on the display screen 6a of the display 6.
It is displayed in the upper divided display area Dz (or).

As described above, as shown in FIG. 5, each divided display area D+, Di, D! of the display 6 is displayed. The image data stored in the refresh memories 3a, 3c, 3b, and 3d are displayed in sections and D4, respectively.

From this display state, when the processing device 1 replaces, for example, the control data in the image data output control register 23 of the refresh memory 3b and the control data in the image data output control register 23 of the refresh memory 3c, the sixth
As shown in the figure, the image data stored in the refresh memory 3b is in the divided display area D, and the image data stored in the refresh memory 3c is in the divided display area D.
2 will be displayed respectively. Therefore, the processing device 1 determines in which of the divided display areas D1 to D4 on the display screen 6a of the display 6 the image data stored in each refresh memory 38 to 3d is to be displayed. By selecting the control data to be written into the image data output control register 23, it can be changed arbitrarily.

Furthermore, in order to change the area of the divided display area DI"D4 on the display screen 6a of the display 6, the processing device l
writes the setting data specifying the width in the X direction to the divided display area setting register 15.16 of the video signal generator 4, and writes the setting data specifying the width in the
By writing setting data specifying the width in the direction and forming a predetermined split display control signal DS based on these setting data, it is possible to easily change the area of the split display areas D1 to D4.

In the above embodiment, a case has been described in which the display screen 6a of the display 6 is divided into four divided display areas to form ~D4, but the present invention is not limited to this, and the display screen 6a may be divided into two or more. In this case, the number of refresh memories corresponding to the number of divided display areas and the number of divided display area setting registers corresponding to the division mode of the divided display areas can be formed. All you have to do is set it up.

In addition, in the above embodiment, as the screen compatible memory,
Although the case where a refresh memory is applied has been described, the same effect as described above can be obtained even if an image memory is applied.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of screen compatible memories such as refresh memory and image memory,
A display device comprising a video signal generation device that generates a video signal according to image data from the screen compatible memory, and a display to which the video signal from the video signal generation device is supplied, the video signal generation device comprising: , has a split display area setting unit that sets a split display area of the screen, and outputs a split display control signal based on setting data stored in the split display area setting unit, and the memory corresponding to each screen corresponds to the split display control signal. image data stored in a memory corresponding to each screen based on the output control data stored in the display control unit and a split display control signal from the video signal generator; Since the split screen display is performed by controlling the readout of When setting the area, there is no need to set the split display area in each screen memory, and since the data stored in the display control register of each screen memory corresponds to the split display control signal, the corresponding display control register By changing the storage contents of the display area, it is possible to change the output area without changing the divided display area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a refresh memory, and FIG. 3 is an explanatory diagram showing the relationship between the display screen of the display device and the split display control signal. , FIG. 4 is a waveform diagram showing the waveform of the split display control signal, FIGS. 5 and 6 are explanatory diagrams for explaining the present invention in detail, FIG. 7 is a block diagram showing the conventional system, and FIG. FIG. 9 is a block diagram showing the configuration of the refresh memory, FIG. 9 is an explanatory diagram showing divided display areas, and FIG. 10 is an explanatory diagram for explaining the operation of the conventional example. In the figure, l is a processing device, 2 is a processor bus, 38 to 3d
4 is a refresh memory, 4 is a video signal generator, 5 is an image data bus, 6 is a display device, 7 is a memory address generator, 8 is a memory array, 15 to 18 are divided display area setting registers, 23 is a display control register, 24 is a comparator.

Claims (1)

[Claims] A plurality of screen compatible memories such as refresh memory and image memory, a video signal generating device that generates a video signal according to image data from the screen compatible memory, and a display to which the video signal from the video signal generating device is supplied. In the display device, the video signal generating device has a split display area setting unit that sets split display areas of the screen, outputs a split display control signal based on setting data stored in the split display area setting unit, and Each of the screen-compatible memories has a display control section that stores output control data corresponding to the split display control signal, and the output control data stored in the display control section and the split display control from the video signal generation device are stored in the display control section. 1. A split display control method for a display device, characterized in that a split screen display is performed by controlling readout of image data stored in a memory corresponding to each screen based on a signal.