JPS61208579A - Geometric converting coordinate producing circuit - Google Patents

Abstract

PURPOSE:To obtain a geometric converting coordinate generating circuit with a low power consumption and a small scale circuit construction by carrying out an accumulation of coefficients bk during a horizontal retrace line period and clearing '0' of an accumulating value of coefficients ak. CONSTITUTION:During a horizontal scanning period in a raster scanning system, a selector control signal is fed from input terminals 52, 58 in a timing of i to (i+1) to (i+2).... In a selector circuit 42, an output (a) of a latch circuit 40 is selected and in one selector circuit 48, an output (accumulating value) of a latch circuit with a clear is selected and they are fed to an adder 43 and thereafter, a latch control signal is fed from an input terminal 54. An added value which the adder 43 adds the two outputs is stored in the latch circuit 44 with the clear. The above-mentioned operations are repeatedly carried out by the coordinate i from '0' to 'Nx' (horizontal scanning period). Thereby, the output of the latch circuit with the clear 44 is renewed from (a1.i) to [a1.(i+1)] to [a1.(i+2)].

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a geometric transformation coordinate generation circuit, and in particular to a geometric transformation suitable for performing geometric transformation of a digital image obtained by a raster scan method with a small-scale circuit configuration, low power consumption, and high speed. This relates to a coordinate generation circuit. [Summary of the Invention] The present invention relates to a geometric transformation coordinate generation circuit. Pixel number 1! By taking advantage of the fact that l[x, yl change in a raster scan manner, the coefficients ak, bk of the transformation are accumulated in correspondence with X and y. Locus $% [al-x+bl ・y+c1 , a2・x+
b2 ・y+c2]. [Prior art] Conventionally, the coordinates of one pixel [x, yl are geometrically transformed and [al
-x+b1 y+c1, a2-x+b2 ly+c
The geometric transformation coordinate generation circuit that maps to the coordinates of 21 has a configuration as shown in FIG. In addition, in the same figure, "al
・x + b 1・y+clJ Since only the geometric transformation coordinate generation circuit is shown, another ri2・x +
In order to simultaneously convert the b 2 ·y + c 2 J section, two circuits shown in the figure are provided. That is, from the coordinates [x, yl to ral-x+b1・Y+
When geometrically transforming the cxJ section, first, transform coefficients al+b1 and C1 are sent to the latch circuits 1 and 3.5, respectively, and the coordinate value XwY of one pixel is sent to the latch circuits 2 and 3.5, respectively.
4, then multiplier 7 multiplies the outputs of latch circuits 1 and 2 to obtain "a" x, and one multiplier 6 multiplies the outputs of latch circuits 3 and 4 to obtain 11 b, y ``'', then adder 8 adds the outputs of multipliers 6 and 7 to generate "a-x+b・y", and adder 9 adds the outputs of adder 8 and latch circuit 5. On the other hand, when performing geometric transformation from locus 1!l [x, yl to ri2 x + b2 x y + C2'', the same method as above is used. Since this can be done with , the explanation will be omitted. [Problems to be Solved by the Invention] In this conventional geometric transformation coordinate generation circuit, each time the pixel coordinate values X and y change, they are latched in the latch circuit 2.4, and then the multipliers 6, 7, . Operate adder 8.9,
Since new coordinates are generated after geometrical transformation, there are certain limits to the ability to reduce the size of the circuit configuration and reduce power consumption. The present invention was devised in view of these points.
When performing geometric transformation on digital images. It is an object of the present invention to provide a geometric transformation coordinate generation circuit that can be realized with a small-scale circuit configuration and low power consumption without using special circuit components. [Means for Solving the Problems] FIG. 1 is a block diagram of a geometric transformation coordinate generation circuit of the present invention, in which the first storage circuit for storing transformation coefficients ak and bk is a latch circuit 40.゜41, coordinate of transformation X
or the above ak or bk that applies when y increases
The circuit that accumulates is the selector circuit 42, 48 and the adder 43.
, stores the accumulation results corresponding to the coordinates X and y from the accumulation circuit. When the coordinate $1x or y is initialized to “0”, the value of the accumulated result stored above is set to 110 II or “ck”.
The circuits that are initialized are the latch circuit 44 with clear, the latch circuits 45 and 46, and the adder 49. [Function] During the horizontal scanning period in the raster scan method, the coefficient a
Continue the accumulation of k, and in the horizontal retrace period, accumulate the coefficient bk and a
By performing II OI + clearing of the accumulated value of k, the addition of the two accumulated values becomes "al・X+bt・y+c
I will be equal to the J part. Furthermore, since the latch, selection, and clear operations are performed in synchronization with the timing of the raster scan method, the digital image is geometrically transformed by the configuration shown in FIG. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a geometric transformation coordinate generation circuit according to the present invention. Note that this figure shows a coordinate generation circuit that performs the geometrical transformation of only the ra1° In order to perform simultaneous conversion, two circuits shown in the figure are provided. In FIG. 1, 40, 41, 45.46 are latch circuits that store variables, etc. with latch control signals, 42.47.4
8 is a selector circuit that selects one of the two signals using a selector control signal, 43.49 is an adder that adds the two signals output by the selector circuit, and 44 is a device that erases the memory contents stored using a latch control signal using a clear control signal. 50.51.54-56 are input terminals for latch control signals, 52.57.58 are input terminals for selector control signals, and 53 are input terminals for clear control signals. Convert/pixel coordinates

[x, y] follows the raster scan method, as shown in Figure 3, [0, 01...-r
i, jL [i+1. j],

[i+2. j】・・・・【
Nx. Nvl, that is, i changes to 110 II ~ "NX" and one j changes to II OH ~ flNV'', so if you want to generate the "al x + bl - y + clJ part" from that change, first perform the geometric transformation operation. In preparation for starting, a latch control signal is sent from the input terminals 50, 51.56, and the conversion coefficients al+b1+cl are stored in the latch circuits 40, 41.46, respectively. During the scanning period,...i→(i+1)→(jl2)...
A selector control signal is sent from the input terminals 52 and 58 at the timing of , the output (al) of the latch circuit 40 is sent to the selector circuit 42, and the output (accumulated value) of the launch circuit 44 with clear is sent to the selector circuit 48. After selecting and sending to the adder 43, a latch control signal is sent from the input terminal 54,
The added value of the two outputs added by the adder 43 is stored in the latch circuit 44 with clear. The above operation is repeated until i goes from '0'' to 'NX' (during the horizontal scanning period).As a result, the output of the latch circuit with clear 44 is...
(aX・i)→(al・(jl1))→(at・(jl
2))... is updated. On the other hand, during the horizontal retrace period in the raster scan method, 1'I* j is
To. Since it changes from LL j II to l/ jl t'''', a selector control signal is sent to the input terminal 52゜57.58, and the output (bl) of the latch circuit 41 is sent to the selector circuit 42.
, the selector circuits 47 and 48 select the output (accumulated value) of the latch circuit 45 and send it to the adder 43 in the same way as above, and then send a latch control signal from the input terminal 55 to The sum of the above two outputs added by the latch circuit 4
At the same time, a clear control signal is sent from the input terminal 53 to clear the contents (accumulated value) of the latch circuit with clear 44 to II Ojl. The above operation is repeated every horizontal retrace period. This results in
The output of the latch circuit 45 is...(bl・j)→(bl
・(jl1))→(bz・(jl2))... is updated. Note that the first raster (j
="0"), the selector circuits 47 and 48 receive the latch time wt instead of the output (accumulated value) of the latch circuit 45.
46 output (cl) is selected, and adder 4 is selected as above.
3 and also sends it to the adder 49, thereby initializing the geometric transformation. By repeating the above two operations, each time point [i
, jl, the output of the latch circuit with clear 44 is 0+i・(at)=at・i...(
1) On the other hand, since the output from the selector circuit 47 is c1+jlbt)=bt-j+ct'' (2), the adder 49 adds the re-output and sends the output terminal as al・i+b1・jlC1=a1・x+b1・y+c1''...(3) is generated. Regarding the latch, selector, and clear control signals, when raster scanning the pixel coordinates of a digital image, the frequency is generally divided by a counter circuit to generate a clock corresponding to the scan of each pixel. Since the circuit configuration is such that the counter circuit and the decoder circuit are used for initialization, the output signals of the counter circuit and the decoder circuit are used as the control signals for the latch, clear, and selector. From the other locus ifA[x, yl, “a2・x+b2・
Geometric transformation to the y + c 2 J part can also be generated in the same manner as described above, so the explanation thereof will be omitted. In this way, the conversion coefficient "l+b1+CI" is stored in advance, and al is accumulated during horizontal scanning in the raster scan method, and bl is accumulated and the accumulated value of al is cleared to "0" during horizontal retrace. , "al・x+b 1・y+C1" part and "a2°X+b29y+c2J" part, it is possible to replace the conventional circuit shown in FIG. Also, when comparing the conventional circuit and the circuit according to the present invention, firstly, a parallel multiplier is used for the multiplier 6゜7 of the conventional circuit, and the image coordinates 81
．． Comparing the hardware scale under the condition that + bl + C1 is operated on m bits, if the hardware scale (number of parts) per 1 bit is P
, when the latch circuit is 9, the latch circuit with clear is r, and the selector circuit is S, the ratio of the hardware scale is:
The present invention (m+n) ・(2・p+q+r+3 ・s
)+3 ・m ・q Conventional type 2・(m-n0m+
n)・P+3・m−q (4) It can be shown as follows. Therefore, as a concrete example of the hardware scale value (number of transistors Tr and gates) in the CMS process, p = 1.6. Using q = 9, r = 11, s = 3, the circuit according to the invention is approximately 1
/2 (m=n=“B” bit), or about 1/4
(m = n = 16 bits). Also, when operating at the same operating speed, the power consumption of the circuit can be reduced to approximately 1/2 (m = n:
8''' bits), or about 1/4 (m=n=
It can be reduced to "l 6" bits). Second, as above, a parallel multiplier is used for the multiplier 6゜7 in the conventional circuit, and the image coordinates XIY are calculated using n bits, and the conversion coefficients a1, bl, and C1 are calculated using m bits. Comparing the operation delay (seconds) of the circuit, if it is 1
The operation delay per bit is g for the sum output of the adder, g for the carry output of the adder and the larger of g and h for the carry output, d for the latch circuit, and e for the selector circuit. The operational delay from the input of the multiplier 6 to the output of the adder 9 in the circuit according to the invention and the latch time w! in the circuit according to the invention. The ratio of the operational delay from the input of I45 to the output of adder 49 can be expressed by the conventional formula (m+n+1)·k (5). Therefore, by configuring the circuit according to the present invention using a commonly used adder whose operation delay for carry output is designed to be smaller than the operation delay for sum output, the conversion coordinates per pixel can be reduced. generation can be operated faster than conventional circuits. As a result of the comparison, it was found that the coordinate generation circuit that performs geometric transformation of a digital image can be constructed on a small scale and with low power consumption.
It becomes easy to convert into I. [Effects of the Invention] As explained above, according to the present invention, ak is accumulated during horizontal scanning in the raster scan method, and bk is accumulated during horizontal retrace.
Since the digital image is geometrically transformed by accumulating ak and clearing the accumulated value of ak to ``0'', the geometric transformation coordinate generation circuit can be made smaller and the power consumption can be reduced without using special circuit components. do.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of the geometric transformation coordinate generation circuit according to the present invention, FIG. 2 is a circuit block diagram of a conventional geometric transformation coordinate generation circuit, and FIG. 3 explains the operation of FIG. 1. This is a diagram for 1 to 5, 40, 41, 45, 46: latch circuit, 6.7
: Multiplier, 8.9, 43, 49: Adder, 42.47.
48: Selector circuit, 44: Latch circuit with clear, 50
~58: Input terminal.

Claims (1)

[Claims] (1) Pixel coordinates obtained by raster scan method [x
, y] into the form f(x, y) = a・x+b・y+c, [a_1・x+b_1・y+c_1, a_2
・x+b_2・y+c_2] In a geometric transformation coordinate generation circuit that performs geometric transformation of a digital image such that it is mapped to the coordinates of
3...) and a first storage circuit that stores bk;
a circuit that accumulates the corresponding ak or bk when the coordinate x or y of the conversion increases; a second storage circuit that stores the accumulation result corresponding to the coordinates x and y from the accumulation circuit; , a circuit that initializes the value of the corresponding accumulation result in the second storage circuit to "0" or "ck" when the coordinate x or y is initialized to "0". Features a geometric transformation coordinate generation circuit.