JPS61206988A - Sector controlling system for magnetic disk device - Google Patents

Abstract

PURPOSE:To enable to give sufficient time to make error correction by error correcting codes minimizing gap length by detecting end of a sector separately from the reading of address information, and counting the number of passed sectors after reading address information. CONSTITUTION:The end of a sector is detected by monitoring the output of a sector synchronizing circuit 40. In the case of data reading, SYNC detected first after detecting termination of preceding sector is the forefront SYNC of the sub-frame of objective sector. Accordingly, data for 1 sector is read from this point of time, and stored in a data RAM 48. Then, after making error correction and the confirmation of address information, the data part is sent to a host such as a microcomputer etc. through a system bus. Writing is started from a gap, and since it is ensured by the sector synchronizing circuit 40 at the time of starting writing that preceding sector passed through the head, there is no possibility of destruction of the preceding sector.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a magnetic recording/reproducing device, and particularly to a sector management method suitable for a magnetic disk device that requires high reliability.

[Background of the invention]

In a magnetic disk drive, a disk-shaped magnetic recording medium is divided into concentric tracks, and these tracks are further divided into several sectors, and data is read and written in each sector. Track designation is performed by controlling the position of a head that moves in the radial direction of the magnetic disk, and sector designation is performed by reading address information recorded on the magnetic disk and using this information.

A conventional sector management method will be explained using FIG. FIG. 1 shows the recording format of a widely used 8-inch floppy disk device. As shown in the figure,
One track is divided into 26 sectors, and in addition to these sectors, there are index marks of 3° for rotational synchronization, gaps, l and 9 for absorbing rotational speed deviations.
is added. Preamples 2, 10, and 18 are used to pull in the VFO for demodulating subsequent data.

Data, address information, etc. of each sector are recorded using a modulation method called FM modulation.

This means that one bit of data corresponds to two pulses called a clock pulse and a data pulse, and if there is only a clock pulse, it is demodulated as '0' data, and if both a clock pulse and a data pulse are present, it is demodulated as '1' data. However, index mark 3. ID address mark 11
．． The data address mark 19 is an exception, and is a signal in which some clock pulses are missing. This is used to distinguish from other data and indicate the start of a track, the start of an ID section, and the start of a data section υ.

Each sector is divided into an ID section and a data section. The ID section contains track number 12. Address information such as head number 13 and sector number 14 is recorded. ID CRC
16 is a code for detecting errors in the information in the ID section.

Next, a method of sector management when using the format shown in FIG. 1 will be explained, taking the case of data writing as an example. The control device (LSI called FDC, tlA Fujitsu ME8877, Aji Nippon Electric μPD765, etc. are often used) has a register that holds the track number, head number, sector number, sector length, etc. of the target sector. After these registers are properly set, a write operation is initiated by receiving a write command.

First, the ID address mark 11 is detected. As described above, this is a signal with a special pattern in which the clock pulses are missing, so it can be detected separately from other data portions.

The second is a 4-byte signal following the ID address mark, track number 12. Head number 13° Sector number 1
4. The sector length 15 is read and compared with the contents of the corresponding internal register. At the same time, the ID CRC16 is read and the read address information is checked for errors. If the address information does not match, or if there is an error in the read address information, the process restarts from the first stage of address mark detection.

Third. If the address information matches and there is no error in the read address information, wait for the time until the end of the gap 17, switch the head from reading to writing, and write the preamble 18 and data address mark 19. Next, the host system is requested to write data, and the sent data is written into the data section 20. After writing data with a length indicated by sector length 15, data for error detection (CRC21) is written. This is the procedure for writing one sector of data.

The sector management method using such an ID has the following table problems.

Firstly, ID section verification and erroneous ID detection must be performed at high speed. There is no problem in the case of the 8-inch floppy disk device described here, but in order to reduce the error rate in the ID section, it is possible to use an error correction code such as a Reed-Solomon code instead of IDCRCO. , when increasing data read/write speed to increase recording density or improve access time, I
Verification, error detection, or correction of the D section must be performed at high speed, and the hardware required for this purpose is complex, large-scale, and expensive.

Second, a gap 17 and a preamble 18 are required between the ID and the data section. The gap 17 is necessary to provide time for the above-mentioned address information comparison and error detection, and head switching time during writing.

The preamble 18 is necessary for pulling in VFO0 used for data demodulation during reading. These reduce the net storage capacity.

Fifth, since ID verification is always performed before reading or writing data, if an error occurs in the ID, it becomes impossible to read or write data. When error correction codes are used to reduce the ID error rate, the first problem is
That is, the problem is that it becomes difficult to perform ID verification and inspection at high speed. This is because the process for error correction is more complex than the process for error detection alone.

Nao, % Kosho 55-45704 describes a sector management method that eliminates the gap between ID and data and eliminates the need for a preamble. However, even in this method, the address information is recorded in a concentrated manner in one location in each sector, so if a burst error occurs in this location, it becomes impossible to read out the address information. A burst error is a phenomenon in which several bits to several hundred bits become unreadable in succession, and is a phenomenon that is particularly problematic when reading and writing at high recording densities. Further, the method described here does not take into account the case where error correction of address information is performed.

[Purpose of the invention]

An object of the present invention is to provide a sector management method that does not use the problematic ID described above, has high reliability, and reduces storage capacity.

[Summary of the invention]

In the present invention, by adding an error correction code to the sector address information, distributing it throughout the sector, and performing multiple writing, the readout of the address information and the consistency check are made highly reliable.

Furthermore, apart from reading address information, a circuit is installed to detect the end of a sector and count it, and by counting the number of sectors that have passed after reading address information, the gap length can be minimized while the error can be detected. This makes it possible to provide sufficient time for error correction using correction codes.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows the configuration of this embodiment. The magnetic disk 55 is rotated at a constant speed by a spindle motor 56. A head 53 attached to a carriage 54 writes and reads data to and from a magnetic disk 55 .

The carriage 54 and head 53 are operated by a step motor 57.
is driven by and positioned on an arbitrary track.

A small magnetic piece 51 is attached to the magnetic disk 55. When this small piece comes directly under the detection coil 52, the detection coil 52 generates a signal (index signal).

The signal reproduced by the head 53 is demodulated by the demodulation circuit I, and is sent to the data RAM 4B and the sub RAM 42.
is stored in Address information is stored in the sub-RAM. Then, the ECC circuit 46 detects and corrects read errors.

Here, a so-called Reed-Solomon code is used as an error correction code. The data corrected on RAM 48 is sent to the outside (microcomputer, etc.) via system bus 58.

At the time of writing, data sent from the system bus 58 is first stored in the RAM 48, and a code for error correction by the ECC circuit 46, a subframe, and a subcode (described later) are created and added.

The modulation circuit 47 modulates the magnetic disk 5.
5.

In this embodiment, a modulation method called an 8/1o conversion method is used. This method divides the data to be recorded into 8-bit units, converts the 8-bit data into a 10-bit code according to a predetermined conversion table, and records this 10-bit code.

The 5YNC detection circuit 45 detects a 5YNC signal (described later) and is used for frame synchronization.

Sector synchronization circuit 40 creates the timing of the beginning and end of each sector. A control circuit 49 controls reading/writing and data transfer through the system bus. Also, the speed control of the spindle motor 56, the step motor 5
7 is performed by a motor control circuit 50.

The track format used in this embodiment is shown in FIG. Thus, one track is divided into four sectors, and each sector is divided into 129 frames. Figure 4 shows the frame format. The format of the data frames from frame φ to frame 127 is shown in FIG. 4 (α), and the format of the subframe is shown in FIG. 5Y#C60 is a code for separating frames, and is a code that does not appear in the sequence of codes obtained by 8/1o conversion, so that it can be easily distinguished from data existing before and after it.

The frame address 61 records the value obtained by adding 128 to the frame number (0'' to '127') of the frame.The next SUB 62 constitutes a subcode to be described later.Next Parity 63 is a code added to detect errors in frame address 61 and SU E 62, and is obtained by exclusive ORing each bit of 61 and 62.

Data sent via the system bus is recorded in the data section. Parity C1- is a code for correcting errors in the frame address 61 and data. Parity C2- is also a code that performs error correction, but a method called interleaving is used to calculate parity 0, and the error correction ability when CI 16d and C2i+51 are combined is extremely high. There is.

FIG. 4 (hl shows the format of the subframe.

One subframe is provided for each sector, >,6
, address information, etc. are recorded. S Y N C
67, the same signal as SYNC60 of the data frame is recorded. Data "'0" indicating that the frame is a subframe is recorded in the frame address.

In 5 U E 69, a part of the subcode is recorded in the data frame, but 0'' is recorded in the subframe. This is because there is no need to record the subcode in the subframe. This is to make the format from 5YNC67 to parity 70ma common between data frames and subframes in order to detect frame address errors, and to share hardware.

Parity 70 is similar to parity 63 of the data frame,
It is used to detect errors in frame address 68 and SUE 69.

mode 7], the reserved area 76 is a part indicating the format of the data frame, etc., and is set to all 0'' in the format shown in FIG. 4 (tX).

Track number 72, sector number 73 and head number 74
is the address information of the sector. Parity C1 (
C) is a code for error correction. The copy protection 75 is used to prevent unauthorized copying of recorded contents, but since it is not essentially related to the present invention, its explanation will be omitted.

The length of each region is shown at the bottom of Figure 4 LtL) and Lc.

B represents a byte and has a length corresponding to 8 bits of data. For example, parity C1- is 4 bytes long.

Next, the subcode will be explained using FIG.

The subcode includes 32 bytes of information shown in FIG. 5 tc). This includes address information with some of the subframe contents deleted. In this way, in this embodiment, address information is recorded five times in total.

This subcode is divided into 1 byte units and written to the SUB of each data frame.

Since there are 128 data frames, the same subcode will be recorded four times. In other words, the address information is 1
Each byte is distributed in each frame.

When extracting the subcode, conversely, the SUB of each frame
Just take them out and connect them in order. Furthermore, since the same subcode is written four times, it is possible to completely read out the subcode even if reading starts from the middle of the sector.

Next, with reference to FIG. 3, the sector management method of the present invention will be explained using the case of writing to sector 3 as an example.

The head number is transmitted from the system bus 58 to the control circuit 49.
Track number, sector number (here it is sector 3, so the sector number is 62'.

Note that the sector numbers of sectors 1 to 4 are 0'' to ``3''.

) is specified and a data write command is sent, the control circuit 49 analyzes this command and starts a write operation to the designated sector.

The control circuit 49 internally holds address information such as track numbers, and requests data to be written to the system bus. Data sent from the system bus is data R
The signal is stored in the AM, and subframes, subcodes, etc. are added as shown in FIGS. 2 and 4, and a code for error correction (Reed-Solomon code) is added.

It also gives a command to the motor control circuit, and
Move to the specified track.

Next, the target sector 3 is found, and the procedure will be described below.

'+, 5YNC is detected, and the frame address recorded next to 5YNC is read. Subsequently, SUE and parity are read out to check for frame address errors. If it is an error, try again from 5YNC detection.

2-A, if the frame address is 1″O″, that is, a subframe, the contents of the frame are read to the subRAM 42;

2-B. If the frame address is ``128'' or more, that is, it is a data frame, and it is ``224'' or less, the subcode can be read. (See Figure 5. The frame address of the data frame is to the number of
128".) In this case, in order to read the subcode, take out the SUB and read the sub RA.
Repeat the operation of storing data in M 32 times without changing.

2-C. If the frame address is 225 or more, wait for the next sector and start over from step I@i.

3゜In order to set the sector from which the subframe or subcode has been read as temporary sector 1, the sector counter (
(not shown) to "+".

4. Perform error correction on subframes or subcodes in sub RAM 42. If an uncorrectable error is detected, start over from step 1.

5. The track number and head number are extracted from the subframe or subcode in the sub RAM 42 and compared with the track number and head number held in the control circuit 49. If they do not match, it is considered to be a malfunction of the motor control circuit 50 or the like, so the write operation is interrupted and the host (microconbeater, etc.) is notified of the abnormal end via the system bus.

If the track number and head number match, it is confirmed that the designated head has been selected and is located on the designated track.

6. Add the value of the sector number extracted from the subframe or subcode in the sub RAM 42 and the count value of the sector counter in the control circuit, and set this value in the sector counter. Since the sector counter increases by 1 by counting the output of the sector synchronization circuit 40,
Even if the magnetic disk rotates for one sector or more between 4 and 5, the number of sectors that have passed is counted by the sector counter. By adding the sector number taken out from the sub-RAM, the sector counter will indicate the sector number of the sector where the head is currently located. Note that since the sector numbers are from 0 to 3, the sector counter is configured in 4 bases, and the above addition is in the remainder system of 4 (remainder when divided by 4).
It will be held in

7. Since the sector counter now indicates the correct sector number in step 6, the control circuit 49 monitors this count until it reaches the sector number immediately before the designated sector. In this case, since sector 3 has been designated, it is only necessary to match the sector number 1 of sector 2 with the count value of the sector counter.

8. If the sector immediately before the target sector is found, the end of this sector is detected by monitoring the output of the sector synchronization circuit 40. In this case, the head will be detected when it is positioned past the boundary between sector 24 and gear 4 shown in FIG.

9. Now that the target sector has been found, data can be written in accordance with the sector format shown in FIG. Here, writing begins from the gap between sector 2 and sector 30, the preamble, subframes and each data frame prepared in the data RAM 48 are written, and the write operation is completed. Since the gap portion is filled with an unmodulated signal (DC signal) and the preamble is a repetition of data "'On," it can be written with a simple circuit, and there is no need to prepare it in the data RAM 48.

In the case of data reading, the first SYNC detected after detecting the end of the previous sector is the first 5YNC of the subframe of the target sector, so from this point on
It is sufficient to read data for a sector and store it in the data RAM 48. After that, error correction and address information confirmation are performed, and the data portion is sent to a host such as a microcomputer via the system bus.

What you need to be careful about here is to start writing from the gap. In traditional sector management methods,
To avoid accidentally writing to adjacent sectors, we did not write to the gap portion. However, according to the present invention, since the sector synchronization circuit guarantees that the previous sector has passed through the head at the time writing starts, the previous sector (sector 2 in the above example) is There is no danger of destruction. Furthermore, since the end of writing is performed by the end of data (postamble), there is no risk of destroying the next sector (sector 4 in the above example).

By writing to the gap, even if there is unerased data in the gap, it can be erased, and malfunctions of the 5YNC detection circuit, sector synchronization circuit, etc. caused by the unerased data can be prevented. can. Generally, unerased data may be caused by deviations in the rotational speed of the magnetic disk, timing errors in the control circuit, etc.

As described above, according to this embodiment, error correction is performed on the address information of each sector, and reading and writing can be performed at the highest access speed while improving the reliability of searching for the target sector. I can do it.

Next, an example of the configuration of the 5YNC detection circuit will be described. 5
The YNC detection circuit is an important circuit used for sector synchronization and subcode reading. Figure 6 shows the configuration.

The read serial binary data is input to the input terminal 99 . The shift register gives input data a time delay equivalent to two frames. The shift register 91 converts input data into parallel data. Since the 5YNC signal used here is 10 bits long, this shift register 91 is also 10 bits long. A pattern generation circuit 92 provides a prescribed 5YNC signal pattern. Comparison circuit 93 compares two pieces of input data and outputs their Hamming distance. The Hamming distance represents the degree of coincidence between two pieces of data, such as O'' if all bits of the two data match, and '1' if only one bit is incorrect. Shift register 94, 9
5 gives a time delay equivalent to one frame. The coincidence determination circuit 96 determines the three input Hamming distances and determines whether the signal is a 5YNC signal or not.

Next, the operation of this circuit will be explained. This circuit utilizes the fact that the 5YNC signal in each sector is recorded exactly at one frame period.

The data input from the input terminal 99 is converted into parallel data, and then compared with the 5YNC pattern by the comparison circuit 93. The resulting Hamming distance is determined by the coincidence judgment circuit 9
6, but input to 96 is through shift registers 94, 9.
5, the comparison results of one frame before and two frames before are input at the same time. The match judgment circuit 96 performs a match judgment on these inputs using majority logic, for example, ``If two or more of the three are "0" (complete match), then all are considered to be a match.'' The 5YNC detection signal is output from the detection power terminal 97. By using such judgment conditions, even if the 5YNC signal is lost at one location due to r dropout, the 5YNC signal will not be detected in that part.
It is possible to generate an NC detection signal, and even if part of the data is input as a 5 YNC signal pattern by mistake, the data one frame before or two frames before that is 5 YNC signal.
Since it is not an NC signal, an erroneous 5YNC detection signal will not be generated.

Here, the correct match is the first 5Y
Since this is two frames after the NC signal is input (because of the shift registers 94 and 95), the data signal must also be delayed by two frames accordingly. This is done by means of a shift register.

Also, when applying this circuit to the configuration shown in Figure 3,
Since the read data is delayed by two frames, the start of writing to the target sector is delayed by two frames. This problem is solved by detecting the end of frame 125 two frames before the target sector, rather than the "end" of the sector before it, and starting writing with a delay of several bytes to prevent data from being destroyed. .

Next, an example of the frame address and subcode detection circuit is shown in the seventh section.
This will be explained using figures. 101 is the input terminal for the 5YNC detection signal, 103 is the parallel data input terminal, 8/
Data demodulated by performing inverse conversion of 10 conversions is input one byte at a time. Reference numeral 102 is a strobe signal for inputting this data. The counter 107 counts the input pulses, and when three pulses are input, the logic
1".Here, the strobe signal input from 102 is outputted as 4 by the inverting gate and the AND gate.
After counting, it is configured to stop counting while outputting logic 1. The counting operation of the counter 107 is 10
It will not restart until it is reset by the 5YNC detection signal input from 1.

D flip-flops 108, 109 and 110 are used to hold three consecutive bytes of data.

The parity check circuit 111 is a logic circuit that performs an exclusive OR operation on each bit of 3-byte input data, and outputs a logic "1" if all the results are ON. This parity check circuit 111 is used as shown in FIG.
, A can perform error detection using parity 63°70.

FIG. 8 is a time chart of this circuit.

In this figure, A is the parallel data input to the input terminal 103, B is the 5YNC detection signal input to the input terminal 101, and C is the 5YNC detection signal input to the input terminal 101.
is a data strobe signal input to 102. D
is the count value of the counter 107, and E is the output signal of the AND gate 106. F, G and H are D flip-flops 1
These are output signals from 08 to 110.

In the figure, S is the data of the 5YNC signal portion.

However, as mentioned above, the 5YNC signal has a pattern that is not included in the conversion table for 8/10 conversion, so it cannot be inversely converted. That is, invalid data appears in the portion represented by S.

Some data appears in the parts indicated by W, X, Y, and Z. However, these are related to the previous frame and are irrelevant at the time shown in FIG. 8, so they are expressed in this manner.

Now, the operation of the circuit shown in FIG. 7 will be explained using FIG. Since the data strobe signal C is constantly input, the counter 107 has a count value of "4" and is stopped.

When the 5YNC detection signal B is input here, the counter 1
07 is reset, and the AND gate 106 outputs five pulses as shown in E. At the rising edge of the fifth pulse, the count value of the counter 107 becomes '4' and the output of the inverting gate 105 becomes logic 'O'.

Therefore, the output of the AND gate 106 also becomes the logic "'0", and the output of the AND gate 106 remains at the logic "I" ON until the 5YNC detection signal is generated.

Here, the output of the D-flip 70 block 108 is the data inputted from 103 delayed by a time corresponding to one byte. Similarly, the outputs of 109 and 110 are delayed by 2 and 3 bytes. For this reason, and gate 10
After the fifth output pulse of No. 6, the parity, SUB, and frame address are each held as shown in FIG. At this time, error checking is being performed by the parity check circuit 111, so this
By taking the logical product of the output of the counter 11 and the output of the counter 107, it is possible to obtain a signal that becomes logic "1" only when the data at the output terminals 115 and 116 are correct. In FIG. 7, the AND gate 112 performs this operation, and the monostable multivibrator 113 outputs the frame address detection signal, which is a pulse signal with an appropriate width, to the output terminal 11.
Output from 4. In the external circuit, this is when a pulse is output from the output terminal 114.

By referring to the output terminals 115 and 116,
The correct frame address and SUE can be obtained.

As described above, by using this circuit, it is possible to check for errors in the frame address and SUB at the same time as reading the parity in each frame, and to extract only the correct frame address and SUE at high speed.

Next, a configuration example of the sector synchronization circuit will be explained. An example is shown in FIG. This uses the frame address output from the circuit shown in FIG. 7 to reliably determine the end timing of a sector. The configuration of this circuit will be explained. The frequency divider 124 divides the byte strobe signal input from the input terminal 123 (same signal as the signal input to 102 in FIG. 7; one pulse is generated for each byte read) by 44 (one frame is I byte.4th
(see figure) and outputs a signal with one frame period. The counter 126 receives the frame address input from 121 and 1
The frequency divider 124 is synchronized with the frame read out by the frame address detection signal input from the
Frame addresses are counted by counting the outputs of . The variable timer 127 measures the time corresponding to the gap between sectors.

Next, the operation of this circuit will be explained with reference to FIG. A represents data to be read. Each number represents a frame number,
"Sub" indicates a subframe. B is 122
The frame address detection signal inputted from C is 121.
Indicates the frame number to be input. For frame 126, the frame address was read incorrectly and the frame address detection signal was not output. D is the output of the branch divider 124, E is the count value of the counter 126, and F is the output of the variable timer 127.

The operation is performed as follows. Here, first frame 1
When the frame address No. 25 is detected without error, the frame number is set in the counter 126 by the frame address detection signal, and at the same time, the OR gate 125 resets the branching unit 124.

(Frame 1250 part) Since the frame address of the data frame is the frame number plus 128, it is expressed in binary as 128 == 2', so the frame address 2? The frame number can be obtained by replacing the bit in the digit with OK.

If the frame address of the next frame cannot be detected, the signal is output from the divider 124 at the U-th byte after the frame address of the previous frame is detected, that is, when the frame address of the next frame should be detected. be done. When the counter 126 counts this signal, the counted value indicates the correct frame number.

In this way, if a strange frame address is detected, the counter value is set to indicate the frame number at that point, and even if no frame address is detected in the future, the counter value will be correct. It will now show the frame number.

Counter 126 issues an output signal when its count reaches 128. This signal indicates the end of the sector and is output from the output terminal 12B to the outside. At the same time, the output of counter 126 triggers variable timer 127. The variable timer outputs a pulse with a certain time width depending on the trigger input.

Me) This time is input as 129 so that when the end of sectors 1 to 5 is detected, the time corresponds to 4 degrees, and when the end of sector 4 is detected, the time corresponds to 8 degrees. selected by the signal. Values such as 4° and 8° are determined based on the length of the portion other than the data frame of the track format shown in FIG. The signal selecting the 129 time widths is generated by a sector counter (not shown) in control circuit 49 (shown in FIG. 3). While the pulse is being output from this timer 127, the counter 1
26 and frequency divider 124 are reset and stop updating the count value of the counter.

Thereafter, in the same manner, by detecting the frame address, it is possible to continue to reliably detect the end of the sector.

According to this circuit, sector synchronization can be achieved reliably.

If no frame address can be detected in one sector, sector synchronization cannot be achieved, but frame addresses are recorded dispersedly in one sector, so it is unthinkable that all of them are errors. . This is because this kind of thing only occurs when the error rate is extremely high, and in that case it is originally not suitable for data recording.

〔Effect of the invention〕

As described above, according to the present invention, even if a reading error occurs in a part of a sector, the error in address information can be corrected and read out, and the reliability of address information can be improved. .

Further, there is an effect that it is possible to eliminate the ID gap and prevent a decrease in storage capacity.

[Brief Description of the Drawings] Fig. 1 is a track format diagram of a conventional system, Fig. 2 is a track format diagram of an embodiment of the present invention, and Fig. 3 is a track format diagram of a conventional system.
Figure 4 is a diagram of the configuration of an embodiment of the present invention, Figure 4 is a frame format diagram of an embodiment of the present invention, Figure 5 is an explanatory diagram of subcodes, Figure 6 is a SYNC detection circuit, and Figure 7 is a frame address. and SUB detection circuit, FIG. 8 is a time chart of FIG. 7, FIG. 9 is a sector synchronization circuit, and FIG. 1O is a time chart of the circuit of FIG. 9. 53...Read/write head 55...Magnetic disk 45...5YNC detection circuit 42...Sub RAM
46...Error correction circuit 48...Data RA
M49...control circuit

Claims (1)

[Claims] In a sector management method in a magnetic disk device in which sector address information is distributed and multiplexed recorded in sectors, a sector detection circuit and a sector counting circuit are provided, and the output of the sector detection circuit is input to the sector counting circuit. A sector management method in a magnetic disk device, characterized in that reading and writing to a target sector is performed by counting the number of sectors from a known sector to a target sector using the sector counting circuit.