JPS61204743A - Interruption controlling system for microprocessor - Google Patents

Abstract

PURPOSE:To reduce an overhead of a simulation processing of VMM which follows the generation of an external interruption, by always setting a value of a state for receiving the external interruption, to a field of an interruption mask code of a real state control register. CONSTITUTION:To an interruption control part 110, a value of a real interruption mask code, and a value of an interruption mask code (virtual interruption mask code) in a status control register corresponding to a running VM are inputted from a status register control part 100 through a signal line l 5 and a signal line l 6, respectively, and an external interruption number is inputted through a signal line l 61 from an external circuit. In case when an external interruption which has been generated, based on said input signal group is in a state that it can be received by a CPU, the interruption control part 110 sets this interruption number and an interrupting operation start signal to a signal line l 20 and a signal line l 21, respectively, and sends out a signal to an instruction execution control part 115.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an interrupt control method for a microprocessor when an external interrupt such as an input/output interrupt occurs.

[Background of the invention]

In recent years, the concept of ``virtual computer'' has been considered and is being put into practical use. As shown in Figure 1, a virtual computer system consists of one real computer (base machine).
Machine) (hereinafter referred to as BM) 501, there are apparently multiple operating systems (○perat
ing Syst, ern; hereinafter referred to as OS) 5
06.507 can be run at the same time. Therefore, in the environment of a conventional real computer system, instead of the 0S506, 507, etc. operating under the 8M501, a special control program (Virtual Machine Monitor)
eMonter) 502 (hereinafter referred to as VMM) is operating, and VMM is 8M501 for 08506°507.
provides a base machine interface 508 that is the same as the base machine interface 503 provided by . VMM 502 is the base machine interface 50
The machine that virtually created VM 8 is called a virtual machine (hereinafter referred to as VM). Note that although only two virtual machines, VM504 and VM505, are shown in Figure 1 as virtual machines, Naturally, a large number of virtual machines can be created.

Under each of the VMs 504 and 505, ○5506 and 08507, which conventionally operated under the BM 501, operate at higher times than expected. In addition, QS506.507
Extended machine interfaces 513 and 514 are provided to programs (UserPrograms hereinafter referred to as UP) 515 to 518. Here, the expansion machine (E
xtendedMachine is hereinafter referred to as EM. )5
What is 09-512?

Processing in response to a request for a certain set of functional processing from a user program (usually called a supervisor call or function call).

The functions that each OS executes within its O8, and the base
It has a machine interface function.

Therefore, if 08506 and 08507 are different, EM509 and EM511 are executed every O8.
are of course different functions.

The above is a virtual computer system (V 1rtual Ma
chin45Systei+hereinafter referred to as VMS), which allows a plurality of different O8s to apparently run simultaneously on one BM. Therefore, the following effects can be expected.

(1) It is possible to depack or test a newly developed system without stopping the services of the running system.

(2) Since one BM can operate a plurality of different O8s, it is possible to reduce the cost of actual hardware and improve the efficiency of using hardware resources.

(3) A computer system with a slightly different architecture or a slightly different system configuration can be created virtually, and a program can be tested by controlling a new device even when the actual device is not connected.

By the way, a special control program VMM 502 exists to realize the concept of VMS shown in FIG. VMM
502 is VM504. In order to operate the VM 505 and the like efficiently, a normal multiprogramming technique is used, and the hardware resources of the 8M 501 are divided temporally and spatially and allocated to each VM 504 and 505. Furthermore, the base machine interface 508 provided by the VMM502 is functionally the same as the base machine interface 503 provided by the 8M501, so the O3 that can be executed on the 8M501 is the VM504, VM50
5 can be executed in the same way. Fundamentally, therefore, a VM is equivalent to the BM it uses, with no discernible functional differences, VMM502
does not interpret and execute the O8 and UP programs for each instruction, and most of the time the program is
Allows direct execution in M501. However, when the VMM 502 detects an instruction (privileged instruction, which can be executed when the operating mode is privileged mode) that operates on hardware resources issued by the O8,
To ensure the overall integrity of the system contents within the VMS, the sensed instructions are interpreted and executed, and control is returned to the executing program after the interpretation and execution is complete.

This processing is necessary because the resources of the BM 501 are shared between the VMs, and this processing time becomes an overhead specific to VMS, which causes a decrease in performance. Regarding the shared control of main memory among hardware resources,
This is achieved using virtual memory control technology.6 Specifically, each virtual memory area created by the VMM 502 is
Allocated as main memory of M504.505. Therefore, if 03506 of VM504 becomes O8 which adopts the virtual memory method again, or if 03506 of VM504 again uses another VM
When MM is operated, two levels of address translation are required, which creates overhead unique to VMS. The overhead specific to VMS is caused by the sharing of actual hardware resources, and can be classified as follows.

(1) Overhead of privileged instruction simulation processing.

(2) Overhead of switching service processing (referred to as dispatch processing) for each VM.

(3) Overhead due to two-level address translation due to virtual memory support.

(4) As an example of a patent for suppressing interrupt simulation processing overhead/VMS-induced performance degradation,
JP-A-50-23146, JP-A-57-2126
No. 80, and Japanese Patent Application Laid-Open No. 55-53749. JP-A-50-23146, JP-A-57-21
Publication No. 2680 discloses a method for reducing the overhead caused by two-level address translation. JP-A-50-23146 intends to provide each level of the VMS with its own f-map in the address translation process. This f-map is an 8-doware virtualization mechanism (Hardvare Virtualizer or later) that operates beyond one VM level.
It is called V. ) is intended. Further, the above invention is limited to VMs that are replicas of the base machine;
It is restricted to VMs that have an inductive relationship to the base machine.

The invention disclosed in Japanese Unexamined Patent Publication No. 57-212680 is a dynamic address conversion method using a shadow table that can perform address conversion beyond two or more levels, in contrast to the conventional two-level address conversion.
s Translation, hereinafter referred to as DAT. ) method, it eliminates the shadow table and replaces it with a translation index buffer mechanism (Translation Locator).
OK-A 5EDE Buffer is hereinafter referred to as TMB.

) is used to indicate whether the address is a second-level or second-level address conversion pair, thereby increasing the speed of conversion from a logical address to a physical address in the main memory.

However, this is an attempt to improve the performance of only a specific VM.

The above invention is limited to application to a computer system configuration having a DAT and a TLB.

The invention disclosed in Japanese Unexamined Patent Publication No. 55-53749 provides a base machine with separate a plurality of operation registers used by O8 operating under VM and a plurality of operation registers used by VMM.

This is intended to reduce the overhead of saving arithmetic registers/circuit processing when the VMM performs simulation processing of privileged instructions issued from the O8 operating under the VM. However, the arithmetic register group allocated for VM is only one set, and must be shared between VMs. Therefore, when switching running services between VMs, it is necessary to replace the calculation registers allocated to the VMs.

Incidentally, the effectiveness of virtual computer systems is being recognized in the field of mainframe processors (large general-purpose computers), and attempts are being made to put them into practical use. Furthermore, the invention of the earlier application is also directed to main frame processors.

Now, with recent remarkable developments in large-scale integrated circuit technology, microcomputer technology has made a significant leap forward. A personal computer is created by combining a microcomputer and its peripheral circuits.
A computer system is realized as er (hereinafter referred to as pc).

Since the PC has only one user, the scale of the O8 that operates on the PC is significantly smaller than that of the large computer system O8, and the functions of the O8 are also simple. Specifically, on the O8 of the PC.

It does not have multi-programming or multi-job functions. This is because the purpose of PCs is primarily for personal use.

Therefore, the O8 of a PC is easy to create, and many application programs that closely depend on the functions of the O8 have been developed. Here, if the functionality of an application program that runs under the O8 of a particular PC is very attractive, a demand arises to use the application program under other O8 environments. However, if the 08506 or the like is operated directly on the BM 501 without adopting the virtual computer system configuration shown in FIG.

In order to run the necessary application programs, it is necessary to replace the O8. Alternatively, the O8-dependent parts of the attractive application program must be reprogrammed so that it can operate under other O8 environments.

However, PC users want to use the functions of application programs immediately, and do not want to replace the O8 or reprogram the application programs. Therefore, the method of using a virtual computer system as shown in FIG. 1 is an effective solution. Current microprocessor-based PCs do not have hardware control circuit support to reduce the overhead of VMM when realizing a virtual computer system.A typical microprocessor of this type is Motorola's Microprocessor.・Processor 68000 or Intel's 8086.8088
and so on. Note that the architecture of the 68000 is discussed in the following paper.

“A Microprocessor Architecture
culture for changing world
: the Motorola 6g000″Com
puter vol, 12 pp, 43-51.
(1979-2) Also regarding the 8086 architecture.

The following publications are published by Intel Japan Corporation.

"i AP The scale of O8 is also smaller than that of a main frame processor, so there is a great deal of interest in running attractive application programs under a virtual computer system.

However, the overhead of the control program VMM that implements the virtual computer system cannot be ignored.

In particular, the O8 that runs on a PC does not have a virtual memory function unlike the O8 that runs on a large general-purpose computer. Showa 5
A solution to the interlayer of two-level addressing as disclosed in Japanese Patent Publication No. 7-212680, and
Solutions in the field of main frame processors, such as the solution of having separate arithmetic register groups for VMM and VM in order to speed up privileged instruction simulation processing, as disclosed in Publication No. 5-53749. In addition to this, the following problems arise as a virtual computer system using a microprocessor.

(1) Overhead due to realizing a virtual computer system using a virtual memory method.

Because of the virtual memory addressing method, the DA
The overhead of T operation and TLB management remains.

(2) Overhead of switching service processing (referred to as dispatch processing) for each VM.

(3) Overhead of privileged instruction simulation processing.

Privileged instruction simulation processing for manipulating status registers in the microcomputer that constitutes the PC becomes overhead.

(4) Overrun of interrupt simulation processing When an interrupt occurs, it is reported to the VMM responsible for the interrupt, and the VM
Simulation processing overhead for M to report back to the VM.

Unless the above problems are solved, even if you want to run an attractive application program that is closely related to the functions of O8 that runs on a PC, the performance will be inferior to that on an actual computer. The problem remains.

Among the above problems, regarding (3) privileged instruction simulation processing and (4) interrupt simulation processing, we have focused on the problems when realizing a virtual computer system using a microprocessor, especially when changing the status register. This will be clarified from the relationship between the simulation processing that occurs and the interrupt operations that occur afterwards.

FIG. 2 shows the main memory (main storage area) 200 in the base 7928M501 shown in FIG. 5 shows the correspondence between the virtual main memories 201 and 202 of the 505 group and the real main memory 200.

That is, under the virtual computer system, the virtual main memory 201 of each VM is associated with a certain area within the actual main memory 200.

On the other hand, the user program UP505 and operating system 08506 in FIG. 1 operate by regarding the virtual main memories 201 and 202 as real main memories.

Therefore, there is no need for the 08506 and the UP505 to be aware that they are operating under a virtual computer system. The virtual machine monitor (V
It is a special control program called 502 (hereinafter referred to as VMM).

The virtual machine monitor VMM 502 uses control blocks VMLIST 205 and 2 to smoothly manage the running of each VM.
06 etc. are created and managed corresponding to each VM. VML
For IST205.

As shown in FIG. 2, the status of the VM and the values of status register operation registers are stored. When running the VM under a real processor, VML I 5T2
The values of the status register and operation register stored in 05 are set in the actual microprocessor. In addition, VMI
DM207 is a pointer that points to the control block VML I Sr105 for the VM currently in running service.

The above is an overview of the operation of a virtual computer system in a microprocessor. Here, when a virtual computer system is configured using a microprocessor, the operation is different from when a virtual computer system is configured using a conventionally known main frame processor.

In a virtual computer system using a microprocessor, this is a status control register (StatusRegis).
This is due to the fact that interrupt generation factors are processed by the vector table (ter) and the vector table. That is, VMM502
(7) When dispatching a VM, the interrupt mask value of the microprocessor's state control register is set to 0, and the supervisor mode bit value is set to 0. FIG. 3 shows an example of a state control register in a microprocessor, and the details of this state register are described in the previously disclosed article on Computer Vol. 12, pages 43-51.

Referring to FIG. 3, the reason why the value of the interrupt mask INT215 in the state control register is set to 0 is that in the virtual machine system environment, external interrupts are always accepted while the VM is running. The reason why the value of the supervisor mode bit 8216 is set to O is for the DMM to detect a sensitive instruction issued from O8 of the VMF and perform simulation processing thereof. Here, a sensitive instruction is an instruction that changes the hardware state within a microprocessor, for example, the value of a state control register, and is also called a privileged instruction.

Figure 4 shows the VMM sensitive instruction that changes the value of the status control register issued from O8 of the VMF mentioned above.
shows the processing procedure when performing simulation processing, and FIG. 5 shows the dispatch processing 22 in FIG.
2 details are shown. In Figure 4, O8 of VMF
issues an instruction that changes the contents of the status register (
In process 220), as shown in process 221, the value is reflected in the register area 213 in the control block VML_IST205 for each VM, but is not reflected in the value of the actual state control register. Further, in the dispatch processing process 225 shown in FIG. 5, the value of the interrupt mask INT225 of the state control register is set to 0 so that all external interrupts are always accepted.

For the above processing, the VMM processing program requires 500
It will run for ~600 steps, and this running time will become the overhead of VMM.

Next, V
Clarify the overhead of MM. FIG. 6 shows the processing flow of the VMM 502 when an external interrupt occurs.

In a microprocessor-based virtual computer system, when an interrupt condition is met, control is transferred to a processing program registered in the actual vector table 210 in the main memory 200 in FIG. The VMM processing program shown in the flowchart of FIG. 6 is one of the interrupt processing programs. The details of the interrupt processing procedure and the vector table are described in the previously disclosed article in Computer Vol. 12, pages 43-51.

Referring to FIG. 6, in the external interrupt processing program of the VMM 502, after determining whether or not it is an emergency interrupt in determination processing 226, in processing 227, the control block VML I 5T 205 of the VM corresponding to the interrupt is located.

In the determination process 228, the interrupt mask information of the state control register of the VM is checked from the register area 213 in the DMLI 5T 205. The format of the state control register copy in register area 213 is the same as that shown in FIG.

As a result of the determination, if the VM is interruptible, process 23
0 is executed to reflect the interrupt to the VM. on the other hand,
If interrupts are disabled, execute process 229 and suspend interrupts (
Pending) state. The interrupt pending state is displayed by creating the interrupt list 214 in FIG. 2.

Note that the interrupt list 214 stores the interrupt priority number, the state of the external device that caused the device number 1 interrupt, and the like.

The above processing is executed by the VMM processing program when an external interrupt occurs, and becomes overhead of the VMM.

[Purpose of the invention]

An object of the present invention is to realize a virtual computer system using a personal computer configured with a microprocessor, and to avoid the occurrence of an external interrupt as shown in FIG. An object of the present invention is to provide a control means for reducing the overhead of accompanying VMM(7) simulation processing.

[Summary of the invention]

To achieve the above object, the microprocessor-based interrupt control method of the present invention is provided with a plurality of state control registers, each state control register corresponding to an individual VM. Furthermore, it is provided with an actual state control register, and operates by moving fields other than the interrupt mask code in the state control register corresponding to the VM to the actual state control register when the VM is running. The interrupt mask code field of the actual state control register is characterized in that it includes means for setting a state value that always accepts external interrupts.

Therefore, in the operating state of the virtual machine system, external interrupt sources of all priority levels are accepted depending on the value of the interrupt mask code in the actual state control register. According to the processor-based interrupt control method, the value of the interrupt mask code of the corresponding VM set in the state control register of the corresponding VM is compared with the generated external interrupt number value, and if one interrupt operation is possible, the micro - A means for sending an interrupt number and an interrupt operation start signal to an instruction execution control unit in the processor, and if the result of the comparison means is that the interrupt operation suppression condition is satisfied, the instruction in the microprocessor is A feature of the present invention is that it includes means for sending an interrupt pending signal to the execution control section.

As a result, among the overheads caused by the VMM simulation processing, the overhead of the VMM simulation processing due to the occurrence of the external interrupt shown in FIG. 6 can be reduced.

[Embodiments of the invention]

The details of the present invention will be explained below using an example.

FIG. 7 shows a microprocessor CP to which the present invention is applied.
It shows the configuration of U. Reference numeral 110 in the figure is an interrupt control unit to which the virtual computer system microprocessor-based interrupt control method of the present invention is applied. Reference numeral 100 denotes a state register control unit, which includes a plurality of state control registers and means for selecting them based on the VM identifier.

The interrupt control unit 110 of the present invention receives the actual interrupt mask code value via the signal line Ω5 from the status register control unit 100, and the status control register corresponding to the running VM via the signal line Q6. The value of the interrupt mask code (this is referred to as a virtual interrupt mask code) and the external interrupt number are input from the external circuit via the signal line group f161.

The interrupt control unit 110 determines whether the generated external interrupt is executed by the microprocessor CPU based on the above input signal group.
If the interrupt number can be accepted, the interrupt number is set on the signal line Q20, the interrupt operation start signal is set on the signal line fi21, and the signals are sent to the instruction execution control unit 115.

First, the configuration and operation of the interrupt control unit 110 that implements the virtual computer system microprocessor-based interrupt control method of the present invention will be explained in detail using FIG. Using the figures from Figure 9 onwards,
Microprocessor CPU operation and microprocessor
The configuration and operation of a computer system using a processor CPU will be explained.

FIG. 8 shows the configuration of the microprocessor-based interrupt control system of the present invention, and shows the interrupt control section 110 of FIG. 7 in more detail. (SEL), 22.23 is a comparator. Reference numeral 24 is a highest priority value generation circuit, which generates a value of 7 in this embodiment. Reference numeral 25 is an AND circuit, 2
6 is an OR circuit.

27 is a gate circuit.

From the status register control unit 100 in FIG.
5, the value of the interrupt mask code (INT) in the real state control register, and the value of the interrupt mask code (V
INT) and information indicating the current operating state of the microprocessor are sent to the interrupt control unit 110 via the signal line fi41. Here, the operating state information of the microprocessor is information that distinguishes between the operating state of the real computer and the operating state of the virtual computer, and is also called the V bit, that is, the value of the V bit is '0'
(If the value of the signal line Ω41 is '0', it indicates the operating state of the real computer, and if the value is '1', it indicates the operating state of the virtual computer.

If the value of the V bit is '0', the selector 21 selects the value of the signal line a5, that is, the value of INT, and the comparator 2
This is one of the two inputs. On the other hand, if the value of the V bit is '1', the value of the signal line a6, that is, the value of VINT, is selected and used as one input of the comparator 22.

The value of the interrupt signal when one interrupt factor occurs is input to the other side of the comparator 22 via the signal line Q61.

Note that the value of the signal line fi61 is determined by the comparator 23. Gate circuit 2
It was also sent out on 7th.

The comparator 22 compares the interrupt number and the value of the interrupt mask code when the interrupt factor occurs. As a result of the comparison, if the value of the interrupt signal when the interrupt factor occurs is less than the value of the interrupt mask code, the value of the signal line Ω25 is set to '1' and becomes one input of the AND circuit 25. On the other hand, if the value of the interrupt number is greater than the value of the interrupt mask code, it means that the interrupt operation activation condition has been met, and the signal line Q
26 is set to '1', and the value is passed through the OR circuit 26 and the signal line Q21 to the instruction execution control unit 11 in FIG.
5 to report that the interrupt operation has started. At this time, the 1 interrupt number is input to the gate circuit 27, and the signal line Q21
When the value becomes '1', the gate circuit 27 is opened. As a result, the interrupt number is sent to the instruction execution control unit 115 via the signal line f120.

Furthermore, the comparator 23 operates in parallel with the operation of the comparator 22. The comparator 23 checks whether the interrupt number sent via the signal line Q61 at the time of occurrence of the interrupt factor is the highest priority interrupt. Here, the highest priority interrupt is one that occurs regardless of the value of the interrupt mask code in the status control register, and in this embodiment, the signal line group Q61 consists of three lines. When the value of the interrupt number is 7, it becomes the highest priority interrupt. therefore,
The highest priority value generation circuit 24 generates a value of 7. Note that this value can be changed.

As a result of the comparison in comparator 23, if the value of interrupt number 1 does not match the value of the highest priority value, the value of signal line Q27 becomes '1'.
' and becomes one input of the AND circuit 25. The signal resulting from the comparator 22 described above is input to the other side of the AND circuit 25, and is 11' when the interrupt number is less than or equal to the value of the interrupt mask code. Therefore, the output signal of the AND circuit 25 becomes an interrupt pending signal,
It is reported to the instruction execution control unit 115 via the signal line Q22.

As a result of the comparison by the comparator 23, if the interrupt number matches the highest priority value, the interrupt operation is forcibly activated. After passing through the OR circuit 26 via the signal line Q2B, this is reported to the instruction execution control unit 115 via the signal line Q21. Note that, as a matter of course, the interrupt number is also sent out via the signal line Q20 as in the case described above.

As described above, when an external interrupt occurs, the means automatically compares and inspects the value of the interrupt mask code of the state control register of the running VM.

There is no need for the VMM to intervene, and the running overhead of the VMM can be reduced.

Now, the operation of the microprocessor CPU and the configuration and operation of a computer system using the microprocessor CPU will be explained using FIG. 7 and FIG. 9 and subsequent figures.

Referring again to FIG. 7, reference numeral 51 indicates an instruction register IR.
, 52 is an instruction decoding processing unit, 53 is an instruction control unit, 5
4 is a local storage in which a microprogram for processing instructions is stored. Reference numeral 55 indicates a plurality of address register files, and a group of registers on one plane corresponds to one VM. Reference numeral 56 indicates a plurality of data register files, and as in the case of reference numeral 55, a group of registers on one plane corresponds to one VM.

Reference numeral 57 is a control circuit that selects one plane corresponding to the VM according to the value of VMID 105 for the address register file 55 and data register file 56, and 58 is a register number specified by each instruction of the program. This is a control circuit that selects an entry corresponding to a register number in one plane selected from register files 55 and 56 in response to. Reference numeral 59 is an instruction address register.
Register: IAR) and 1. m(7)I
AR59 exists for VM. In addition, IAR59
Program Count
, er).

60 is a temporary holding register T-Reg, 61 is an arithmetic unit ALU, 62 is a shift arithmetic unit, 63 is a multiplexer MPX, 64 is a selector, 65 is a data holding register DR, 66 is an address value holding register ADR, and 67 is an address value holding register ADR. This is a control signal processing circuit.

Signal line Q51 is a 32-bit wide internal data bus. The signal line Q52 indicates the state of the microprocessor CPU, for example, whether it is in VM mode or not, whether it is in supervisor mode or user mode,
Furthermore, the value of VMID 105 and the like are output. In addition,
A part of the value of the state control register in the state register control section [°00 is outputted from the microprocessor CPU via the signal line Q53. Here, among the signal line groups in FIG. 7, the signal line group indicated by double arrows means the main input/output signal line group from the microprocessor CPU.

Signal line Q54 is a 24-bit wide address bus sent from the microprocessor CPU, and signal line Q55 is a 16-bit wide or 32-bit wide address bus for exchanging data with memory devices and input/output devices. It is a data bus. Signal lines Q56 to Q59 are control signals sent from the microprocessor CPU to each device making up the personal computer system, signal line R60 is a response signal from each device, and signal line 861 is a signal sent from each device to the microprocessor CPU. This is a signal line that transmits an interrupt signal when exciting an external interrupt.

Next, using FIG. 7, we will explain the outline of the operation of each unit when the instruction sequence existing in the main memory is executed sequentially, and then explain the operation of the status register control unit 100 and interrupt control unit 110 of the present invention. The operation will be explained in more detail using FIGS. 9 and 10.

The instruction control unit 53 reads an instruction string from the memory based on the value indicated by the IAR selected by the circuit 57 from the program counter IAR 59 and regards that value as the memory address of the next instruction to be executed. try.

The IAR value selected from IAR59 is MPX63
is held in the ADR66 via the address bus 1115.
4 is sent on. At this time, signal line Q56. It also sends out an auxiliary control signal via Q57. For example, when the bit width of data bus Q55 is 16 bits I-, the signal on signal line ff56 is 1', which means 16 bits 1 to the lower 8 bits.
It means 1～, the signal of signal line Ω57 is 111 and 1
For example, it means the upper 8 bits out of 6 bits. Note that in the case of reading an instruction, the signal line Q56. The value of Q57 is 11. , and requests 16-bit data. These commands are sent from the command control unit 53 to the signal line group Q6.
2 to the instruction execution control unit 115, and is further transmitted to the control signal processing circuit 67 via the signal line group Q63, and the circuit 67 generates signals on the control signal lines Q56 to Q59.

Since this is the process of reading data from the memory, the value of the R/W signal on the signal line Q58 is 1'. Next, the signal on the signal line Q59 is set to logic '1' for a certain period of time.
Keep it. Here, the main memory control device (Memor
y Control Unit, :MCU) is the signal line Q
52. Depending on the values of signals Q53 and 256-Q59, desired instruction data is retrieved from the main memory and sent to data bus Q55. Note that the data bus Q55 has a bidirectional bus structure.

Next, the main memory control unit MCU (the connection relationship with the MCU will be described later) sets the signal 9060 to 11. This signal is a response signal to the request signal on signal line f159. Microprocessor CPU is signal line Q60
When the signal becomes 1', the data on data bus Q55 is held in DR65, and then the instruction data on DR65 is transferred to MPX.
63, instruction register I via internal data bus Q51
Hold in R5I.

The instruction data held in the IR5] is decoded by the instruction decode processing section 52. Instruction data (not shown) is an instruction field and a register field.

It consists of an operand field, examines the instruction field to determine the type of instruction, and sends information necessary for processing the instruction to the instruction control unit 53 via the signal line Q64. Note that an example of the command data format is the previously disclosed E d
It is described in the paper by Ward S. Schritt, er et al.

The instruction control unit 53 communicates with the processing unit 52 via the signal line Q65 in order to calculate the effective memory address and prepare the instruction data necessary for it, and downloads the microprogram necessary for the operation from the local storage 54. prepare. Also, IAR59 will be corrected.

Next, the instruction execution control unit 115 performs calculation control. For example, in the case of an addition operation, the address is
Register file 55 or data register
One plane in file 56 is selected and register file control 58 selects the address register, data
Select one of the registers, take out the values of the J registers corresponding to the register number specified by the instruction among the selected register group, pass through the T-Reg 60 and the selector 64, and then retrieve the values from one of the ALUs 61. It becomes input. On the other hand, the memory address data is obtained by setting the memory address value in the ADR66 and issuing a request to the MCU in the same way as when reading the instruction data mentioned above.
63 and becomes one input of the ALU 61. Next, A.L.
An operation is performed by U61, and the operation result is stored in the address register file 55 or data register file 56 again.
Store it in either.

The above is the general instruction processing order. These instructions are also commonly called non-privileged instructions. On the other hand, C.P.
Sensitive instructions that change the state of U, such as instructions that change the contents of the state control register, are controlled by the jrlA register control section of the present invention. Figure 7 shows the details of this operation.

This will be explained using FIG.

First, the outline of the state control register changing process will be explained using FIG. 7, and then the main configuration and operation in the control section 100 will be explained in detail using FIG. 9.

When executing an instruction to change the value of the field of the state control register shown in FIG. 3, for example INT215, the change data is transmitted via signal line Q1.

A reference/update discrimination signal is sent to the status register control unit 100 via the signal line Q2. If the value of the signal on line 3 Q2 is 0', it means that the state control register is referenced, and 1'
If so, it means updating.

In addition to the change data described above, the signal line group Q2 also includes signal lines for transmitting other information, such as signal lines for setting the operating mode to VM mode (indicated by Qll in FIG. 9).
Also includes. Further, the signal line Ql is capable of bidirectional data transfer, and when the contents of the status control register are referenced, the contents of the status control register are sent to the internal bus Q51. The state register control unit 100 also receives a VMID register 1 representing identification information of the running VM.
The contents of 05 are also sent out.

The state control register control unit 100 locates the state control register corresponding to the number indicated by the VMID register 105 from among the plurality of state control registers. Thereafter, the state control register operates based on the value of the signal on the signal line Q2. For example, signal! If the value of the signal 1AQ2 is 0', the contents of the located state control register are sent onto the internal bus Q51 via the signal line Q1.

On the other hand, if the value of the signal on the signal line Q2 is 1', it means that the value of the status control register is updated, and the update data sent via the signal line Q1 is matched to the contents of the VMID register 105. Store in the located state control register.

After storing the updated data in the located state control register, an operation is started to reflect the value in the actual state control register. That is, if it is the virtual machine operation mode (VM mode), the S bit 216 and INT mask 216 shown in FIG. 3 are forcibly set to 0 and set in the actual state control register. This is the instruction execution control unit 115
．． And for the interrupt control unit 110, it is displayed that when the VM mode is in the user mode, it will accept any external interrupts.

The actual state control register value is sent to the instruction execution control unit 115 via the signal line Q4. Note that the VM mode value is output via the signal line Q4L, 167. Note that the signal on the signal line Q41 is also sent to the instruction execution control section 115.

Next, using FIG. 9, state control register control section 10
The configuration and operation of 0 will be explained in detail. FIG. 9 shows in more detail the portions of the state control register control unit lOO shown in FIG. 7 that are related to the present invention. Among the symbols in the figure, those having the same meaning as in FIG. 7 are referred to by the same symbols. In FIG. 9, reference numeral 1 is a state control register file that stores a plurality of state control registers.

The formation of the individual state control registers is as shown in FIG. Reference numeral 2 is a decoder, 3 is a holding register, 4 is a comparator, 5 is a zero generation circuit, 6 is a VM momo indicator, 7 is an AND circuit, and 8 is an amplifier circuit, which also has the ability to invert a signal. 9 is an OR circuit.

10 is a selection circuit SEL, 11.12 is a zero generation circuit, 1
3 is a selection circuit SEL, and 14 is an actual state control register.

The contents of VMID105 are input to decoder 2 and comparator 4 via line Q3.If the value of VMTD105 is O, it indicates whether the VMM is operating in the virtual machine operating mode or not. Alternatively, it refers to the operating mode of an actual computer.

The decoder 2 selects one state control register from the state control register file 1 corresponding to the value of VMrDI05. The distinction between reference and update of the contents of the status control register is input from the instruction execution control unit 115 to the write/read control circuit 15 via the signal line Q2, and the updated data is input via the signal line 21 via the internal bus Q51. is entered. Note that the set/reset control signal to the VM momo indicator 6 is sent from the instruction execution control section 115.

The control circuit 15 performs processing on the state control register selected from the state control register file 1 based on the contents of the signal line Q2. In other words, if the value of the signal on signal line 0.2 is 'O'', it means that the state control register is being referenced, and the contents of the selected state control register are output to holding register 3, and the value is transferred to signal line 0.2. ff12, and again via the line Ql, returning to the internal bus Q51.

On the other hand, if the value of the signal on the signal line Q2 is 'bi', it means that the value of the state control register is updated, and the update is sent to the selected state control register via the signal line Q1. Write data to the state $ control register via line ff13. Then the state control register
The modified contents of the state control register in file 1 are output to holding register 3. The format of the holding register 3 is the same as that of the state control register shown in FIG.

Next, an operation is performed to reflect the value of the state control register held in the holding register 3 to the actual state control register.

This operation is performed regardless of whether the status control register is referenced or updated.

The criteria for reflecting a value to the actual state control register 14 are as follows.

(1) When the operation mode is the real computer operation mode, that is, the value of indicator 6 is 0', or even if it is the virtual computer operation mode, when it is VMM operation (when the value of VMID105 is 0), the state The value of the selected state control register in the control register file 3 is set as is in the actual state control register 14.

(2) V that is the operating mode of the virtual machine and is running
If M is not a VMM, force the S mode bit 216 and interrupt mask INT 215 to 0 in the selected state control register in state control register file 3 to always accept interrupts from external devices. 6. First, we will explain the operation in case (1) above.

In the case of the actual computer operation mode, the value of indicator 6 is 0'.
The signal passes through the inverting amplifier 8, and the signal on the output line +214 of the OR circuit 9 becomes 1'. Furthermore, even in the virtual machine operation mode, when the VMM is operating, that is, when the value of the VMrD register 105 is 0', the @Q15 signal is set to 'I' by the result of the comparator 4.
becomes.

As a result, the signal on the output signal line Q14 of the OR circuit 9 is also 1'
becomes. Therefore, the selector 5EL10 selects the signal line Q
Select 16 signals. Selector 5EL136 signal line Q
Select signal 6. These are the S bits 18 . of the real state control register 14, respectively. Set to INT bit 19. Note that other data in the state S control register are directly set in the actual state control register via the signal aρ17.

Next, the operation (2) above will be explained.

The value of the status indicator 6 becomes 1', and the output signal thereof is passed through the amplifier circuit 8 and becomes the negative input of the AND circuit 7. Also, the result of comparator 4 is 0 because the VM is running.
As a result, the signal on signal line Q18 becomes 1'. Therefore, the signal on the output signal line Q19 of the AND circuit 7 becomes 1'.

When the signal on signal line Q19 becomes 1', selector 5EL
IO selects the output signal of the zero generation circuit 11. Also,
The selector 13 also selects the output signal of the zero generation circuit 12. As a result, the S bit 18 of the actual state control register 14
The value of 1 interrupt mask lNT19 is forcibly set to O. Therefore, this is the operating mode of the virtual computer system, and while the VM is running, it is always in a state where it can accept interrupts from external devices.

Note that the contents of the actual state control register 14 are sent to the instruction execution control section 115, and the contents of the interrupt mask lNT19 are sent to the interrupt control section 110. The value of the operating state indicator 6 is sent to the instruction execution control section 115, the interrupt control section 110, and the control signal processing circuit 67. In addition, the interrupt mask (referred to as VINT) of the state control register corresponding to the VM selected from the state control register file 1 is connected to the signal line ℃6.
It is sent to the interrupt control unit 11 via.

Referring again to FIG. 7, the interrupt control unit 110 outputs the interrupt level number reported from the external device via the signal line Q61 and the value of the signal aQ5 which sends the value of the interrupt mask lNT19 of the actual status register 14. Or signal line 126
(V I NT). The value of the signal line to be compared is determined by the value of the output signal line U41 of V bit 6, as described above. If an interrupt from an external device is possible, the signal on the signal line Q21 is set to 1', the interrupt number is sent to the signal line Q20, and the instruction execution control unit 115
Report interrupts to . If interrupts cannot be accepted, set the signal on signal line Q22 to 1',
Reports pending interrupts.

To check whether or not an interrupt from an external device is possible, check the value of the signal line Q61 (interrupt level numbers from O to 7 in the example of FIG. 7) and the value of the signal line Q5 (interrupt mask number:
0 to 7), and if the interrupt level number is larger than the interrupt mask number, interrupts from external devices are always accepted.

FIG. 10 is a block diagram of a personal computer system constructed using the microprocessor method for virtual computer systems of the present invention.

PC (Personal Ca) according to this embodiment
301 is a microprocessor CPU equipped with the control method of the present invention, 302 is a clock generator CLOCK, 303 is an interrupt priority control circuit, and 304 is the configuration of the VMS shown in FIG. Memory RAM 305 in which example control programs VMM 502 and 0S 506 and user program 515 are stored
is the control unit of the RAM 304 (Memory Control
rolUnit: MCU),
306 is a disk control circuit, 307 is a magnetic disk file, 308 is a printer control circuit, 309 is a printer device, 310 is a display/keyboard control circuit, 311 is a display device and keyboard, 312 is a communication control circuit, 313 is communication It is a circuit device. In the configuration of FIG. 10, the printer device 309 and its control unit 308
, and the communication circuit device 1313 and its control unit 312 are not essential components.

The connection between the microprocessor CPU30L and each component is a 24-bit address bus Q31.16 bits, or a 32-bit data bus Q32, and a
301, a function line bus Q52 indicating the access form to the memory RAM 304, and control signal line groups Q56 to 1259. Q53. A response signal Q60 from each part is connected to an interrupt line bus μ61 from an interrupt priority control circuit 303.

The interrupt priority control circuit 303 prioritizes interrupt requests from each section and assigns them an interrupt level number (0 to 7).
create. This interrupt level number is sent to signal line group Q61.

〔Effect of the invention〕

According to the present invention, as the value of the interrupt mask code of the microprocessor CPU, the value of the interrupt mask code of the actual state control register is used depending on the operation mode of the microprocessor, or the value of the interrupt mask code provided for each VM is used. Since the value of the interrupt mask code in the virtual state control register corresponding to the running VM is used, when the virtual machine system is operating, the external interrupt number is the value of the interrupt mask code in the virtual state control register corresponding to the running VM. compared to the value. As a result, every time an external interrupt occurs, the VM
The overhead of simulation processing due to the intervention of M can be reduced, and the processing performance in the virtual computer system can be improved.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the concept of a normal virtual computer system, Figure 2 is a diagram showing the relationship between the main memory allocation method and VMJI control blocks, and Figure 3 is a diagram showing the formation of state control registers. Figure 4 is a diagram showing the processing procedure when the VMM performs simulation processing of a sensitive instruction that changes the value of the status register issued from the O8 under the VM in the environment of a virtual computer system. 6 is a diagram showing the operation flow of the VMM when an external interrupt occurs, and FIG. 7 is a diagram showing details of the dispatch processing 222 shown in FIG. A diagram showing the configuration of the microprocessor, FIG. 8 a diagram showing details of the interrupt control section, FIG. 9 a diagram showing details of the status register control section, and FIG. 10 a diagram for the virtual computer system of the present invention. 1 is a diagram showing the configuration of a personal computer system including a microprocessor. In FIG. 8, 21: selector, 22, 23: comparator, 24: highest priority value generation circuit, 25: AND circuit,
26: OR circuit, 27: Gate circuit, O5: Signal line that transmits the value of the interrupt mask code in the real state control register, O6: Signal that transmits the value of the interrupt mask code in the virtual state control register. line, O41: signal line that transmits the operating state of the virtual computer system, O61: signal line that transmits the interrupt number when an external interrupt occurs, O20: signal line that transmits the interrupt number, O21: transmits the interrupt operation activation signal Signal line O22: A signal line that transmits an interrupt pending signal. In addition, in FIG. 9, 1: state control register file, 2: decoder, 3: holding register, 4: comparator, 5
: Zero generator, 6: VM mode indicator, 7: AND circuit, 8: Amplifier circuit, 9: OR circuit, 10: Selector, 11
, 12: zero generation circuit, 13: selector, 14: actual state control register, 15: write/read control circuit. Figure 1 Figure 2 Figure 48 Figure 2 Figure 7 Zoro 3rd area vJNT 1M7 Go to qth 〃6

Claims (1)

[Claims] 1. In an interrupt control method for a microprocessor in which a plurality of virtual machines are running, whether or not to permit an external interrupt factor in response to an interrupt number indicating the occurrence of an interrupt factor from an external device. means for storing a plurality of interrupt mask codes corresponding to the plurality of virtual machines for comparing and determining the interrupt mask codes; and a mask corresponding to the currently running virtual machine from among the plurality of interrupt mask code storage groups. means for selecting a code; means for comparing the selected interrupt mask code with an interrupt number from an external device; 1. An interrupt control method for a microprocessor, comprising: and means for reporting an interrupt operation activation command. 2. In item 1, the selection means includes a virtual machine operation mode indicator and a running virtual machine identifier,
If the virtual machine operation mode indicator is displaying the operation of the real computer system, select the storage information of the actual interrupt mask code, and the virtual machine operation mode indicator should display the operation of the virtual computer system. 1. An interrupt control method for a mask processor, comprising means for selecting storage information of an interrupt mask code corresponding to the value of the virtual machine identifier, if the virtual machine identifier has a value. 3. In paragraph 1, the comparison means issues a command signal to excite the activation of the interrupt operation when the interrupt number from the external device is smaller than the value of the selected mask code, and when the interrupt number from the external device is smaller than the value of the selected mask code, 2. The microprocessor interrupt control system according to claim 1, further comprising means for issuing a command to suspend the interrupt in the case of .