JPS6120446A - Digital data reproducing circuit - Google Patents

Abstract

PURPOSE:To realize the conversion to non-adjustment, also IC, a small size, and also one chip in all digital systems, by inputting an input signal train quantized at a higher speed of two times of a transmission rate, to a phase interpolating circuit and a phase detecting circuit, and controlling said phase interpolating circuit and a clock selecting circuit. CONSTITUTION:A signal train quantized a digital information signal transmitted by F.b.p.s as an input signal, by two times of a transmission rate is inputted to a phase interpolating circuit 8 and a phase detecting circuit 10. The phase detecting circuit 10 detects phase information from the input signal and outputs it to a control circuit 9. The control circuit controls a selecting circuit 11 and outputs a timing clock to a signal decoding circuit 12. The phase interpolating circuit 8 receives a control signal from the control circuit 9, executes an optimum interpolation, outputs it to a signal decoding circuit 11, and it is decoded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital data reproducing circuit used for reproducing digital data in a digital information signal receiver.

2. Description of the Related Art Structures and Their Problems In recent years, services in which a digital information signal is multiplexed with a television signal and transmitted as seen in teletext broadcasting, etc., are becoming popular. In line with this trend, the digital signal processing section for reproducing digital data is being made into an IC, more compact, and even more integrated into a single chip. Hereinafter, a digital data reproducing circuit of a conventional digital information signal receiver for teletext broadcasting will be described as an example with reference to the drawings.

In Figure 1, 1 is a signal extraction circuit, 2 is a multiplier circuit,
3Vi crystal oscillation circuit, 4 is an amplifier circuit, 6Vi waveform shaping circuit, 6Vi slice circuit, and 7 is a signal decoding circuit. T
An input terminal to which the 1H input signal is applied, and T2 is an output terminal to which the reproduced output is applied.

The operation of the digital data reproducing circuit configured as described above will be explained below.

A signal extraction circuit 1 extracts a clock run-in signal placed at the beginning of the signal for sampling clock reproduction in synchronization with the data signal in the input signal, and inputs this clock run-in signal to a multiplier circuit 2. The frequency is doubled and input to the crystal oscillation circuit 3 to excite the crystal.

The oscillation output from the crystal i-oscillation circuit 3 is amplified by the amplifier circuit 4,
The waveform shaping circuit 6 shapes the waveform and outputs it to the signal decoding circuit 7 as a sampling clock.

The input signal is converted into a binary signal by the slice circuit 6 and output to the signal decoding circuit 7, and is output as a reproduced signal at the timing of the sampling clock from the waveform shaping circuit 6.

However, the above configuration requires adjustment of the temperature characteristics of analog elements such as the multiplier circuit, the capacitors and coils of the crystal oscillation circuit, and is affected by aging. On the other hand, we are using ICs and miniaturizing analog elements instead of using them.
Furthermore, it is difficult to integrate into a single chip because of the high cost.

Another problem is that the crystal must be excited in several cycles of the clock run-in signal, and the oscillation output must be maintained stably for the 1H period of the television signal.

Purpose of the Invention The purpose of the present invention is to use an all-digital method, no adjustment, and an integrated circuit.
It is an object of the present invention to provide a digital data reproducing circuit that can be reduced in size, size, and even integrated into a single chip.

Composition of the Invention The digital data reproducing circuit according to the present invention inputs an input signal sequence quantized at a rate higher than twice the transmission rate to a phase interpolation circuit and a phase detection circuit, and uses the output of the phase detection circuit to input the input signal sequence to the phase interpolation circuit. and a control circuit for controlling a clock selection circuit, and a decoding circuit for decoding the output of the phase interpolation circuit at the clock timing from the clock selection circuit.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a digital data reproducing circuit in one embodiment of the present invention. In Figure 2, 8 is a phase interpolation circuit, a 9-digit control circuit, a phase detection circuit for detecting 10-Vi phase information, an 11-Vi black selection circuit, a 12-digit signal decoding circuit, which are T3 input terminals, and T4 is an output terminal. be.

Phase information is detected from the input signal and output to the control circuit 9. The control circuit controls the clock selection circuit 11 to output a timing clock to the signal decoding circuit 12. The phase interpolation circuit receives a control signal from the control circuit 9, performs optimal interpolation, and outputs it to the signal decoding circuit 11, where it is decoded.

FIG. 3 is a circuit diagram showing a specific configuration of the phase interpolation circuit 8. As shown in FIG. In Fig. 3, 13 is a delay circuit, 14.15.1
6 is a changeover switch, 1γ.

18 is a multiplier outside the magnification, and 19 is an adder.

FIG. 4 is a conceptual diagram showing the interpolation state of the phase interpolation circuit. The switch is activated by the control signal from the control circuit 9. 7chi 14,1
5.16 to switch two adjacent signals in the input signal string to the fourth
Interpolation is performed using the signal ratios shown in A2B and B of the figure. In the same figure, A shows a state in which no interpolation is performed, a state in which two adjacent signals of the input signal string are interpolated at a signal ratio of 1:2, and a state in C shows a state in which interpolation is performed at a signal ratio of 1:1.
This shows a state in which interpolation is performed with a signal ratio of 1.

FIG. 6 is a circuit diagram showing a specific configuration of the phase detection circuit 1o. In Figure 6, 2). 211-i delay circuit, 2
2.23 is an absolute value circuit, 24-digit EX-OR gate, 25
, 26.27 are subtracters, 28 are switches, 29
．． 30 are multipliers each having a magnification of V4+rod.

In the digital data reproducing circuit of this embodiment configured as described above, there is a signal at the beginning of the signal to determine the sampling timing of the data signal. The operation when a digital information signal in which a check run-in signal is arranged is input will be described below.

A signal string obtained by quantizing a digital information signal transmitted in F, b, p, and s at twice the transmission speed is input as an input signal. FIG. 6 shows four sampling points 2L, bla/, and b' during one cycle of the clock run-in signal having a frequency component of F/2 Hz at this time. These a, b, a', and b' have a phase difference of 900 with each other. C is an ideal sampling point, and the phase difference between C and a and b is ψ.

ψ2 is phase jitter.

From now on, a and b will also be used as sampling data.

In FIG. 6, the phase detection circuit 10 uses an absolute value circuit 22 to determine the absolute value of the input signal, and uses an EX-OR gate 24 to output code information of two sampling data a and b to the control circuit 9. A subtracter 25 takes the difference 1l-1bl between the absolute values 1al and lbl of a and b, and outputs the result to the control circuit 9 as magnitude information. The smaller of Ial and lbl is selected by switching the switch 28 using the MSB of 1al-lbl. This smaller value and l+a+-1b 1
114, 1al-1b1. ! :Outputs the difference value from the smaller value to the control circuit 9.

The control circuit 9 determines the magnitude relationship and sign relationship between a and b.

FIG. 7 shows this state. The table below shows the magnitude relationship and sign relationship of the states shown in FIG.

Furthermore, the size relationship is divided into three stages. FIG. 8 shows this state. The magnitude relational expression at this time is shown in the table below.

In FIG. 3, the magnitude relational expressions (1), (2), (3) are calculated by the control signals from the 8 phase interpolation circuits and the control circuit 9.
When the conditions are satisfied, the switches 14, 15, and 16 are switched so that the interpolation shown in FIG. 4 is performed. In this way, when the magnitude relation is expressed by magnitude relational expression 1, the switch is changed to output the data with the larger absolute value, and when the magnitude relational expression 2) is present, the switch is changed to output the data with the larger absolute value. The signals are added at a signal ratio of 1:V2, and when the magnitude relational expression 3 is satisfied, the switch is changed so that the signal ratio is added at a signal ratio of 1:1 as shown in FIG. 4C. Thereby, the phase jitter can be interpolated from two adjacent sampling data and the phase jitter can be further improved.

Effects of the Invention As is clear from the above description, the present invention is composed of a phase interpolation circuit, nine phase detection circuits, a control circuit, a clock selection circuit, and a signal decoding circuit, so phase jitter can be detected from sampling data, Correct the phase in a more optimal direction. In addition, since it is an all-digital system, it can be miniaturized without any adjustment, and the IC
Further, it becomes possible to integrate into a single chip.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional digital data reproducing circuit, Fig. 2 is a block diagram of a digital data reproducing circuit according to an embodiment of the present invention, Fig. 3 is a circuit diagram of a phase interpolation circuit, and Fig. 4 is a block diagram of an interpolation circuit. A conceptual diagram showing the state, Fig. 6 is a circuit diagram of the phase detection circuit, Fig. 6 is a diagram showing the sampling points of one cycle of the clock run-in signal, and Fig. 7 is a conceptual diagram showing the magnitude relationship and sign relationship of sampling data. , FIG. 8 is a conceptual diagram showing the magnitude relationship of the interpolation determination. 13.2). 21...Delay circuit, 14,15°16.28...Switch, 17.18,29.
30... Multiplier, 19... Adder, 2
2.23... Absolute value circuit, 24-=4 X-O
R gate, 25, 26° 27...subtractor. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 4 Figure 5 Figure 8

Claims (6)

[Claims] (1) A phase detection circuit that receives an input signal sequence sampled and quantized at a sampling frequency higher than the transmission speed and detects phase information; a phase interpolation circuit that receives the input signal sequence and performs interpolation; and the phase detection circuit. a control circuit that controls the phase interpolation circuit and the clock selection circuit by the output of the
and a digital data reproducing circuit comprising a decoding circuit that decodes the output of the phase interpolation circuit at clock timing from the clock selection circuit. (2) The phase interpolation circuit includes a first multiplier that inputs the quantized input signal sequence, a delay circuit that delays the signal by one clock, and a second multiplier that inputs the output of the delay circuit. 2. The digital data reproducing circuit according to claim 1, further comprising: an adder circuit for adding the outputs of the first and second multipliers. (3) The phase interpolation circuit detects two adjacent input signal sequences sampled and quantized at a sampling frequency higher than the transmission speed.
One of the signals is input into a first multiplier with a coefficient of 1 or 1/2, and the other of the two signals is input into a second multiplier with a coefficient of 1 or 1/2 or 0. , said first,
and an adder circuit for adding the outputs of the second multiplier, and the coefficients of the first and second multipliers are selected by the output from the control circuit. The digital data reproducing circuit described in . (4) The phase detection circuit performs phase detection by obtaining phase information from the magnitude relationship between two signals in the clock line signal of the input signal sequence sampled and quantized at a sampling frequency higher than the transmission speed. The digital data reproducing circuit according to item 1 or 2 or 3. (5) A digital data reproducing circuit according to claim 1, 2, or 3, in which the sampling frequency is twice the transmission speed. (6) The phase detection circuit includes a multiplication circuit that multiplies the signs of two adjacent signals in the clock line signal of the input signal sequence sampled and quantized at a sampling frequency twice the transmission speed, and the absolute value of the two signals. a first absolute value circuit that calculates the absolute value of the difference between the absolute values of each of the two signals, and a first selection that selects a smaller value from among the absolute values of each of the two signals. a first comparison circuit that compares the magnitude of 1/4 of the output of the second absolute value circuit and the output of the first selection circuit; a second comparator circuit that compares the output of the multiplier circuit with 1/2 of the output of the first selection circuit;
3. A digital data reproducing circuit according to claim 1, wherein the digital data reproducing circuit outputs magnitude information of the comparison circuit to a control circuit.