JPS61194566A - Vector data reference control system - Google Patents

Abstract

PURPOSE:To ensure dammy processing of a successive command without stopping an arithmatic unit when the order of vector data access is not assured between linked commands by setting a flag for each bank of a vector register. CONSTITUTION:A write address of a leading command in an address register 1-1 and a read address of the successive command in an address register 3-0 are compared in a coincidence circuit 5, which outputs 1 in the event of coincidence and 0 in the event of mismatch. When the circuit 5 outputs 0, an inverter 7 inverts 0 to 1 and a read-out valid flag 4-0 is set to 'on' through an OR circuit 8. Although the write address of the leading command and the read address of the successive command coincide, the flag 4-0 is set either to 'on' or 'off' according to an on-off state of a write valid flag 2-1. Thus, when the order of access can not be assured, the dammy processing of the successive commandtion can be performed.

Description

[Detailed Description of the Invention] [Summary] When the vector data of a succeeding vector instruction is linked to the vector data of a preceding instruction, even if the vector and data of the succeeding instruction are interrupted, other unlinked independent instructions so that it doesn't stop running.

A flag is placed for each memory bank to indicate the validity of the data, and subsequent instructions are executed when the flag is not valid.

Perform dummy processing without stopping execution.

[Industrial application field]

The present invention relates to a vector processing device, and particularly to a control method for parallel execution of instructions that refer to vector data.

[Conventional technology]

Modern vector processing devices are equipped with multiple pipelines for addition, squaring, division, load/store, etc.
Executing multiple vector instructions in parallel “””,H,!,,j
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If there is a time limit for data usage and these instructions are in a so-called link relationship that requires processing in a predetermined order, the data □ can be used by executing the preceding instruction. Subsequent instructions cannot be executed in parallel until .

For example, the preceding instruction (assumed A) or the hector register VR
When data written in is read out by a subsequent instruction (referred to as B), if the writing of vector data to the vector register VR by instruction A is interrupted, the processing of instruction B must be stopped midway.

That is, the process is temporarily stopped until the writing into the VR by the instruction A is resumed.

To give a specific example, as shown in FIG.
AD, when instruction B is like ADD, the LOAD instruction is
Data is read from the main memory to the vector register, but if there is an access to the main memory from another device, such as a channel, it may conflict with the access for loading and the data may not be loaded continuously. be.

In such a case, conventionally, instead of stopping instruction B, the entire arithmetic unit that processes instruction B has been stopped. Therefore, other independent MUL'rI commands could not be processed during that time.

[Problem that the invention seeks to solve]

As described above, in the conventional method, when the access order of vector data cannot be guaranteed between linked instructions, the arithmetic unit is stopped, but as a result, it is also impossible to execute other unlinked arithmetic instructions. There was a problem that.

[Means for solving problems]

According to the present invention, when the access order of vector data cannot be guaranteed between linked instructions, dummy processing is performed on subsequent instructions without stopping the arithmetic unit.

Therefore, a flag is provided for each bank of vector registers to indicate the validity of vector data.

When the linked preceding instruction accesses data in that bank, it sets the flag to valid, and when the linked subsequent instruction accesses the bank with the flag enabled, it executes the original processing, and when it accesses the bank with the flag disabled, it sets the flag to valid. Control is performed so that dummy processing is executed when accessed.

[Effect]

Linked instructions perform parallel execution that guarantees the access order of vector data without stopping the arithmetic unit, so other unlinked instructions can execute processing using the arithmetic unit without interruption. can.

[★Example]

FIG. 3 shows an embodiment of the configuration of the vector register (R) in a pipelined vector processing device to which the present invention is applicable.

In FIG. 3, reference numeral 31 denotes vector registers VR, 32-0 to 32, which are composed of eight banks #0 to #7.
-7 is a writing side address register, 33 is a +1 adder, and 34 is an address input line.

35 is a selector, 36-0 to 36-7 are address registers on the read side, and 37 is a +1 adder.

38 represents an address input line, and 39 represents a selector SEL.

In banks #O to #7, elements of vector data are sequentially stored one by one in an interleaf format. One bank, No, O~No.

256 elements can be stored in 255 storage locations.

address registers 32-0 to 32-7;

A register that specifies the storage location @No in each bank and has an address for writing or reading an element.One address is input from 34 to 32-0 via selector 35, and is input every cycle. Shifts to the right, and when going from 32-7 to 32-0 again, +1
The adder 33 adds +1.

When the address for a new instruction is input from 34, the selector 35 selects whether to input the address by adding 1 to the address of the instruction already being processed.

The circuit portions 36-0 to 36-7, 37, 38, and 39 are mechanisms for reading out elements from each bank.
It performs the same operation as the write-side model described above.

Here, as illustrated in FIG. 4, the timing of accessing bank #0 is determined by the LOAD/5TORE
There is provided a Hank's Loso 1- which is defined separately from arithmetic instructions such as DD and MULT1.

In the illustrated example, for the LOAD/5TORE instruction.

K slots or L slots are assigned, while arithmetic instructions include E's, F2, El, or F3°F2. A slot of F is allocated.

The arithmetic instruction reads two operands from the vector register VR in slots F3 and F2.
, writes the operation result to the vector register VR in the slot. Furthermore, F3. F2. The same applies to the Fl slot.

For example, the LOAD command uses a slot.

ADD command is F3. F2. If we use slot E, when we focus on one bank, in the next cycle (F3) after writing with the LOAD instruction, we read the first operand of the ADD instruction.

Further, in the next cycle (F2), the second operand is read, and in the next cycle (El), the result of the ADD operation is written.

FIG. 5 shows the above operation in a timing diagram.

Next, based on the second invention, a valid signal means is provided on the write side of each bank of the vector register VR, and a means for generating a valid signal is provided on the read side of each bank of the vector register VR. establish.

FIG. 1 is a block diagram of a valid control circuit according to an embodiment of the present invention. For the sake of simplicity, the illustrated example is a case where the first operand is read from bank #0 through E3 slot.
Only the circuit that generates the valid signal of the first operand for the DD instruction is shown. Therefore, bank #
1 to #7. It should be considered that a similar circuit is provided for the second operand as well.

In FIG. 1, J-0 and 1-1 are address registers for writing to banks #O and #1, respectively;
2-O and 2-1 are respectively bank #0. The write valid flag indicates that valid data to write to #1 has arrived. 3-0 is for reading from bank #0. Address register 24-0 indicates that the data read from bank #0 is valid. 5 represents a coincidence circuit, 6 represents an AND circuit, and 7 represents an inverter 28 an OR circuit.

Here, when the write valid flag 2-1 is valid, the previous Niremen 1- is also in the vector register VR.
It should have been written in.

It can be determined that valid data has already been written to bank #0.

Therefore, when the contents of address registers -1 and 3-O are equal, when the LOAD and ADD instructions are linked and the VR addresses match, if the write valid flag 2-1 is ON, the address register 3
- The data read from the VR by 〇 is valid data.

Therefore, the read valid flag 4-0 is turned ON.

Further, when address registers 1-0 and 1-1 are not equal, the two instructions are not linked, so the read valid flag 4-0 is always ON.

In FIG. 1, circuit elements indicated by 5 to 8 are for realizing the above-mentioned logical operations. That is, the minus number circuit 5 is the write address of the preceding instruction in the address register 1-1.

Compares the read address of the subsequent instruction in address register 3-0, and if they match, the two instructions are linked and outputs "1"; if they do not match, "0" is output.
” is output.

- When the It circuit 5 outputs "o", that is, when the two instructions are not linked, the inverter 7 inverts "0" to "1", and reads it out via the OR circuit 8, valid flag 4-0. Set to ON (valid).

On the other hand, when the matching circuit 5 outputs "1".

The AND circuit 6 outputs "1" to the OR circuit 8 on the condition that the write valid flag 2-1, which indicates that the write data of the preceding instruction is valid, is turned on, and similarly turns on the read valid flag 4-0. Set.

Therefore, the read valid flag 4-0 is.

Even if the write address of the preceding instruction and the read address of the subsequent instruction match, the write valid flag 2-
If 1 is OFF (invalid), it is set to OFF (invalid).

Figure 6 shows that the writing of the preceding LOAD command is interrupted and the write valid flag is ON or O as shown by ○ or ×.
When the FF value is taken, the value of the read valid flag when reading the first operand by the subsequent ADD instruction (○
, ×) and the value of the write valid flag when writing the first result of the ADD operation (○
, x). Valid and invalid (○, ×) of each vector data.

It can be seen that the LOAD and ADD instructions are consistent. Further, in executing a MULTI instruction that is not linked to these LOAD and ADD instructions, the read valid flag is always turned ON.

When executing an ADD instruction, an operation result of a non-valid operand is not written to VR, and no exception handling is performed. That is, NOP (No 0PERATI ON)
processing or dummy processing.

〔Effect of the invention〕

According to the present invention, when an instruction that has a link relationship and an instruction that does not have a link relationship are executed in parallel, execution control of the instruction that has a link relationship does not affect the execution of the instruction that does not have a link relationship. , the processing can be completed quickly, and the processing efficiency of the vector processing device can be improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of a valid control circuit, Fig. 2 is an operation timing diagram of a conventional example, Fig. 3 is a block diagram of an embodiment of a vector register, and Fig. 4 is an explanatory diagram of an example of a bank slot. FIG. 5 is a timing diagram of an example of arithmetic operation, and FIG. 6 is a timing diagram of an example of operation according to the present invention. In Figure 1, 1-0.1-1.3-0 is an address register, 2-0.2-1 is a write valid flag, and 4
-0 is a read valid flag. 5 is a matching circuit, 6 is an AND gate, 7 is an inverter, 8
represents an OR gate.

Claims (1)

[Claims] In a vector processing device having a vector register interleaved with a plurality of banks, a write address to the vector register by a preceding instruction and a read address from the vector register by a subsequent instruction are compared for each of the plurality of banks. means for detecting a linked instruction relationship based on the coincidence thereof, and means for displaying validity of read data when the write data by the preceding instruction is valid and the linked instruction relationship is detected, The above-mentioned subsequent instruction executes the original processing when the validity is displayed for the read data of the accessed bank, and on the other hand, executes the dummy processing when the validity is not displayed. control method.