JPS61188927A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To release thermal stress resulting from thermal expansion coefficient difference and obtain a high quality compound semiconductor device by forming an intermediate layer which alleviates mismatching of lattice constant between a Si substrate and III-V group compound semiconductor layer on said Si substrate. CONSTITUTION:A Ge layer 3 is laminated on a Si substrate where a SiO2 pattern 2 is formed and a GaAs layer 6 on which a GeO2 pattern 5 is formed is stacked on such Ge layer 3. A polycrystalline region is formed at the upper part 2a and periphery 2b of the SiO2 pattern 2. The polycrystalline region is also formed at the upper part 5a and periphery 5b of the GeO2 pattern 5.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a compound semiconductor device in which an m-v group compound semiconductor layer such as GaAs is epitaxially grown on a Si substrate, and is used as a core technology for manufacturing compound semiconductor devices. be done.

(Conventional technology) Epitaxial growth of an m-v group compound semiconductor layer on a Si substrate is an important technology for the development of devices such as three-dimensional integrated circuits, optoelectronic new functional devices, and wavelength-splitting high-efficiency solar cells. be.

However, 8, for example, GaAs has a mismatch of about 4% with St in lattice constant, and also has a difference of about twice in thermal expansion coefficient. Therefore, conventionally, a halogen transport CVD method has been used to form a GaAs layer on a Si substrate.

Using crystal growth methods such as MOCVD and MBE.

Although epitaxial growth was performed, it was impossible to obtain a high-quality single-crystal epitaxial growth layer due to the above-mentioned mismatch.

Conventionally, in order to alleviate the mismatch between the Si substrate and the GaAs layer, a single intermediate layer has been interposed, an intermediate layer having a superlattice structure has been interposed, or SiO2 has been formed on the Si substrate in advance. A pansivation film such as □ is formed, and Ga
A method of growing an As layer by graphite epitaxial growth has been proposed.

(Objective of the Invention) However, even if such a solution is taken, it is still difficult to obtain a high quality GaAs single crystal layer on a Si substrate by simultaneously solving the mismatch between the lattice constant and the coefficient of thermal expansion. do not have.

In view of this point, the present invention provides a high-quality III film on a Si substrate.
- It is an object of the present invention to provide a compound semiconductor device in which a Group V compound semiconductor epitaxial layer is grown.

(Structure of the Invention) The present invention is characterized in that an intermediate layer is formed on a Si substrate to alleviate the mismatch in lattice constant between the Si substrate and the m-v group compound semiconductor layer, and the m-v group compound semiconductor layer and the intermediate layer Relating to a compound semiconductor device in which a localized polycrystalline region is formed,
For example, a Ge layer is used for this intermediate layer.

(Example) An example of the present invention will be described below with reference to the drawings.

In FIG. 4, Sin, Si on which pattern 2 is formed
A Ge layer 3 is laminated on a substrate 1, and a Ge layer 3 is formed on the Ge layer.
A GaAs layer 6 on which an O2 pattern 5 is formed is laminated. Polycrystalline regions are formed in the upper part 2a and peripheral part 2b of the Sin pattern 2, and polycrystalline regions are also formed in the upper part 5a and peripheral part 5b of the Ge0Z pattern 5.

The manufacturing procedure of the two examples will be explained below with reference to FIGS. 1 to 4.

■ Thermal oxidation of the surface of a single-crystal Si substrate l results in S i O
After forming the Z film, a desired SiO pattern 2 is formed using photolithography.

After forming the Si pattern 2, the Si substrate is heated in a high vacuum to clean the growth surface.

(2) Next, the Ge layer 3 is formed by a vapor deposition method, a CVD method using thermal decomposition of Get(4), etc. In this case.

Parameters such as substrate temperature, degree of vacuum, growth rate, and Ge
By optimizing the annealing conditions after layer formation, the SiO
□The Ge layer 3a separated from the pattern 2 easily becomes a single crystal, while the Ge layer 3b formed in the upper part 2a of the Sing pattern 2 and its peripheral part 2b becomes a polycrystalline region containing many polycrystalline nuclei. Become. This occurs because thermal stress due to the difference in thermal expansion coefficients between St and Ge is concentrated at the stepped portion between the Si substrate 1 and the Stow pattern 2, and a large number of Ge polycrystalline nuclei are generated.

■ Single crystallized Ge layer 3a obtained as described above
The surface of the polycrystalline Ge layer 3b is then thermally oxidized to form a Ge
, after forming the film, G is applied using photolithography technology.
Form e0z pattern 5. This gem, pattern 5
are aligned so as to cover the Ge polycrystalline region formed in the upper part 2a of the SiOt pattern 2.

(2) Then, on the Ge layer 3 and the Ge0Z pattern 5, halogen transport vapor phase epitaxy and organic metal vapor phase epitaxy (
After growth, the GaAs layer 6 is grown using a compound semiconductor layer growth technique such as MOCVD (bimolecular beam epitaxy (MBE)).

Apply annealing. When such growth is performed, a polycrystalline region 6 of GaAs is formed at the step between the GeO2 pattern 5 and the Ge layer 3.
b is generated and thermal stress is thereby released, so that a high quality GaAs single crystal epitaxial growth layer is realized in the region 6a other than the peripheral portion of the pattern.

FIG. 5 shows an example of application of the above-mentioned embodiment, in which a 3i substrate l
Si active region 10 and G formed by ion implantation
This is a three-dimensional circuit element comprising a GaAs active region 11 formed in an aAs layer 6. In this case, the S i O,
Doped polysilicon 12 using ion implantation technology is used instead of pattern 2, and the other configuration is the fourth pattern.
Same as the figure. In the figure, 13 is an electrode for a Si circuit, and 14 is an electrode for a GaAs circuit.

(Effects of the Invention) As described above, according to the present invention, a high-quality compound semiconductor device can be obtained by releasing thermal stress caused by a difference in thermal expansion coefficients, and also eliminates mismatching of lattice constants. can do.

[Brief explanation of the drawing]

The drawings show an embodiment of a compound semiconductor device according to the present invention, and FIGS. 1 to 4 are cross-sectional views showing steps of the manufacturing procedure in sequence, and FIG. 5 is a cross-sectional view of a three-dimensional circuit device showing an application example of the present invention. FIG. 1...Si substrate 2...SiO□ pattern 3
...Ge layer 6...GaAs layer Fig. 7 Fig. 2 Fig. 3 Fig. 4 Fig. 5

Claims (1)

[Claims] 1) An intermediate layer is formed on the Si substrate to alleviate the lattice constant mismatch between the Si substrate and the III-V compound semiconductor layer, and local polycrystalline regions are formed in the III-V compound semiconductor layer and the intermediate layer. What is claimed is: 1. A compound semiconductor device comprising: