JPS61187364A - Ohmic electrode - Google Patents
Ohmic electrodeInfo
- Publication number
- JPS61187364A JPS61187364A JP2623185A JP2623185A JPS61187364A JP S61187364 A JPS61187364 A JP S61187364A JP 2623185 A JP2623185 A JP 2623185A JP 2623185 A JP2623185 A JP 2623185A JP S61187364 A JPS61187364 A JP S61187364A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ohmic electrode
- electrode
- width
- oxided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052737 gold Inorganic materials 0.000 claims abstract description 3
- 229910052735 hafnium Inorganic materials 0.000 claims abstract description 3
- 229910052709 silver Inorganic materials 0.000 claims abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 claims abstract 2
- 229910052804 chromium Inorganic materials 0.000 claims abstract 2
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract 2
- 229910052715 tantalum Inorganic materials 0.000 claims abstract 2
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 12
- 230000008021 deposition Effects 0.000 abstract description 9
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 238000010030 laminating Methods 0.000 abstract 1
- 239000003870 refractory metal Substances 0.000 description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体に対するオーム性電極、特にｍ−Ｖ族化
合物半導体に対するオーム性電極に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to ohmic electrodes for semiconductors, particularly ohmic electrodes for m-V compound semiconductors.
従来、高キャリア濃度を煙畜Ｐ型Ｇ ａ Ａ ｓ 、半
導体のオーム性電極にはＣｒ −Ａ ｕ 、 Ｍ ｏ
−Ａ ｕ ｔＴ ｘ −Ａ ｕなどで構成された。高融
点金属とＡｕまたはＡｇからなる２層構造の電極が広く
用いられている。たとえば、町野等のｒ電極技術Ｊ東芝
レビュー、ｖｏ１２４＆６ｐｐ７２７−７３０昭４４等
に報告がある。Conventionally, high carrier concentration has been achieved using P-type GaAs, and Cr-Au, Mo for semiconductor ohmic electrodes.
-A u tT x -A u etc. Electrodes with a two-layer structure consisting of a high melting point metal and Au or Ag are widely used. For example, there is a report in Machino et al.'s R Electrode Technology J Toshiba Review, vol. 124 & 6 pp. 727-730, 1973, etc.
しかし、これらの電極は、電極形成後に２００〜４００
℃の熱処理を行うと、電極層相互の拡散や、Ｇ ａ Ａ
ｓから分解したＧａやＡｓの外方拡散により、電極層
の産資や、合金化が生じることが知られている。このた
め、電極金属の半導体基板への過度の侵入や、電極層へ
のワイヤボンディングが不能となるなどの欠点をもって
いる。However, these electrodes are 200 to 400
When heat treatment is performed at ℃, mutual diffusion between electrode layers and G a A
It is known that the outdiffusion of Ga and As decomposed from s causes the formation of metals and alloys in the electrode layer. For this reason, there are drawbacks such as excessive penetration of the electrode metal into the semiconductor substrate and the impossibility of wire bonding to the electrode layer.
本発明の目的は、上記の欠点を解消した。耐熱性に優れ
たオーム性電極を提供することにある。The object of the invention is to overcome the above-mentioned drawbacks. The object of the present invention is to provide an ohmic electrode with excellent heat resistance.
先に挙げた電極が劣化するのは、金属層間の相互拡散や
、ＧａＡｓから分解したＧａやＡｓの外方拡散によるも
のである。そこで、上記の従来電極の第一層目の高融点
金属層の拡散バリヤとしての性能を向上させるべく検討
を行った結果、若干酸化された状態の高融点金属層を、
第一層目の中間層として設ける方法が、最も簡便であり
、かつ効果的なことがわかった。The deterioration of the above-mentioned electrodes is due to interdiffusion between metal layers and outdiffusion of Ga and As decomposed from GaAs. Therefore, we conducted studies to improve the performance of the first refractory metal layer of the conventional electrode as a diffusion barrier, and found that the refractory metal layer in a slightly oxidized state was
It has been found that the method of providing it as an intermediate layer of the first layer is the simplest and most effective method.
第一層（高融点金属層）目の中間に、若干酸化した状態
の高融点金属層を設けるには、高融点金属の蒸着途中で
、蒸着チャンバ内に、制御された微量の酸素ガスを導入
するか、あるいは、蒸着レートを著しく低下させればよ
い。To provide a slightly oxidized refractory metal layer in the middle of the first layer (refractory metal layer), a controlled trace amount of oxygen gas is introduced into the deposition chamber during the deposition of the refractory metal. Alternatively, the deposition rate may be significantly reduced.
以下１本発明の実施例を第１図、第２図を用いて詳細に
説明する。An embodiment of the present invention will be described in detail below with reference to FIGS. 1 and 2.
実施例１
第１図は、Ｍ ｏ −Ａ ｕからなるＰ型Ｇ ａ Ａ
ｓに対するオーミック電極に本発明を適用した場合の電
極構造を示す断面図である。以下その製造方法を説明す
る。Example 1 FIG. 1 shows a P-type Ga A consisting of M o -A u.
FIG. 3 is a cross-sectional view showing an electrode structure when the present invention is applied to an ohmic electrode for s. The manufacturing method will be explained below.
表面キャリア濃度が大略Ｉ Ｘ １０”ａｍ−’のＰ型
Ｇ ａ Ａ ｓ基板１上に、Ｍｏ層２とＡｕ層３が真空
蒸着法により形成されている。まず、ｐ−ＧａＡｓ基板
１を２００〜３００℃に加熱したのち、真空度約５ Ｘ
１０−’Ｔｏｒｒ、蒸着レート５〜１５人／ｓｅｅに
おいて、電子ビーム蒸着法により、膜厚約５００人の第
１ Ｍ ｏ層４を形成する０次に、バリアプルリークバ
ルブを介して、真空チャンバ内に酸素ガスを導入したの
ち、蒸着レート０．１〜１．０人／８ｅＣにおいて、膜
厚２０００人の第２ Ｍ ｏ層５を形成する。ついで、
酸素ガスの導入を停止したのち、第１ Ｍ ｏ ｊｆｌ
ち同一の条件で第３ Ｍ ｏ層６（膜厚約５００人）を
形成する。最後に、抵抗線加熱蒸着法によりＡｕ層７を
厚さ約５０００人形成してオーム性電極を完成する。A Mo layer 2 and an Au layer 3 are formed by vacuum evaporation on a P-type GaAs substrate 1 with a surface carrier concentration of approximately I x 10"am-'. First, the p-GaAs substrate 1 is After heating to ~300℃, vacuum degree is approximately 5X
A first Mo layer 4 having a film thickness of about 500 mm is formed by electron beam evaporation at a deposition rate of 5 to 15 mm/see at 10 Torr and a deposition rate of 5 to 15 mm/see. After introducing oxygen gas into the chamber, a second Mo layer 5 having a film thickness of 2000 layers is formed at a deposition rate of 0.1 to 1.0 layers/8 eC. Then,
After stopping the introduction of oxygen gas, the first M o jfl
A third Mo layer 6 (film thickness of about 500 layers) is then formed under the same conditions. Finally, an ohmic electrode is completed by forming an Au layer 7 with a thickness of about 5,000 layers using a resistance wire heating vapor deposition method.
通常の方法で製作したＭ ｏ −Ａ ｕの構造の電極が
４００’Ｃ５１時間程度の熱処理で劣化が始まるのに対
し、本実施例によるＭ ｏ −Ａ ｕの構造の電極では
４５０℃、１時間の熱処理にも充分耐えることができた
。While the electrode with the M o -A u structure manufactured by the usual method begins to deteriorate after heat treatment at 400'C for about 51 hours, the electrode with the M o -A u structure according to this example was heated at 450C for 1 hour. It was able to sufficiently withstand heat treatment.
実施例２
第２図は、ｎ型ＧａＡｓに対するオーム性電極層上に１
本発明によるＭｏ Ａｕ電極を設けた場合の電極構造
を示す断面図である。Example 2 FIG. 2 shows the ohmic electrode layer for n-type GaAs
FIG. 3 is a cross-sectional view showing an electrode structure when a MoAu electrode according to the present invention is provided.
表面キャリア濃度が大略Ｉ Ｘ Ｉ Ｏ”ａｓ−’のｎ
型Ｇ ａ Ａ ｓ基板２１上にＡｕＧｅＮｉ （Ａｕ
： Ｇｅ：Ｎ１＝８８ ：１２ ： ４ｗｔ、）層２２
（膜厚１０００人）を室温蒸着し、ついで、真空チャン
バ内で４００℃、５分間の淵処理を施してオーム性の接
触を得る０次に、基板温度を２００℃に冷却したのち。The surface carrier concentration is approximately I
AuGeNi (Au
: Ge:N1=88 :12 :4wt, ) layer 22
(film thickness: 1000) was deposited at room temperature, and then subjected to edge treatment at 400°C for 5 minutes in a vacuum chamber to obtain ohmic contact.Then, the substrate temperature was cooled to 200°C.
実施例１を全く同一の条件により、ＭＯ層２３を形成す
る。すなわち、ほとんど酸化されていない第１ Ｍ ｏ
層２５（膜厚５００人）、やつ酸化されている第２ Ｍ
ｏ層２６（膜厚２０００人）、ほとんど酸化されてい
ない第３ Ｍ ｏ層２７（膜厚５００人）を順次形成す
る。最後に、Ａ ｕ ＠ ２２４を被着してオーム性電
極を完成する。The MO layer 23 is formed under exactly the same conditions as in Example 1. That is, the first Mo that is hardly oxidized
Layer 25 (thickness: 500), the second layer is oxidized
A layer 26 (thickness: 2,000 layers) and a third Mo layer 27 (thickness: 500 layers), which is hardly oxidized, are sequentially formed. Finally, A u@224 is deposited to complete the ohmic electrode.
通常の方法で製作した従来のＡ ｕ Ｇ ｅ Ｎ １−
Ａｕ構造のｎ型オーム性電極では、２００℃。Conventional A u G e N 1- manufactured by normal method
For an n-type ohmic electrode with an Au structure, the temperature is 200°C.
３０分間の熱処理を経ると劣化が生じ、Ａｕ層上へのＡ
ｕ線のワイヤボンドが極めて困難であったが１本実施例
によれば、３５０℃、１時間の熱処理後も電極の劣化は
起きず、Ａｕ層２４上へのワイヤボンドも極めて容易に
行うことができた。After 30 minutes of heat treatment, deterioration occurs and A
Wire bonding of U-line was extremely difficult, but according to this example, the electrode did not deteriorate even after heat treatment at 350° C. for 1 hour, and wire bonding onto the Au layer 24 was extremely easy. was completed.
本発明によれば、バリヤ層を含む電極構造に何らの変更
を加えることなく、単に、バリヤ層となる高融点金属の
被着時の真空度と被着レートを制御するのみで、バリヤ
層の性能を大幅に向上することができる。According to the present invention, without making any changes to the electrode structure including the barrier layer, the barrier layer can be formed simply by controlling the degree of vacuum and deposition rate during deposition of the high melting point metal that will become the barrier layer. Performance can be significantly improved.
本発明の適用により、電極の低熱性は５０〜１５０℃以
上向上し、ワイヤボンディングの作業遇デバイスの信頼
性の向上にも寄与するところが大きい。By applying the present invention, the low thermal properties of the electrode are improved by 50 to 150° C. or more, which greatly contributes to improving the reliability of devices during wire bonding operations.
なお、実施例では、高融点金属としてＭｏを用いた例を
示したが、ＭＯのみならず、Ｃｒ ｒ Ｔ ｌ １Ｔａ
ｎ Ｈｆ、Ｗなどの他の高融点金属でバリヤを構成する
場合にも本発明が適用できる。In addition, in the example, an example was shown in which Mo was used as the high melting point metal, but not only MO but also Cr r T l 1Ta
The present invention can also be applied when the barrier is composed of other high melting point metals such as n Hf and W.
また、本発明によるバリヤ層の被着方法とじては、電子
ビーム蒸着法に限るものではなく、スパッタ蒸着法や、
クラスタイオンビーム蒸着法なども適用できる。Furthermore, the method of depositing the barrier layer according to the present invention is not limited to electron beam evaporation, but may include sputter evaporation,
Cluster ion beam evaporation method can also be applied.
さらに、本発明の適用対象となる半導体材料は、Ｇ ａ
Ａ ｓのみならず、ＧａＡｌ２Ａｓ、ＧａＰ。Furthermore, the semiconductor material to which the present invention is applied is Ga
Not only As, but also GaAl2As, GaP.
ＩｎＧａＡｓＰ、ＩｎＰなどのｍ−ｖ糖化合物半導体に
適用可能である。It is applicable to m-v sugar compound semiconductors such as InGaAsP and InP.
また１本発明の適用できる下地のオーム電極層は、Ａｕ
ＧａＮｉ層のみならず、Ａ ｕ Ｇ ｅ −Ｎ ｉ 。Furthermore, the underlying ohmic electrode layer to which the present invention can be applied is Au.
Not only the GaNi layer but also A u G e -N i .
Ａ ｕ −Ｚ ｎ 、 Ａ ｕ −Ｓ ｎ 、 Ａ ｕ
−Ｓ ｉなどで構成されるオーム性電極層に対しても
適覆可能である。A u -Z n , A u -S n , A u
- It is also possible to suitably coat an ohmic electrode layer composed of Si or the like.
さらに１本発明は、オーム性電極の他の、ショットキバ
リヤ電極や、集積回路中の配線金属層に対しても適用で
きる。Furthermore, the present invention can be applied to Schottky barrier electrodes and wiring metal layers in integrated circuits in addition to ohmic electrodes.
第１図は、本発明の一実施例を示す断面図、第２図は１
本発明の他の実施例を示す断面図である。
２．２３−Ｍｏ層、４．２５・・・第１ Ｍ ｏ層、５
゜代理人 弁理士 小用勝−１′５．・７第 １ 図
第２０FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
FIG. 3 is a sectional view showing another embodiment of the present invention. 2.23-Mo layer, 4.25... first Mo layer, 5
゜Representative Patent Attorney Masaru Koyo-1'5.・7 Figure 1 Figure 20
Claims (2)
なる、III−Ｖ族化合物半導体用のオーム性電極におい
て、上記半導体基板に接して被着した高融点金属層を、
ほとんど酸化されていない第１層領域と、拡散バリヤと
しての性能を向上させるために適度に酸化された第２層
領域と、ほとんど酸化されていない第３層領域とを連続
的に堆積させて構成したことを特徴とするオーム性電極
。1. In an ohmic electrode for a III-V compound semiconductor consisting of two layers of a high melting point metal and Au, Ag or Al, the high melting point metal layer is deposited in contact with the semiconductor substrate,
Consisting of successive deposits of a first layer region that is hardly oxidized, a second layer region that is moderately oxidized to improve its performance as a diffusion barrier, and a third layer region that is hardly oxidized. An ohmic electrode characterized by:
いずれか１つ、またはこれらの組合せからなることを特
徴とする特許請求範囲第１項記載のオーム性電極。2. The ohmic electrode according to claim 1, wherein the high melting point metal is made of any one of Cr, Mo, Ta, Hf, W, or a combination thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2623185A JPS61187364A (en) | 1985-02-15 | 1985-02-15 | Ohmic electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2623185A JPS61187364A (en) | 1985-02-15 | 1985-02-15 | Ohmic electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61187364A true JPS61187364A (en) | 1986-08-21 |
Family
ID=12187561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2623185A Pending JPS61187364A (en) | 1985-02-15 | 1985-02-15 | Ohmic electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61187364A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5124270A (en) * | 1987-09-18 | 1992-06-23 | Kabushiki Kaisha Toshiba | Bipolar transistor having external base region |
| US5273937A (en) * | 1988-01-08 | 1993-12-28 | Kabushiki Kaisha Toshiba | Metal semiconductor device and method for producing the same |
| JPH0766391A (en) * | 1993-08-31 | 1995-03-10 | Nec Corp | Ohmic electrode |
| WO1998025310A1 (en) * | 1996-12-06 | 1998-06-11 | Raytheon Ti Systems, Inc. | GATE ELECTRODE FOR GaAs FET |
-
1985
- 1985-02-15 JP JP2623185A patent/JPS61187364A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5124270A (en) * | 1987-09-18 | 1992-06-23 | Kabushiki Kaisha Toshiba | Bipolar transistor having external base region |
| US5273937A (en) * | 1988-01-08 | 1993-12-28 | Kabushiki Kaisha Toshiba | Metal semiconductor device and method for producing the same |
| JPH0766391A (en) * | 1993-08-31 | 1995-03-10 | Nec Corp | Ohmic electrode |
| WO1998025310A1 (en) * | 1996-12-06 | 1998-06-11 | Raytheon Ti Systems, Inc. | GATE ELECTRODE FOR GaAs FET |
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