JPS61184078A - Color encoder circuit - Google Patents

Abstract

PURPOSE:To obtain a color encoder from which color difference components coping with a TV receiver of the PAL and NTSC system are obtained easily by inverting the three primary chrominance components in a period twice that of a horizontal synchronizing signal in converting the three primary chrominance components into the color difference components. CONSTITUTION:The three primary chrominance components R, G, B from terminals 1-3 and a burst flag signal from a terminal 4 are inputted to a matrix circuit 5, and an inverted horizontal synchronizing siganl H' is fed from a terminal 8 to an FF9. The siganl having double period that of the signal H fed from the circuit 5 is controlled by a switch circuit 10, and in case of a receiver with the PAL system, the color difference components B-Y from the circuit 5 and an output inverting the phase of the color components R-Y in a period twice the period of the signal H are obtained, and the signal B-Y and R-Y are outputted in case of the NTSC system. The color difference components are fed respectively to orthogonal modulation circuits 6, 7, a chrominance subcarrier signal from a terminal 11 is used to generate a pi/4 lead signal and a pi/4 lag signal from a phase shift circuit 2, which apply orthogonal modulation, and the modulated color difference components are superimosed to output the chrominance components.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field of the Invention] The present invention relates to a color encoder circuit that obtains a video signal compatible with an NTSC or PAL television receiver from three primary color signals.

[Problem that the invention seeks to solve]

Generally, a color encoder circuit as shown in FIG. 4 is used for personal computers, game machines, etc., and is compatible with NTSC or PAL television receivers. In the figure, 5 is a matrix circuit, and inverters 60, 61, 65
67, buffers 62 to 64, and resistors 68 to 75, three primary color signals are input from input terminals 1, 2, and 3, and a burst flag signal is input from input terminal 4, respectively, and a color difference signal (B-Y), ( RY) is obtained.

These color difference signals are modulated in quadrature modulators 6, 7 by color subcarrier signals obtained via a phase shift circuit 12. The phase of the modulated color difference signal (R-Y) from the quadrature modulator 7 is inverted by a switch circuit 76 at twice the period of the horizontal synchronizing signal supplied from the input terminal 8 to obtain a PAL chroma output. Also, a color encoder circuit is formed that obtains a chroma output compatible with an NTSC television receiver without inversion. Therefore, PAL and NTS
The means to obtain the chroma output corresponding to the C-scheme receiver is performed by a signal after quadrature modulation, and it is used in a high frequency band (
In order to switch signals at 4.43 MHz), it is necessary to use an analog switch with excellent frequency characteristics, which has the disadvantage of being expensive.

Furthermore, the phase inversion of the color difference signal (R-Y) cannot always be said to be good.

[Purpose of the invention]

The present invention was made in view of the above-mentioned problems, and its main purpose is to use PAL and NTSC systems in a relatively low frequency band.
An object of the present invention is to provide a color encoder circuit equipped with a matrix circuit for obtaining a color difference signal compatible with a television receiver of this type.

Another object of the present invention is to provide a color encoder circuit equipped with a matrix circuit that obtains color difference signals without fluctuations in DC components when switching to obtain color difference signals compatible with PAL and NTSC receivers. .

Still another object of the present invention is to provide a color encoder circuit that can be easily integrated into a semiconductor integrated circuit.

[Summary of the invention]

In the color encoder circuit of the present invention, the matrix circuit part generates the color difference signal (R-Y) at twice the period of the horizontal synchronization signal by a circuit system for obtaining the color difference signal (B-Y) and selection by a switching signal. By including a circuit system for obtaining an output with phase inversion or an output without phase inversion, a chroma output compatible with PAL and NTSC television receivers is obtained.

[Embodiments of the invention]

The color encoder circuit of the present invention will be explained based on FIGS. 1 to 3.

FIG. 1 is a block diagram of a color encoder circuit, in which three primary color signals R, G, and B are supplied to a matrix circuit 5 from input terminals 1, 2, and 3, and a burst flag signal is supplied from an input terminal 4, respectively. An inverted horizontal synchronizing signal is supplied from a terminal 8 to a flip-flop (hereinafter abbreviated as F/F) 9. A color subcarrier signal is supplied from a terminal 11 to a phase shift circuit 12 . 6.7 is a quadrature modulation circuit.

The switch circuit 10 is a switch for selecting between the NTSC system and the PAL system. The switch circuit 10 controls a signal with twice the period of the horizontal synchronization signal supplied to the matrix circuit 5, and in the case of a PAL receiver, the color difference signal (B-Y) and the horizontal synchronization signal are supplied from the matrix circuit 5. The phase of the color difference signal (R-Y) is inverted at twice the period of NTSC, and the color difference signal (B
-Y) and (RY).

These color difference signals are respectively supplied to quadrature modulation circuits 6.7, and the color subcarrier signals manually inputted from terminals 11 are converted by a phase shift circuit 12 into a signal with a phase lead of π/4 and a signal with a phase delay of π/4. The chrominance signals are quadrature modulated and the modulated color difference signals are superimposed to obtain a chroma output.

Now, FIG. 2 is a circuit diagram showing an embodiment of the matrix circuit section of the color encoder circuit of the present invention.

The matrix circuit 5 in FIG.
It is formed from a circuit that obtains the output of the system and (RY) system. Terminals 1 to 4 are inverters 20 and 21 and buffer 2, respectively.
2.23, and their output terminals are connected to resistors 39 to 4.
2 and their other ends are commonly connected to a resistor 48.
．． 49 and is connected to the output terminal 17 to form a color difference signal (B-Y) system circuit. - In the old color difference signal (R-Y) system, the Q terminal of F/F9 is connected to one terminal of NAND circuits 24, 27.29 and one terminal of AND circuit 31, and The terminal is
It is connected to one terminal of NAND circuits 25, 26 and 28, 30. The input terminal 1 is connected to the other input terminal of the NAND circuit 24 and is also connected to the other input terminal of the NAND circuit 25 via the inverter 32.
The output terminals of the D circuits 24 and 25 form a wired OR circuit (hereinafter abbreviated as W-OR circuit) 36 and are connected to a resistor 43. Further, terminals 2 and 3 are connected in the same way as terminal 1 to form a logic circuit. Terminal 4 is NAND circuit 3
The other input terminal of the NAND circuit 35 is connected to the P terminal of the F/F 9 and the switch circuit 10, and its output terminal is connected to the other terminal of the NAND circuit 30 and the AND circuit 31. and their respective output terminals are connected to resistors 46 and 47. And resistance 43-47
The other end is connected in common, and is also connected to the common connection point of the resistors 50 and 51 and the output terminal 18.

Next, the operation will be explained based on the timing charts of FIGS. 3(a) to 3(j).

First, a color difference signal (B-Y) system circuit that operates in common with the PAL system and the NTSC system will be described. Input terminal 1
4, the three primary color signals R, C, , B and the burst flag signal shown in FIG. Horizontal sync signal is supplied. Therefore, when the pulses shown in FIGS. 3(a) to 3(d) are supplied, the (BY) system inverter 20,
The logical values of the outputs of 21 and buffers 22 and 23 are as shown in Table 1. In addition, inverters 20 and 21 and buffers 22
．． 23 is an open collector, and the resistance values of the resistors 39 to 42 are such that the resistance value of the resistor 39 is the largest, and the resistance value of the resistor 4 is the highest.
Weighting is given to values as small as 0.41.

(Table 1) Depending on the output state as shown in Table 1 and the timing of the burst flag signal added to the buffer 23, (B-Y
) signal is offset to the negative side to generate a color burst signal, and an output pulse of a color difference signal (B-Y) as shown in FIG. 3(h) is obtained from terminal F.

Next, the operation of the (RY) system circuit in the case of an NTSC receiver will be described. Similarly to the above example, input terminals 1 to 4 receive pulses as shown in FIGS. 3(a) to 3(d), respectively, and input terminal 8 receives pulses as shown in FIG. 3(e). A signal is input. Switch 10 is NTS
A switch is connected to the terminal 14 in order to support the C method.

Therefore, the P terminal of F/F9 is grounded, and the P terminal of F/F9 is grounded.
)(g-1), the output of the Q terminal is "1" and the output of the Q terminal is "0". That is, one terminal of the NAND circuit 30 is fixed at "0", and one terminal of the AND circuit 31 is fixed at "1". On the other hand, N A, N D circuit 3
One terminal of 5 is fixed to "0", and the other terminal receives the burst flag signal from input terminal 4 shown in FIG. 3(d).
Even if “1” or “0” is input, the NAND circuit 3
5 is fixed at "1", the output terminal of the NAND circuit 30 becomes "1", and the output terminal of the AND circuit 31 becomes "0". The output terminals of the NAND circuit 30 and the AND circuit 31 are formed of open collectors, and the resistance values of the resistors 46 and 47 are set to be equal, so that the influence of the burst flag signal is eliminated. In addition, the three primary color signals R, G, and B and the burst flag signal are inputted from the input terminals 1, 2, and 3°4 to the input terminals of the NAND circuits 24 to 29 as shown in FIGS. From F/F9 to Figure 3 (f-1
)(g-1) is input. Therefore, W-
The output states of the OR circuits 36, 37, and 38 are as shown in Table 2.

(Table 2) The resistors 43, 44, and 45 are weighted so that their resistance values increase sequentially, and the output terminal 18 outputs a color difference signal (R-Y) as shown in FIG. 3(i). has been done.

Next, the case of the PAL system will be explained. switch 10
is switched to contact 13. When a high level signal is input to the P terminal of F/F9, the terminal connected to the Q terminal will be shown as shown in Figure 3 (
Output pulses such as f-2) (g-2) are input. (
An output as shown in FIG. 3(j) is obtained from the output terminal 18 of the RY) system. When the Q terminal is "1" and the period of the Q terminal is rOJ, the output waveform is similar to that of the NTSC system, so the creation of a logic value table is omitted. F/F9 in next cycle
When the Q terminal is rOJ and the Q terminal is inverted to "1", W-
The output states of the OR circuits 36, 37, and 38 are as shown in Table 3.

(Table 3) Furthermore, the resistance values of the resistors 43, 44.45 are weighted sequentially. Furthermore, the output terminal is an open collector N
The outputs of the AND circuit 30 and the AND circuit 31 are "1", and the resistance values of the resistors 46 and 47 are set to be equal, so that the DC level after switching of this circuit portion is kept constant. At the same time, a color burst signal is generated by applying an offset to the timing of the burst flag signal in both positive and negative directions at 1/2 the timing of the horizontal synchronizing signal.

As is clear from the logical values in Tables 2 and 3, the Q of F/F9
The terminal changes from “0” to “1”, and the Q terminal changes from “IJ” to “0”.
When the horizontal synchronizing signal is inverted, the output of the output terminal 18 is inverted at twice the period of the horizontal synchronizing signal. Therefore, by switching the switch 10, a video signal compatible with PAL and NTSC television receivers can be easily obtained.

〔Effect of the invention〕

The present invention is a color encoder circuit that can obtain color difference signals compatible with PAL and NTSC television receivers by means of a matrix circuit. By periodically inverting the signals, a color difference signal compatible with the PAL system can be obtained very easily. Therefore, since signals can be inverted in a relatively low frequency band (approximately IMHz), an inexpensive color encoder circuit can be provided without using expensive analog switches compared to conventional color encoder circuits, and the present invention The color encoder circuit can be easily integrated into a semiconductor integrated circuit.

Furthermore, even if the chroma output of the NTSC system is switched to the PAL system, the DC output of the color difference signal (R-Y) system is kept constant, so there is no distortion in the video signal, resulting in an excellent effect. It is something that plays.

[Brief explanation of drawings]

FIG. 1 is a book diagram showing an embodiment of a color encoder circuit of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of a matrix circuit which is a main part of the color encoder circuit of the present invention.
FIG. 3 is a timing chart for explaining the operation of the color encoder circuit of the present invention, and FIG. 4 is a diagram for explaining the conventional color encoder circuit. 1.2, 3: Input terminal 4 to which the three primary color signals are input: Input terminal 5 to which the burst flag signal is input: Matrix circuit, 6.77 quadrature modulation circuit 8; Long sword terminal 9 to which the horizontal synchronization signal is input: F /F, 11: Color subcarrier signal input terminal, 10: Switch circuit

Claims (1)

[Claims] A matrix circuit that obtains a color difference signal from three primary color signals is connected to a circuit system that obtains a first color difference signal (B-Y) and a second color difference signal (R-Y) that is inverted at twice the period of the horizontal synchronization signal by a switching signal. ) or obtain a third color difference signal (R
- Y), and quadrature modulates the first and second or third color difference signals from the matrix circuit using color subcarriers having different phases, respectively, and outputs the respective outputs. A color encoder circuit characterized by obtaining chroma output through superimposition.