JPS61177700A - Composite association memory - Google Patents

Composite association memory

Info

Publication number
JPS61177700A
JPS61177700A JP60016523A JP1652385A JPS61177700A JP S61177700 A JPS61177700 A JP S61177700A JP 60016523 A JP60016523 A JP 60016523A JP 1652385 A JP1652385 A JP 1652385A JP S61177700 A JPS61177700 A JP S61177700A
Authority
JP
Japan
Prior art keywords
register
condition
coincidence
circuit
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60016523A
Other languages
Japanese (ja)
Other versions
JPH0743942B2 (en
Inventor
Shinichiro Miyaoka
宮岡 伸一郎
Akira Muramatsu
晃 村松
Seiju Funabashi
舩橋 誠寿
Tsutomu Tashiro
勤 田代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60016523A priority Critical patent/JPH0743942B2/en
Publication of JPS61177700A publication Critical patent/JPS61177700A/en
Publication of JPH0743942B2 publication Critical patent/JPH0743942B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

PURPOSE:To make it possible promptly and accurately to discriminate the establishment of plural conditions by providing a register storing the presence or absence of the condition establishment to a cell of a portion storing a conditional word equipped with a circuit for discriminating the coincidence or non- coincidence with the retrieval key. CONSTITUTION:The retrieval key information from a retrieval key buffer 6 is compared with the contents of a conditional word register 8 in a cell 7 at a coincidence circuit where coincidence is discriminated. The coincidence and non-coincidence are written as 1 or 0 in a condition establishment register 9 and the contents of the register 9 of each cell 7 are processed by an AND circuit 10. The output of the circuit 10 goes H only when plural conditions are established to read the association data. By this, the establishment of plural conditions are promptly and accurately discriminated to provide for high speed operation of the composite associative memory.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、複数の条件が成立したときにある結果が導か
れるような対象に対し、条件成立の判別と結果の読み出
しを高速化する装置に係り、特に複合的な検索、ルール
型制御、2値的推論に好適な複合連想メモリに関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a device that speeds up the determination of whether a condition is satisfied and the reading of the result for a target where a certain result is derived when a plurality of conditions are satisfied. In particular, the present invention relates to a complex associative memory suitable for complex searches, rule-based control, and binary reasoning.

〔発明の背景〕[Background of the invention]

従来の連想メモリは、一つの検索キーに対し一致する条
件語を持つデータを出力するものであって、複数の検索
キーに対し複数の条件語の成立を識別しなければならな
いような問題に対しては、機能的に不十分であった。
Conventional associative memory outputs data with matching condition words for one search key, and is useful for problems where it is necessary to identify whether multiple condition words hold true for multiple search keys. However, it was functionally inadequate.

【発明の目的〕[Purpose of the invention]

本発明の目的は、複数の検索キーに対し、複数の条件語
の成立を識別し、全条件が成立した結果データを高速に
読み出し得る複合連想メモリを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a complex associative memory that can identify the fulfillment of a plurality of condition words for a plurality of search keys and read out result data for which all conditions are satisfied at high speed.

〔発明の概要〕[Summary of the invention]

一つの条件語を記憶する部分をセルと呼ぶことにするが
、このセルは通常検索キーとの一致不一致を識別する回
路を備えている。本発明ではさらに各セルごとに条件成
立の有無を記憶するレジスタを設け、このレジスタの出
力から、一つの結果データの全条件語が現在までに入力
された検索キーのいずれかと一致したか、すなわち複合
条件が成立したのかを判別する点に特徴がある。
The part that stores one condition word is called a cell, and this cell is usually equipped with a circuit that identifies whether it matches or does not match a search key. In the present invention, a register is further provided for each cell to store whether or not a condition is satisfied, and from the output of this register, it is possible to determine whether all condition words of one result data match any of the search keys input so far. The feature is that it determines whether a compound condition is met.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第1〜3図に従い説明する。 An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

@1図の例では1条件C工f Q29 as が成立し
たとき、結果R1が読み出される。また、結果R。
@1 In the example shown in Figure 1, when one condition C operation f Q29 as is satisfied, the result R1 is read out. Also, the result R.

が読み出されるためには、条件axrc<が成立してい
る必要がある。この例に対し複合連想メモリを構成した
例が第2図である。全体は多数のセルから構成される条
件語記憶部1、普通のRAMである結果データ記憶部2
、応答レジスタ3、多重応答分解器4、符号器5、検索
キーバッファ6から構成される。条件語記憶部1を構成
する一つのセルフは、条件語レジスタ8と条件成立レジ
スタ9を備えている。
In order to read out, the condition axrc< must be satisfied. FIG. 2 shows an example in which a complex content addressable memory is configured for this example. The condition word storage unit 1 is composed of a large number of cells, and the result data storage unit 2 is an ordinary RAM.
, a response register 3, a multiple response decomposer 4, an encoder 5, and a search key buffer 6. One self constituting the condition word storage section 1 includes a condition word register 8 and a condition establishment register 9.

検索キーバッファ6に格納された検索キーが、順次条件
語記憶部1に入力される。検索キーは全セルにブロード
キャストされ、該キーと条件語が一致したセルにおいて
は条件成立レジスタ9にit 1”のフラグが立てられ
るものとする。たとえば、C3がキーとして入力される
と、レジスタ8の内容と一致しているのでレジスタ9の
内容が“1″となる。なお、条件語が格納されていない
セルの条件成立レジスタ9にはあらかじめ“1”がセッ
トされているものとし、他のセルの条件成立レジスタ9
の初期値は“0”とする1条件成立レジスタ9の出力は
、一つの結果に対応する条件の組ごとにANDがとられ
、該組の全条件が成立した時点で“1”が応答レジスタ
3に入力される。
The search keys stored in the search key buffer 6 are sequentially input to the condition word storage section 1. It is assumed that the search key is broadcast to all cells, and in cells where the key matches the condition word, a flag "it 1" is set in the condition fulfillment register 9. For example, when C3 is input as a key, the flag "it 1" is set in the condition fulfillment register 9. The contents of register 9 become "1" because the contents match the contents of Cell condition fulfillment register 9
The initial value of is "0". The output of the 1-condition fulfillment register 9 is ANDed for each set of conditions corresponding to one result, and "1" is set as the response register when all the conditions of the set are satisfied. 3 is input.

応答レジスタ3には一般に同時に複数個の“1”が入力
されることがあるので、多重応答分解@4により多重入
力を直列化するものとする。多重応答分解器4の出力は
符号器5でアドレス信号に変換された後RAM2に入力
される。RAM2からは成立した条件部に対応する結果
データが出力される。
Since a plurality of "1"s are generally input to the response register 3 at the same time, multiple inputs are serialized by multiple response decomposition@4. The output of the multi-response decomposer 4 is converted into an address signal by an encoder 5 and then input to the RAM 2. The RAM 2 outputs result data corresponding to the satisfied condition part.

セルフの内部構成を第3図に示す、セルフは条件語レジ
スタ82条件成立レジスタ9および一致回路11から構
成される。検索キーは、入力線12によって入力される
。このキーがレジスタ8の内容と一致したとき、レジス
タ9にクロック信号が入力され入力線13の値に従いレ
ジスタ9の内容が書き変えられる。入力線13には1条
件が新たに成立した場合に“1”、成立していた条件が
解除された場合に′0”の信号値が乗せられる。
The internal structure of the self is shown in FIG. 3. The self is composed of a condition word register 82, a condition establishment register 9, and a matching circuit 11. A search key is input via input line 12. When this key matches the contents of register 8, a clock signal is input to register 9, and the contents of register 9 are rewritten according to the value of input line 13. The input line 13 is loaded with a signal value of "1" when one condition is newly established, and a signal value of '0' when the previously established condition is cancelled.

条件の解除は、複合検索の途中で、以前に入力した検索
キーが成立しなくなった場合(たとえば制御に用いる場
合、外部状況が変化したときなど)に用いるものである
。なお1図中には記していないが、必要に応じて全セル
のレジスタ8,9の一括リセットを行えるものとする。
Canceling a condition is used when a previously input search key no longer holds true during a compound search (for example, when used for control, when external conditions change, etc.). Although not shown in FIG. 1, it is assumed that the registers 8 and 9 of all cells can be reset at once if necessary.

応答レジスタ3.多重応答分解器4.符号器5は公知の
もので良い(たとえば、「奥州:連想メモリとその応用
、 bit vol、is、Na4J ) e〔発明の
効果〕 本発明によれば、従来のCA M (ContentA
ddrassabla Mamoty)では困難であっ
た、複数の検索キーに基づき連想データを読み出すこと
をハードウェアだけを用いて行うことができるので。
Response register 3. Multi-response decomposer4. The encoder 5 may be a known encoder (for example, "Oshu: Associative memory and its applications, bit vol, is, Na4J").
This is because it is possible to read out associative data based on multiple search keys using only hardware, which was difficult with DDRASSABLA Mamoty).

複合条件の成立の判定、該条件成立時の対応結果読出し
を高速化できる効果がある。
This has the effect of speeding up the determination of whether a complex condition is met and the reading of corresponding results when the condition is met.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は条件−結果テーブルの一例を示す図、第2図は
複合連想メモリの全体構成図、第3図はセル内部構成の
一例を示す図である。 1・・・条件語記憶部、2・・・結果データ記fiRA
M。
FIG. 1 is a diagram showing an example of a condition-result table, FIG. 2 is a diagram showing the overall configuration of a complex associative memory, and FIG. 3 is a diagram showing an example of the internal configuration of a cell. 1... Condition word storage unit, 2... Result data record fiRA
M.

Claims (1)

【特許請求の範囲】[Claims]  検索キーと記憶内容の一致不一致により必要データを
読み出す連想メモリにおいて、一つの読み出しデータに
対し検索キーの比較対象となる複数個の条件語に対し一
致不一致の情報を記憶するレジスタと、該データの条件
部となる全条件語が現在までに入力された検索キーのい
ずれかと一致したか判別する回路とを備えたことを特徴
とする複合連想メモリ。
In an associative memory that reads necessary data based on a match or mismatch between a search key and stored content, there is a register that stores information on matches or mismatches for multiple condition words that are comparison targets of a search key for one read data; A complex associative memory comprising a circuit for determining whether all condition words serving as a condition part match any of the search keys input so far.
JP60016523A 1985-02-01 1985-02-01 Compound associative memory Expired - Lifetime JPH0743942B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60016523A JPH0743942B2 (en) 1985-02-01 1985-02-01 Compound associative memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60016523A JPH0743942B2 (en) 1985-02-01 1985-02-01 Compound associative memory

Publications (2)

Publication Number Publication Date
JPS61177700A true JPS61177700A (en) 1986-08-09
JPH0743942B2 JPH0743942B2 (en) 1995-05-15

Family

ID=11918630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60016523A Expired - Lifetime JPH0743942B2 (en) 1985-02-01 1985-02-01 Compound associative memory

Country Status (1)

Country Link
JP (1) JPH0743942B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5129074A (en) * 1988-09-22 1992-07-07 Hitachi Vlsi Engineering Corporation Data string storage device and method of storing and retrieving data strings
JPH0531610U (en) * 1991-10-14 1993-04-27 茂 戸上 Bracelet handicraft set
US7124200B2 (en) 2000-09-28 2006-10-17 Fujitsu Limited Routing apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5129074A (en) * 1988-09-22 1992-07-07 Hitachi Vlsi Engineering Corporation Data string storage device and method of storing and retrieving data strings
JPH0531610U (en) * 1991-10-14 1993-04-27 茂 戸上 Bracelet handicraft set
US7124200B2 (en) 2000-09-28 2006-10-17 Fujitsu Limited Routing apparatus

Also Published As

Publication number Publication date
JPH0743942B2 (en) 1995-05-15

Similar Documents

Publication Publication Date Title
KR890004994B1 (en) Address translation control system
US3949369A (en) Memory access technique
JPS61210477A (en) Vector type association memory system
JPS61177700A (en) Composite association memory
US4456976A (en) Associative memory system
US4488260A (en) Associative access-memory
US4982379A (en) Semiconductor memory device having associative function
KR960015231A (en) Enhanced Addressing Method and System
JPS60211540A (en) Data retrieval circuit
US4929938A (en) Area searching system
JPH09506446A (en) Accelerated rule evaluation method in fuzzy inference processor and apparatus for implementing the method
JP3583799B2 (en) Method of using associative memory and associative memory
JPS6214919B2 (en)
JP2558821B2 (en) Associative memory device
JP2656538B2 (en) Address translation device
RU2006939C1 (en) Device for information search with literal matching
JP3059209B2 (en) Associative memory
JPH01106138A (en) Associative memory
JPH07271816A (en) Contents address type memory
JPH04101272A (en) Data element retrieving method
JPS59207477A (en) Semiconductor memory
JPS60211541A (en) Data retireval circuit
JPS59116991A (en) Associative memory
JPS60147838A (en) Data retrieving device
JPS63244496A (en) Memory with content addressing