JPS61164339A - Data decoder - Google Patents

Abstract

PURPOSE:To constitute a data decoding system not participating in waveform distortion by decoding independently a leading edge or a trailing edge of a binary-coding signal respectively and using two kinds of decoding data as an information source so as to obtain the decoded data by logical means. CONSTITUTION:A binary-coding signal is given to a rise signal detection circuit 2 and a fall signal detection circuit 5. A data demodulating circuit 4 uses an output of the circuit 2 to demodulate the 1st decoded data based on the 1st decoding clock given from a phase synchronizing circuit 3. A data demodulation circuit 7 used an output of the fall signal detection circuit 5 to demodulate the 2nd decoding data based on the 2nd decoding clock signal from a phase synchronous circuit 6. A latch 9 latches the 1st and 2nd decoded data supplied from an OR circuit 8 bad on the 2nd decoding clock signal and outputs a demodulated data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data decoding device, and in particular, the present invention relates to a data decoding device that converts a binary data string into an NRZ I modulation method (N on Return
.

7ero ■nverted ) or N, RZL (
(NonReturn to zero 1 level)
The signal is modulated by a modulation method, recorded and reproduced in a predetermined transmission system such as an optical disk device or a magnetic disk device, and based on the reproduced signal, the original NR is returned without error.
The present invention relates to a data decoding device that decodes ZI data or NRZL data.

[Prior Art] In recent years, write-once optical disk devices and magnetic disk devices have been developed and put into practical use as devices for recording and reproducing large amounts of data. Also, a CD device (Compact Qlsc) that digitizes and plays audio signals.
has been put into practical use.

Here, a write-once optical disk device will be described as an example of an application HW related to the present invention, but the present invention can be applied to a wide range of devices such as erasable optical disk devices or magnetic disk devices.

FIG. 2 is a diagram showing recording bits on a disc in a conventional optical disc device, and FIG. 3 is a waveform diagram of each method for modulated data.

First, in FIG. 2, P is the track spacing, d is the minimum bit diameter, and T is the minimum spacing between recording bits. The bits in track 1 have the same recording bit shape and are called RZ recording (Return 7-era) bits. On the other hand, the recording bit shape of the bits in track 2 is different for each bit, which is NRZ recording (Non R
It is called the turn to zero) bit. The RZ system or NRZ system is a recording system for digitally modulated data, and this recording system will be explained with reference to FIG.

As shown in FIG. 3(b), the RZ method generates a pulse with a width of "1n" using digitally modulated data.The NRZ method generates a pulse with a width of "1n" as shown in FIG. 3(l and (d)). Divided into NRZI method and NRZL method.NR
In the Z1 method, the polarity is inverted at "1", and in the NRZL method, the data polarity corresponds directly to the signal level. As can be understood from FIG. 3, in the RZ method, only the rising edge of the data signal has information indicating data "1", whereas in the NRZ method, the rising edge and the falling edge of the data signal have information indicating the data "1". Both have information indicating "1".

FIG. 4 is a diagram showing recording bits of each method for MFM*gll data. As shown in FIG. 4(b), M
As explained in FIG. 3 above, the FM (Modified FM) modulation data becomes a recording signal of the RZ method shown in FIG. 4(C) and the NRZ I method shown in FIG. 4(e), When the polarity of the recording signal is high, a bit is formed on the disk.

On the other hand, in the above-mentioned FIG. 2, if the minimum bit interval T is determined by the minimum bit shape d, then generally T''
r2d ), the minimum bit interval in the RZ method is TO, and in the NRZI method it is 2To.

When d is the same, the NRZI method allows writing at twice the data transfer speed as the RZ method, and doubles the recording density. However, a drawback of the NRZ method is that the shape of the bit is very important because both the leading edge and the invasive edge of the bit have information necessary for decoding. In FIG. 4, the decodable detection window width of each method is ±0.
25T.

It is.

FIG. 5 is a diagram showing reproduction signals and detection signals for recorded pits. Next, with reference to FIG. 5, a reproduced waveform of bits recorded on an optical disc and distortion of detected data will be explained. FIG. 5(a)' shows recording bits of the RZ system, and the reproduced waveform of each bit becomes the Gaussian distribution waveform shown by the solid line in FIG. 5(b), and the continuous reproduced waveform becomes the waveform shown by the dotted line. This waveform is set to a predetermined level Vo
When the level is discriminated by , the detection signal shown in FIG. 5(C) is obtained. This detection signal is distorted due to the asymmetry of the leading and trailing edges of the recorded bits, and the detection signal has a phase distortion of ΔT1 with respect to the recorded signal. However, since RZ decoding uses only information corresponding to the leading or trailing edge of a bit, as described above, this type of distortion does not cause errors.

On the other hand, as shown in Fig. 5(d), the reproduced waveform of bits recorded using the NRZ method becomes the dotted line shown in Fig. 5(e), and the detection signal becomes as shown in Fig. 5(f). , is detected with a width of T2+ΔT2 with respect to the time width T2 of the recording signal. In this case, ΔT2 is the detection signal (Fig. 5 (t
)) becomes an error factor during NRZ decoding.

FIG. 6 is a diagram showing the decoding timing of the NRZ I method. FIG. 6(a) shows a recorded NRZ signal, in which the inversion section has the correct time, for example, the bit length To. FIG. 5(b) shows a reproduction detection signal, and it is assumed that this pit length is detected as To+ΔTo. In decoding, edge signals (Fig. 6 (C)) of rising and falling parts are created from the detection signal (Fig. 6 (b)), and a decoding clock signal (Fig. 6 (C)) whose phase is synchronized with this edge signal C is generated. (d)). A loop is formed between the clock signal d and the edge signal e so as to minimize the phase error. Therefore, the phase error between the edge signal C of the detection signal and the demodulated clock signal d ideally has a value of ΔTo/2. The detected data is one period (sixth
If the edge signal C is present within the decoding window width of 1 square in FIG.

As can be understood from FIG. 6, when the reproduction signal does not correctly detect the leading edge of the bit and the edge of the bit, or when the discrimination level changes due to DC fluctuations in the reproduction signal, a duty change occurs in the detection signal. Playback data errors are more likely to occur.

The duty change of this detection signal largely depends on the recorded pit shape. On the other hand, the bit shape during recording largely depends on the current characteristics of the laser diode and the medium characteristics. In order to record bits correctly, the recording current power of the laser diode must be controlled by the track system of the disk.
Precise pricking is required, and generally as the temperature rises, the quantization efficiency of the laser diode decreases and the amount of current must be increased. The reality is that it is difficult to always form optimal NRZ waveform bits on the disk, including the increase in the amount of control system hardware for this purpose.
*It is. For this reason, write-once optical disc devices that have been announced or are currently on the market do not use NRZ recording, but instead use the R2 system.

[Problems to be Solved by the Invention] As mentioned above, the NRZ recording method has the advantage of approximately doubling the amount of recorded data compared to the RZ recording method, but the difference between the leading and trailing edges of recording bits is There is a drawback that a phase error occurs in the reproduced detection data, resulting in a data error.

Therefore, the main object of the present invention is to provide a data decoding device that is less susceptible to waveform distortion even when recording NRZI or NRZL.

[Means for Solving the Problems] This invention provides that the binary data string is modulated by NRZI modulation or NRZ modulation.
A data decoding device that decodes a reproduced signal transmitted after being L-modulated into original NRZI or NRZL data,
The binarization means level-discriminates the reproduced signal to output a binary signal, and the first data generation means outputs a first decoded data string using only the leading edge signal of the binarization signal as information data. Further, the second data generating means outputs a second decoded data string using only the trailing edge signal of the binary signal as information data. Then, based on the first decoded data string and the second decoded data string, the logic means converts the original NRZ
Obtain I or NRZL decoded data.

More preferably, the first decoded data string and the second decoded data string are written in separate memories, and during playback, the addresses are determined using the same clock signal and the data in the two memories are output, and the summed data is NRZ I or NRZ
It may be output as L data.

[Operation] In this invention, even if a recorded bit becomes larger or smaller than a normal bit, a signal that captures only its leading edge is not distorted, and a signal that captures only its trailing edge is not distorted. Using the fact that there is no NRZ of the detection signal
When decoding, if a first decoded data string is created using only the 111 detection signal and a second decoded data string is created using only the trailing edge signal, the obtained data sequence is the sum of the summed signals. becomes the NRZ signal to be decoded. Therefore, according to the present invention, the influence of the phase distortion of the detection pulse caused by the phase distortion occurring at the leading edge and the trailing edge of the reproduction detection pulse or the w4 difference in the discrimination level when detecting data can be eliminated, and the conventional RZ recording method can be eliminated. It becomes possible to decode data with a reproduction phase distortion approximately equal to
There is no increase in the reproduced data error rate, and the amount of data recorded by the device is approximately doubled.

[Example] FIG. 7 is a diagram for explaining the present invention in detail,
FIG. 4 is a reproduction signal waveform diagram with respect to distortion of recorded bits. 7th
Figure (a) shows the recorded waveform, Figure 7 (b) shows normal recorded bits, Figure 7 (e) shows small recorded bits, and Figure 7 (h) shows large recorded bits. Showing bits. In addition, Fig. 7 (0), <f ), (1
) are the reproduction signals of each bit, respectively, and Fig. Wi7 (d
), (g>.

(J) are detection signals, respectively. As is clear from FIG. 7(d), the detection signal d has no phase distortion, and the detection width of bit ■ is T1. On the other hand, the widths of the bits shown in FIG. 7(e) are T, −ΔT, and −ΔT2, and the widths of the bits shown in FIG. 7(h) are T, −ΔT, and −ΔT.
, +ΔT.

Therefore, as mentioned above, in the conventional NRZ system, tl
With respect to the iijl clock, the waveform shown in FIG. 7(e) causes an lI-toned mother-gin loss of (ΔT1+ΔT2)/2, and the waveform shown in FIG. 7(h) produces (ΔT, +ΔT,)/
This results in a 1m margin loss of 2 and increases data errors.

On the other hand, the rising signal interval and falling signal interval of the detection signals in FIGS. 7(a) and (J'') are TI+T2 and T2+T a, respectively, and no distortion of the reproduced waveform occurs.Therefore, , when data is decoded using only rising signals or falling signals, decoding is performed without phase distortion.

Now, is it 1st L? =NRZL signal “11100001
10” (NRZ! signal is 100100010
1”), the first using only the decoded rising signal.
The decrypted data “i oooo.

0100", and the second decoded data using only the falling signal is "ooooioooooi". However,
The temporal phases of the first and second decoded data are not synchronized. For this reason, the first decoded data and the second decoded data are written to independent memories as shown in FIG. When read out and added together, the itching signal becomes the original NRZI signal. Also, the first
When the flip-flop is set with the decoded data of 1 and the flip-70 is reset with the second decoded data, the output of the flip-flop becomes the NRZL signal.

On the other hand, if the time phase difference between the first decoded data and the second decoded data is smaller than the decoding window width, the first decoded data and the second decoded data can be added without using the above-mentioned independent memory. Similar results can be obtained by using a decoded NRZl signal as the signal and using a clock signal created from either or both of the first decoded data and second decoded data clock signals as the decoded clock signal.

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

First, the configuration of an embodiment of the present invention will be described with reference to FIG. A reproduced signal from the optical disk device is applied to a comparator circuit 1 as a binarization means. This comparator circuit 1 discriminates the level of the reproduced signal at a predetermined level and outputs a 211 signal. The binarized signal whose level has been discriminated by the comparator circuit 1 is applied to a rising signal detecting circuit 2 and a falling signal detecting circuit 5. The rising signal detection circuit 2 detects the rising portion of the signal 21 and outputs the rising signal.
The falling signal detection circuit 5 detects the falling portion of the binary signal and outputs a falling signal. The rising signal output from the rising signal detection circuit 2 is given to a phase synchronization circuit 3 and a data demodulation circuit 4. The phase synchronization circuit 3 generates a first decoding clock signal synchronized with the rising signal. The first decoded clock signal generated from this phase synchronization circuit 3 is given to a data demodulation circuit 4. The data demodulation circuit 4 demodulates the first signal data using the output of the rising signal detection circuit 2 based on the first decoded clock signal given from the phase synchronization circuit 3. The first decoded data demodulated by the data demodulation circuit 4 is given to an OR circuit 8.

On the other hand, the falling signal output from the falling signal detection circuit 5 mentioned above is given to a phase synchronization circuit 6 and a data demodulation circuit 7. The phase synchronization circuit 6 generates a second decoding clock signal synchronized with the falling signal. This second
The decoded clock signal is applied to the data demodulation circuit 7, and is also inverted by the inverter 10 and applied to the clock pulse input terminal of the latch 9. The data demodulation circuit 7 demodulates second decoded data from the falling signal detected by the falling signal detection circuit 5 based on the second decoded clock signal from the phase synchronization circuit 6. The second decoded data demodulated by this data demodulation circuit 7 is OR
is applied to circuit 8.

The OR circuit 8 adds the first and second decoded data output from the data demodulation circuits 4 and 7, respectively, and provides the added output to the latch 9. The latch 9 latches the first and second decoded data given from the OR circuit 8 based on the first decoded clock signal, and outputs demodulated data.

Note that the first decoded clock signal inverted by the inverter 10 is output as a demodulated clock signal.

FIG. 9 is a time chart for explaining the operation of FIG. 1. Next, with reference to FIG. 1 and FIG. 9, a specific operation of an embodiment of the present invention will be described. FIG. 9(a) shows the original data string, and considering the case where it is subjected to MFM*II, the NRZ 1 waveform of the MFM modulated signal becomes as shown in FIG. 9(b). This signal is recorded on the optical disk, reproduced, and applied to the comparator circuit 1.

The comparator circuit 1 discriminates the level of the reproduced signal at a predetermined level and outputs a level discrimination signal shown in FIG. 9(C). This level discrimination signal C has a data m interval different by ΔTo due to waveform distortion compared to the recording signal S. This level discrimination signal C is given to a rising signal detection circuit 2 and a falling signal detection circuit 5, respectively. . The rising signal detection circuit 2 detects the rising portion of the level discrimination signal and outputs the rising signal d shown in FIG. 9(d).

On the other hand, the falling signal detection circuit 5 detects the falling portion of the level discrimination signal C, and generates a falling signal @ shown in FIG. 9(g).
Output a. The rising signal d output from the rising signal detection circuit 2 is given to the phase locking circuit 3, and the phase locking circuit 3 is synchronized with the rising signal d (Fig. 9<8).
A first decoded clock signal e shown in FIG. On the other hand, the phase synchronization circuit 6 similarly outputs the second decoding clock signal shown in FIG. 9 (IT) in synchronization with the falling signal Q.

Based on the first decoded clock signal e, the data demodulation circuit 4 demodulates the first decoded data f shown in FIG. 9(f) using a rising signal. Similarly, the data demodulation circuit 7 generates a falling signal σ based on the second decoded clock signal.
Accordingly, the second decoded data 1 shown in FIG. 9(1) is output. The decoded data f,: is applied to the latch 9 via the OR circuit 8. The latch 9 latches the data based on the second decoded clock signal whose polarity has been inverted by the inverter 10, and v! 111 data j is output.

Note that in the embodiment shown in FIG.
, h is smaller than the decoding margin ±To/4 (T; the bit interval of the original data), and
If the phase difference between decoded clock signals e and h is large, the embodiment shown in FIG. 8 may be applied.

FIG. 8 is a schematic block diagram of another embodiment of the invention. First, the configuration will be explained with reference to FIG. The first signal output from the phase synchronization circuit 3 shown in FIG.
The decoded clock signal e is applied to the counter 11 and the memory 16. The counter 11 receives the first decoded clock signal e.
, and generates a write address signal for designating the write address of the memory 16. The write address signal output from this counter 11 is given to a selector 14. Further, the first decoded data f from the data demodulation circuit 4 shown in FIG. 1 is given to the memory 16. Similarly, the second decoded clock signal output from the phase synchronization circuit 6 shown in FIG.
7 and given. The counter 12 counts the second decoded clock signal g and outputs a write address signal for designating the write address of the memory 17. This write address signal is applied to selector 15. Further, the second decoded data 1 from the data demodulation circuit 7 shown in FIG. 1 is given to the memory 17.

Furthermore, the successive clock signals are sent to the counter 13 and the memory 16.
and 17. Counter 13 is memory 16 and 1
A successive address signal for designating each of the 7 read addresses is output. This read address signal is applied to selectors 14 and 15. The selector 14 selects the write address signal outputted from the counter 11 and the read address signal outputted from the counter 13 based on the R/W signal, and applies the selected signals to the memory 16. Further, the selector 15 selects either the write address signal from the counter 12 or the read address signal from the counter 13 based on the R/W signal and applies the selected signal to the memory 17. Memory 16.
The decoded data read from 17 is outputted as demodulated data via OR circuit 18.

Next, the operation will be explained. At the time of writing, the selector 14 selects the write address signal from the counter 11 and the selector 15 also selects the write address signal from the counter 12 according to the R/W signal.

At this time, the memories 16 and 17 are each in recording mode. Then, the first decoded data f is written into the memory 16, and the second decoded data 1 is written into the memory 17. At the time of reading, selectors 14 and 15 each select a read address signal from counter 13 according to the R/W signal. Then, each of the memories 16 and 17 enters the read mode, and the first and second decoded data are read out in synchronization with the read clock signal. The first decoded data read from memory 16 and the second decoded data read from memory 17 are outputted via OR circuit 18.

Note that when the recorded data is generally composed of frames, the R/W signal is switched in units of reproduced frames, and by providing a circuit section 2111 similar to that shown in FIG. 8, continuous reproduced data is switched as a signal. It becomes possible to do so.

[Effects of the Invention] As described above, according to the present invention, the leading edge or the sliding door edge of a binarized signal is independently decoded, and the two types of decoded data are used as information sources to perform logical means. Compared to conventional optical disk devices, where distortion of the recorded bits causes waveform distortion of the reproduced signal, which forced recording using RZ recording, NR2 recording allows for faster recording and recording. playback becomes possible. In this case, it is possible to configure a data decoding method that does not involve waveform distortion, and as a result, it is possible to improve the recording density on the disk by about twice that of the RZ recording method. Become.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a diagram showing recording bits on an optical disc. FIG. 3 is a waveform diagram of each method for modulated data. Fourth
The figure shows recording bits of each method for MFM modulation data. FIG. 5 is a diagram showing reproduction signals and detection signals for recorded bits. FIG. 6 is a diagram showing the decoding timing of the NRZ I method. FIG. 7 is a reproduction signal waveform diagram with respect to distortion of recorded bits. FIG. 8 is a schematic block diagram of another real mm according to the present invention. FIG. 9 is a time chart for explaining the operation of FIG. 1. In the figure, 1 is a comparator circuit, 2 is a rising signal detection circuit, 3 and 6 are phase synchronization circuits, 4.7 is a data demodulation circuit, 5 is a falling signal detection circuit, 8 is an OR circuit, 9 is a latch, 11. 12.13 is a counter, 14.15 is a selector, and 16.17 is a memory. Agent Masu Oiwa Male tiger
7 Sugar 2 Figure 10 Congee 3 Figure 4 Pi ← Figure 6

Claims (4)

[Claims] (1) A reproduced signal in which a binary data string is NRZI modulated or NRZL modulated and transmitted is converted to the original NRZI or NRZL modulated signal.
A data decoding device for decoding into RZL data, comprising: 2 which discriminates the level of the reproduced signal and outputs a binary signal;
digitization means; first data generation means for outputting only the leading edge signal of the binarized signal binarized by the binarization means as information data of a first decoded data string; 2
a second data generation means for outputting only the trailing edge signal of the digitized binary signal as information data of a second decoded data string; and an output of the first data generation means and the second data generation means. The original NRZI or NRZL based on the output
A data decoding device, comprising logical means for obtaining decoded data. (2) The first data generation means includes a leading edge detection means for detecting a leading edge portion of a binarized signal binarized by the binarized signal, and a leading edge portion outputted from the leading edge detection means. a first phase synchronization means that outputs a first clock signal synchronized with the edge signal; and an RZ signal from the leading edge detection means based on the first clock signal output from the first phase synchronization means. a first demodulating means for demodulating, and the second data generating means includes: trailing edge detecting means for detecting a trailing edge of the binarized signal binarized by the binarizing means; and the trailing edge a second phase synchronization means for outputting a second clock signal synchronized with the trailing edge signal output from the detection means; and second demodulation means for demodulating the RZ signal from the output of the edge detection means.
The data decoding device described in section. (3) The logic means includes: an addition means for adding the output of the first data generation means and the output of the second data generation means and outputting the result as decoded data; and the first decoded data string or the second data generation means. Claim 1 includes means for outputting a clock signal created to generate a decoded data string as a decoded clock signal.
The data decoding device described in Section 1. (4) The first data generation means includes a first storage means for storing the leading edge of the binarized signal detected by the leading edge detection means, and the second data generation means is configured to store the leading edge of the binarized signal detected by the leading edge detection means. a second storage means for storing the trailing edge of the binarized signal detected by the edge detection means, and further for adding and reading the contents stored in each of the first and second storage means. 3. A data decoding device according to claim 2, comprising means for generating a clock signal.