JPS61156310U

JPS61156310U -

Info

Publication number: JPS61156310U
Application number: JP3879885U
Authority: JP
Priority date: 1985-03-20
Filing date: 1985-03-20
Publication date: 1986-09-27

Description

[Brief explanation of the drawing]

第２図は従来のＰＬＬ変調回路の構成図、第１
図は本考案の一実施例のＰＬＬ変調回路の構成図
、第３図は本考案の他の実施例の同上構成図であ
る。１：ＴＣＸＯ（温度補償水晶発振器）、２：固
定分周器、３：位相比較器、４：ループフイルタ
、５：ＶＣＯ（電圧制御発振器）、６：音声変調
信号、７：可変分周器、８：分周指定データ、９
：ＡＧＣ（電圧制御利得可変）増幅器、１０：Ｖ
ＣＯ５の周波数変調端、１１：Ｄ／Ａ変換器。 Figure 2 is a configuration diagram of a conventional PLL modulation circuit;
The figure is a block diagram of a PLL modulation circuit according to one embodiment of the present invention, and FIG. 3 is a block diagram of another embodiment of the present invention. 1: TCXO (temperature compensated crystal oscillator), 2: fixed frequency divider, 3: phase comparator, 4: loop filter, 5: VCO (voltage controlled oscillator), 6: audio modulation signal, 7: variable frequency divider, 8: Frequency division specification data, 9
:AGC (voltage controlled gain variable) amplifier, 10:V
Frequency modulation end of CO5, 11: D/A converter.

Claims

[Scope of utility model registration request]

In a PLL modulation circuit that applies an audio modulation signal to a voltage-controlled oscillator used in a frequency synthesizer of a wireless device to perform FM modulation, a voltage-controlled variable gain amplifier is disposed on the input signal line of the audio modulation signal, and connecting the output end to the audio modulation end of the voltage controlled oscillator, and connecting the gain of the amplifier to the input signal to the frequency modulation end of the voltage controlled oscillator;
Alternatively, a PLL modulation circuit characterized in that the PLL modulation circuit is controlled by frequency division number designation data of a variable frequency divider that divides the oscillation output of the voltage controlled oscillator.