JPS61152174A - Digital ghost eliminating device - Google Patents

Abstract

PURPOSE:To reduce the number of taps to obtain television signals of good S/N by changing the delay time of an input signal by a variable delay circuit to add the input signal to a ghost signal and using a digital equalizing circuit to eliminate a ghost. CONSTITUTION:A variable delay circuit 211 changes the delay time of the input signal of a terminal I1 and outputs the delayed inputs signal to a terminal 01, and a digital transversal filter 212 of input summation type consists of unit time delay elements connected between adders which are connected to plural tap coefficient devices, whose input terminals are connected commonly, and output terminals of coefficient devices respectively. Gain values of tap coefficients of the filter 212 and the delay time of the circuit 211 are stored in a memory 214. An adder 213 operates the sum of the output of the filter 212 and the input signal of a terminal I2 and outputs the result to a terminal 02. Thus, the number of taps is reduced to simplify a device with respect to hardware, and television signals of good S/N where the failure in erasing of ghost is lessened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a ghost removal device for automatically removing television ghosts, and more particularly to a digital ghost removal device that digitally removes ghosts.

[Technical background of the invention]

Devices that automatically and digitally remove television ghosts using equalization circuits are known in the art.

An example is shown in FIG.

The details of this configuration and operation are described in Reference 1 (Murakami et al., "Digital Ghost Automatic Eraser", Institute of Electronics and Communication Engineers Technical Research Report EMCJ78-37, November 1978), and an outline thereof is shown below. This device is entirely digitalized, and a digital video signal containing ghosts is input to an equalization circuit 2 via an input terminal 1. As shown in FIG. 4, this equalization circuit 2 consists of N0M unit delay elements 201 (delay time T
It is composed of +1 tap coefficient units 202 (digital multipliers), an adder 203 for adding together the outputs of each tap coefficient unit, and a tap gain memory 204. The tap coefficients (C-M-CN) of this tap coefficient multiplier are set to appropriate values by the control circuit 3, and a digital video signal from which ghosts have been removed is outputted to the output terminal 5.

The reference signal for removing ghosts is the differential waveform (b) of the trailing edge (,) of the vertical synchronization signal shown in FIG. The peak corresponding to the falling portion of the trailing edge of the vertical synchronization signal is set as time reference 0, and each peak di after this time reference is detected.

The sign of this differential value di corresponds to whether the residual ghost having the delay time iT is positive or negative. Therefore, the tap gain correction circuit 31 uses this differential value d1 to sequentially correct each tap gain according to the following equation.

CI, new=cl, old-64fndI (1=-
1d~N, t4o)++++++(2) Here, Ci,
old is the tap gain before correction, C4, new is the tap gain after correction, Δ is a small positive correction coefficient, (2)
The formula is widely known as the Zero Forcing method. In addition, the center tap coefficient 6 is Co〒1
River... (3) K is fixed. Ghosts are removed by performing this sequential correction every time a vertical synchronization signal arrives (t"70 seconds). The sequence controller 4 controls the sequence of the above-mentioned control circuit 3, and includes, for example, a ROM It can be configured using

Additionally, a device for eliminating ghosts using a combination of fixed delay circuits and a transversal filter is also known (1985-158579).

[Problems with background technology]

However, in the conventional digital ghost removal device as described above, a large number of coefficient units (multipliers) are required to perform sufficient ghost removal, and the general-purpose digital multipliers used for these coefficient units are expensive. Moreover, because of its large scale (one multiplier is one IC), a practical ghost removal device could not be obtained. on the other hand,
Although an analog equalization circuit using a ccD has been put into practical use as a ghost removal device, it has problems in terms of residual noise and S/N ratio.

To explain the above problem more specifically, even if we use digital IC technology, which has made rapid progress in recent years,
CE can only integrate about 10 multipliers at most. This is because an 8-bit x 8-bit multiplier is required as a coefficient unit for a transversal filter for ghost removal, and at the latest technology level, a 16-bit x 8-bit multiplier is required.
The 16-bit OCMO8 multiplier is 3.5m x 5.0- (Reference 2: Yoshilo Kajageto 45ns
16 X 100MO8MultlpHsr″l8S
CC84WPM8.1) Therefore, on an IC chip with a practical chip size of 7m x 7m, 8bl x 8bi
The cMbs multiplier for t is -Y and 2, mutually, 11''39,
3 ・・・・・・(4) 3.5×5 8
8, it is possible to accumulate about 9 pieces.

The delay range of ghosts that can be removed by the N-tap transversal filter is NT (T is the sampling period, T = fsc, -1, (fsc (color sub-gear frequency: 3.58 MHz)). , N = 10. T = 70ns ~1
00ns, N T = 0.7 μs ~1
/J - (5), and this alone was insufficient as a transversal filter for ghost removal. Therefore, the equalization circuit used in the ghost removal device that has already been put into practical use is
Murakami et al. “Ghost Clean System” Toshiba Shiviem
1.38 Nu 7 June 1982),
A CCD (Charged Coupled Device) using a sparse filter was used. However, since this is an analog signal processing device, the linearity of the coefficient unit (multiplier) and the overall 87N are insufficient. This drawback, when viewed as a ghost removal device, has led to an increase in ghosts remaining on the screen and a decrease in S/N.

Also, the technique of the above-mentioned Japanese Patent Application Laid-Open No. 56-158579 was used.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and is a digital ghost removal method that does not require a large number of coefficient units and has sufficient ghost removal performance to withstand practical use in terms of cost and hardware. The purpose is to provide a device and a digital equalization circuit that is necessary and essential for this device.

[Summary of the invention]

According to the present invention, even in a transversal filter having a large number of taps, only a few taps need to change the gain etc. to actually remove ghosts, and the other taps are necessary to match the times of the real signal and ghost signal. This was done by focusing on the fact that it is only a .

Then, ghost removal is actually performed using an input-weighted digital transversal filter.

If there are a plurality of ghosts, the ghosts are removed using a plurality of digital equalization circuits having the variable delay circuit and the digital transversal filter as main components, and further having a memory and an adder.

A first invention of the present application is a digital equalization circuit using an input weighted digital transversal filter and having the above configuration.

Further, a second invention uses this digital equalization circuit, and further includes a subtracter whose first input is a television signal including a ghost, and whose output is a signal obtained by subtracting a second input from this input. The output of the subtracter is input to the first input terminal of the first-stage digital equalization circuit, and the output of the first output terminal of the previous stage is input to the first input terminal of the subsequent-stage digital equalization circuit. Alternatively, the outputs of the subtracters described above are input in parallel to the first input terminals of each digital equalization circuit, and the outputs of the second output terminals of the subsequent stages are sequentially input to the second input terminals of the previous stage. The output of the second output terminal is configured to be the second input of the subtracter.

〔Effect of the invention〕

The present invention has a variable delay circuit that appropriately changes the time of the input signal to match it with the ghost signal, thereby providing a digital equalization circuit that requires a small number of taps in the digital transversal filter.

Moreover, since the ghost removal device of the present invention is configured using the above-mentioned digital equalization circuit, the total number of taps is small, the cost is low, the hardware is not so complicated, and there is no residual noise. A sufficiently practical digitized ghost removal device is obtained which can obtain a television signal with a good ratio of 8/N.

The second aspect of the present invention uses an input-weighted digital transversal filter, and has the advantage that each first adder can be configured as one output using two inputs, making the configuration easy.

Furthermore, by adding a digital equalization circuit, a device with high ghost removal performance that can also remove grandchild ghosts can be obtained.

[Embodiments of the invention]

Hereinafter, the present invention will be explained using the drawings. FIG. 1 shows an embodiment of the digital equalization circuit of the present invention, and FIG.
This is an example of a digital ghost removal device configured using the example.

In FIG. 2, a digital video signal containing ghosts is input to one of the subtracters 29 in the equalization circuit. The output of the subtracter 29 is input to the output terminal 5 and the differentiation circuit 33 in the control circuit 3, and is also input to the digital equalization circuit (
Hereinafter, it will be referred to as an equalization unit. ] 21 is inputted to the first input terminal Che 1, and the equalization unit 2 i (i=1.2.3
) of the equalization unit 2 j (j
=i+1. i=1.2.3) first input terminal IIK
Connecting. The second input terminal I2 of the equalization unit 24 is
It is grounded and O is input. Further, the second output terminal 02 of the equalization unit 21 (i==4.3.2) is
Equalization unit 2J (j=quantity -1+ + ==4.3e
2), and the second output terminal o2 of the equalization unit 21 is input to the other input terminal of the subtracter 29.

The equalization units 21 to 24 all have the same configuration, and the configuration is shown in FIG. The first input terminal 11 of the equalization unit 21 is input to the variable delay circuit 211, and is connected to one input terminal of the switch S1 and the other input terminal of the switch S1 via a delay element D1 having a delay amount T. Ru. The output terminal of the switch S1 passes through the input terminal of the switch S2 and a delay element D2 having a delay amount of 2T.
20 connected to other input terminals. From now on, repeat the same process until 82. D3.83. D4.84. D5
．． 85 is connected. Here, each delay element DI is composed of a shift register or a latch connected in one measurement column.

Therefore, switch! 3i (i=1.....5)
is set by false in the delay amount memory DL of the equalization unit memory 214, thereby constructing a variable delay circuit that provides an arbitrary delay (in T increments) from 0 to 31T.

The output of switch S5 is input to delay circuit 216.

The purpose of this delay circuit 216 is to align the delay times of the signals applied by the switches 81 to S5 with the clock time TK.

The output of the delay circuit 216 is connected as the output of the variable delay circuit 211 to one input of a digital multiplier 2122 which is a tap coefficient unit of each weighting circuit 220 in the digital transversal filter 212. Other inputs are connected to tap gain memories C1-C5 of equalization unit memory 214. The output of the multiplier 2122 is input to the adder of each tap of the tapped delay circuit 221, and each input signal is
The delay and addition are repeated and output to the adder 213.

That is, the output of the final stage has the delay amount given by the variable delay circuit 211 as an offset, and is the output of a digital filter with a variable tap number of 5 given by the transversal filter 212.

The output of this transversal filter 212 is applied to the second input terminal I2 of the equalization unit 21 in an adder 213.
The output signal of the equalization unit 22 obtained from the delay circuit 2
It is added to the signal delayed by 18° and input to the delay circuit 215. The purpose of these two delay circuits 215 and 218 is to align the delay times of the input signal from the input terminal and the output signal from the transversal filter 212 to the clock time T.

The output from the delay circuit 215 is the second output of the equalization unit 24.
It is connected to the output terminal 821 of. That is, the output signal obtained from the second output terminal η2 of this equalization unit 21 is
Each equalization unit) 24.23.22.21 becomes the ghost cancellation signal generated at 21 and is connected to the other input terminal of the subtracter 29.

Further, the output of the variable delay circuit 211 of the equalization unit 21 becomes the input of the delay circuit 2170, and is delayed by 2T time.
It is output to the first output terminal 01.

The first output terminal 01 of the equalization unit 21 is connected to the first input terminal II of the equalization unit 22, and the output of the first output terminal 01 of the equalization unit 21 is connected to the first output terminal II of the equalization unit 22. By delaying the output by 2T time, the delay circuit 216 and the delay circuit 215 of the variable delay circuit of the equalization unit 22 are delayed by the delay circuit 21B of the equalization unit 21 and the digital transversal filter 212 of the equalization unit 21. When the maximum time delay (5T time) can be compensated and one or more equalization units are connected, the minimum interval between taps at the connection point is determined by the delay time of the ghost removal signal from each tap of Tt ~ ( R+4)
・If T is the minimum interval between the equalization units in the 1st stage and the (t+1)th stage, then the delay time of the ghost removal signal of each tap in the 1st stage (I+1) is (R+3)・T ~ (R+7)T
becomes. By the way, delay circuits 218 and 215 are inserted between the second input terminal of the equalization unit - check 2 and the second output terminal 02, and the ghost removal signal of the first stage equalization unit is sent to the subtracter. By the time it is input to 29, (2I-
The ghost removal signal of the equalization unit of the (I+1)th stage is delayed by (2I+1)·7 hours.

As a result, the delay time of the ghost removal signal from each tag of the first-stage equalization unit input to the subtracter 29 is (
R+2I-1)・T〜(R+2I+3)・T, and (
The delay time of the ghost removal signal from each tap of the equalization unit in the I+1)th stage is (R+2I+4)・T~(R+
2I+8)T and ghosts can be continuously removed even at the connection point of the equalization unit. Also,
The delay circuit 217 may be omitted and the adjustment may be performed using the variable delay circuit 211 at the subsequent stage.

In the embodiment, the minimum delay amount of the variable delay circuit 211 of the equalization unit 24 is T;
The minimum delay amount is not necessarily T due to switches and the like.

Next, in the equalization unit 21, in the case of N=8 +M+Q...
...If the relationship (7) is satisfied, and the delay amount of the variable delay circuit of each equalization unit is minimized, the range of the ghost removal signal from each equalization unit is as follows in the subtracter 29, etc. The minimum delay between the conversion units is T, and ghosts can be removed continuously. Note that instead of formula (7), N)8+M+Q...
. . . The relationship shown in (9) may be satisfied, and in this case, it can be adjusted using a variable delay circuit.

Here, in the first embodiment, FIG. 1 shows the case of , and FIG. 6(a) shows the case except that the delay circuit 218 in FIG. 1 is replaced with the delay circuit 230 and the delay circuit 217 is eliminated. is the case of the same operation as in FIG. Figure 6(b)
In this case, the delay circuit 217 shown in FIG.
adder 23 in the transversal filter
Perform the same operation as in Figure 1 except that it is added by 1,
This is the case. In FIG. 6(c), the delay circuit 217 is removed from the transversal filter 21 in FIG.
The operation is the same as in FIG. 1, except that the number of taps in 2 is now 8 and the minimum delay amount of the variable delay circuit is 6·T.

Next, control of each equalization unit shown in FIG. 1 will be described.

The control circuit 3 controls the equalization unit memory 214 of 21.22.23.24, and the output waveform memory 3 receives the output da of the differentiating circuit 33.
4, a microprocessor 37 that performs judgment and calculations, a ROM 36 that holds its programs, a RAM 35 that holds various data under control, and an equalization unit 21.2.
2, 23, and 24 are connected by an address bus 61 and a data bus 62, respectively. microprocessor 3
7 via the address bus 62,
The chip selector 38 is connected to the output waveform memory 34 and the RAM 3.
5, ROM36 and equivalent chemical knit 21, 22, 23.24
A chip select signal is applied to the chip select signal via a chip select signal path 63. It is shown in the above-mentioned document 3 that ghosts can be removed by controlling the general transversal filter shown in FIG. 4 using such a control circuit.
21, 22, 23, and 24 are shown in accordance with the flowchart shown in FIG.

Normally, the shorter the delay time, the larger the ghost, so here we will describe a simple control that sequentially finds the largest ghost and allocates equalization units. However, if there are large and small ghosts regardless of the delay time, it is sufficient to detect as many equalization units as the number of equalization units starting from the largest ghost, and then allocate equalization units in order from the ghost with the shortest delay time. Such control can also be easily realized using a microprocessor.

That is, the equalization unit register value l indicating that the equalization unit 21 is controlled is set to 1 (block 701).
. Next, the output signal P of the leading edge of the vertical synchronization signal shown in FIG.
A is passed through the differentiation circuit 33 and stored as a differential value dm into the output waveform memory 34 for several seconds (block 702). Next, detect the maximum peak of the differential value d4 shown in FIGS. 5(b) and 5(d), and set the sample timing as the time reference TO (
block 703).

Next, in order to allocate the maximum ghost to the equalization unit 21, 1 is detected in the maximum peak value dTJ21+ of the differential value dA after sample timing T#+5 (block 70
4). Next, the delay amount of the variable delay circuit 211 of the equalization unit 21 is set to (Kl-5)T (Phy 705
). At 1320 o'clock (Kl-Ki-1-5・l) -'
Set to r. Specifically, a chip select signal is issued from the chip selector 38 to the thickening unit 21,
Microprocessor 37 to equalization unit memory 214
The address information indicating the delay amount memory is output, and the microprocessor converts it into a binary number and outputs the value of 9K1-5 to the data bus 62.

In this way, the delay amount memory (DL) value in the equalization unit memory 214 in the equalization unit 21 is converted into a binary number and set to 1-5, and based on that value, the variable delay circuit 211 is 1 so that the delay amount is (Kl-5)TK
Switches 81-85 are set.

Next, the tap gain modification number register <1> is set to l (block 706). Next, just as in block 702, the differential value dA of the output signal 4tta is stored in the output waveform memory 3.
4 (block 707). Since the acquisition start timing at this time is the same, as shown in FIG.
become. Next, each tap gain of the equalization unit 21 is
C5 is modified according to the following formula (block 708).

Cl, new=cj, old+Δ・sgndTl+
1-6+j ・--4143= 1.2.3.4
．． 5 Here, Cl, new is the first tap gain after modification,
CIs old is the first tap gain before correction, Δ is a small positive correction coefficient, sgn dTfIt+ is 1-6+
5 is the sign of the sample value of the differential value d of the output signal y corresponding to 1-6+j at the sample timing T#+. Specifically, the tap gain Cl read out from the equalization unit memory 214 to the microprocessor 37
, old and the differential value dTjlT+ read out from the output waveform memory 34 to the microprocessor 37 by 1-6+j.
are calculated in the micro processor 37 according to Equation 1, and the calculation results Cl, ney are written in the equalization unit memory 214.

Next, the tag gain modification count register CI-) is incremented by 1, in this case to 2 (block 709).

Next, it is determined whether the NTAP has been modified a predetermined number of times (block 710), and if the modification has not been performed the predetermined number of times, the process returns to block 707 and the tag gain is repeatedly modified. Also, if the equalization unit 22 has been used a predetermined number of times, the next equalization unit 22
In order to control the equalization unit register, the equalization unit register (ri) is increased by 1, in this case, to 2 (block 711).Next, it is determined whether the control has been performed for a predetermined number of equalization units (4 in this case). Otherwise, the process returns to block 702 to control the next equalization unit (in this case, equalization unit 22). Also, if it is being done, all controls will be stopped. (block 713)
In this way, during the delay time shown in FIG. 5, the largest ghost f8 of T is removed by the equalization unit 21, and during the delay time, the second largest ghost f of T0 is removed by the equalization unit 22. be done.

Note that the range of delay time of the receivers of equalization units 21 and 22 is 1cKIT-2TIK shown in FIG. 5(c).
IT + 2T) *＾Ba, 'I'-2'l', K,'
r+2T]. In addition, when there are two ghosts in this way, the equalization units 23 and 24 are originally unnecessary, but even if they exist, the maximum peak of the differential value d of the output signal (in this case, the peak of noise) Since equalization is performed centering on each, there is no problem with ghost removal performance.

Further, the length of the variable delay line may be at most the length of (delay time between adjacent ghosts - 51·T), and in this embodiment, the maximum length is 143·T= (34X3+31+3
+4+3) Can remove ghosts up to T length.

In addition, as a variable delay circuit, a RAM as shown in FIG.
The present invention is also effective even if . Note that it is well known to use RAM as a variable delay circuit, but the address counter 2112 is repeatedly counted by the amount corresponding to the delay amount, and the first half of each counter output is stored in the RAM 2.
111 read, and the second half of the second half of the read time is allocated to read). Before the end of the read time, the output data of Ordinary M2111 is sent to the first latch circuit 2114, and in order to synchronize it with the clock, the latch is The circuit 2115 may latch it in synchronization with the clock.

A control generation circuit 2113 generates a read/write pulse for the RAM 2111 and a clock for the second latch circuit 2115. Each timing shown in FIG. 8 is shown in FIG. 9.

By connecting a plurality of digital equalization circuits (equalization units) having the same circuit configuration and having nine digitized ghost removal apparatuses, ghost removal can be effectively performed.

FIG. 10 shows a second embodiment of the digital equalization circuit. This is simply by reversing the connection of the digital transversal filter and variable delay circuit in the first embodiment shown in FIG. The operations and effects other than those used for delay are the same as in the first* embodiment.

FIG. 11 shows a third embodiment of the digital equalization circuit, which has variable delay circuits on both sides of a digital equalization filter. This also has the same operation and effect as the first embodiment, except that the first variable delay circuit is used to extend the equalization unit universal filter connected to the rear.

Furthermore, it is clear that one of the two delay circuits may be a fixed delay circuit.

Further, the number of taps of the digital transversal filter in each unit of the digital equalization circuit according to the present invention, the amount of delay of the variable delay circuit, and the delay range thereof are not particularly limited.

Furthermore, the present invention does not limit the connection method of each equalization unit; for example, as shown in FIG. The present invention is also effective. That is, in this embodiment, the output of the subtracter 29 is input in parallel to the first input terminal of each equalization unit 24.23, 22.21, and the output of the second output terminal 02 of the equalization unit 21 is The output from the second output terminal 02 of the equalization unit 24 at the first stage is input to the second input terminal 02 of the equalization unit 22, and similarly, the output from the second output terminal 02 of the equalization unit 24 at the first stage is input to the subtracter 2.
It is inserted into one terminal of 9.

Further, in the digital ghost removal device of the present invention, the second
As shown in the drawings and FIG. 12, the equalization unit as a whole is connected by a feed link, but the present invention is also effective even if the equalizer unit is connected by a feed link.

Furthermore, the present invention is effective even in the waveform equalization mode in which the main signal also passes through the equalization unit in FIGS. 2 and 12.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a digital equalization circuit of the present invention, FIG. 2 is a block diagram of an embodiment of a digital ghost removal device of the present invention, and FIG. 3 is a block diagram of a conventional ghost removal device. 4 is a circuit diagram of a conventional digital equalization circuit, FIG. 5 is a diagram for explaining the ghost removal operation, and FIG. 6 is a circuit diagram of another embodiment of the digital equalization circuit of the present invention. , FIG. 7 is an operation flowchart of the ghost removal device shown in FIG. 2, FIG. 8 is a circuit diagram of another embodiment of the variable delay circuit of the digital equalization circuit of the present invention, and FIG. 10 and 11 are timing diagrams for explaining the operation, and FIG. 1 is a configuration diagram of another embodiment of the digital equalization circuit diagram of the present invention.
FIG. 2 is a block diagram of another embodiment of the digitized ghost circuit of the present invention. 211... Variable delay circuit 212... Digital transversal filter 21
3... Second adder 214... Equalization unit memory 11... First input terminal 2... Second input terminal 01... First output terminal 02... Output terminal 29 of 2...Subtractor 21, 22.23.24...Digital equalization circuit (equalization unit) (Representative Patent Attorney) Rules Kensuke Chika (and 1 other person) $3121 Figure + Figure! 1-4 CJ
``fi. Toru 71! 1 寥 δ g 寥 9 小寥 10 寥郎! １ 小竿 12 ■

Claims (3)

[Claims] (1) A variable delay circuit that changes the delay time of a signal input to a first input terminal and outputs the delayed signal to a first output terminal, and a plurality of tap coefficients whose input terminals are commonly connected. an input-weighted digital transversal filter consisting of a first adder connected to the output ends of the coefficient multipliers, a unit time delay element connected between the adders; a memory for storing a gain value in the tap coefficient unit and a delay time in the variable delay circuit;
and a second adder that takes the signal input to the second input terminal as the second input, and sums the two signals and outputs the sum to the second output terminal. (2) The digital equalization circuit according to claim 1, wherein the second adder also serves as one of the first adders. (3) A subtracter whose first input is a television signal containing a ghost, and whose output is a signal obtained by subtracting a second input from this input, and whose output is input to the first input terminal of the first stage. Sequentially, the output of the first output terminal of the previous stage is inputted to the first input terminal of the subsequent stage, or the output of the subtracter is inputted to each first input terminal in parallel, and the second output of the subsequent stage is inputted. a digital equalization circuit in which the outputs of the terminals are sequentially input to a second input terminal of the previous stage and the output of the second output terminal of the first stage is the second input of the subtracter; and the output of the subtracter is the input. and a control circuit that controls the digital equalization circuit, and the digital equalization circuit changes the delay time for the signal input to the first input terminal and outputs the delayed signal to the first output terminal. a variable delay circuit, a plurality of tap coefficient units whose input terminals are connected in common, a first adder connected to the output terminals of these coefficient units, and a unit time delay element connected between these adders. an input-weighted digital transversal filter comprising: a memory for storing a gain value in the tap coefficient unit of the transversal filter and a delay time in the variable delay circuit;
and a second adder which takes a signal inputted to a second input terminal as an input and outputs the sum of both signals to a second output terminal. Device.