JPS61147360A - Resource common use system - Google Patents

Abstract

PURPOSE:To solve access contention with current optimum priority by providing a priority altering means. CONSTITUTION:A memory circuit 113 normally has the lowest priority for a refresh request REFRQ, and neither a write request WRPQ nor a read request RDRQ is enqueued for the refresh request REFRQ, so when those requests are generated in succession, the refresh request is enqueued continuously. Consequently, when the refresh request is enqueued once and a next refresh request is outputted by refresh counter 110 again, a gate 212 outputs a forcible refresh request signal REFOV/(negative logic to clear FFs 201 and 202, so neither the write request WRRQ nor the read request RDRQ is latched and an FF 203 keeps on latching the refresh request during this period, so that the refresh request is processed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a resource sharing system that includes one or more resources and a plurality of resource access means that share the resource, and particularly to a resource sharing system that resolves access conflicts between the resource access means. Regarding the system.

[Prior art] Conventionally, in such *S sharing systems, the system's optimal ja priority order should change dynamically, but the 4a priority order that resolves access contention was fixed, so the throughput of the entire system decreased. did not rise. In other words, in a case where some resource access means have a low access frequency but a high priority, the explanation for why access permission to the resource of the access means with a high access frequency is postponed is explained in detail. To take this into consideration, an example of access contention in a memory circuit (DRAM is also a resource) consisting of a dynamic RAM (hereinafter abbreviated as DRAM) element will be explained.

FIG. 1 is a block diagram illustrating a conventional example of a memory control circuit for a DRAM element. In FIG. The timing generator 108 periodically generates a signal RQSPL, and by this RQSPL, logical states such as a refresh request (REFRQ), a write request (WRRQ), a read request (RDRQ), etc. are sent to flip-flops (hereinafter abbreviated as FF), respectively. 1
01, 102, and 103, respectively (the above operation is called request sampling).
The order of Q is fixed. That is, the refresh request REF
RQ is the highest level, and when this request is sampled, WRRQ is ignored by gate 104 and RDRQ is ignored by gates 106 and 105. Similarly, if WRRQ is occurring, RDRQ is ignored. In this way, the priority determining circuit 109 determines the process to be performed next.

-7, the refresh counter 110 performs a counting operation based on REFCLK output from the timing generator 108. REFCLK is generated at the same cycle as RQSPL, and when the refresh counter 110 counts up to a specified number (ie, refresh time), FFIII is set. That is, the output of FFIII is the refresh request REFRQ.

In the example shown in FIG. 1, since REFRQ is fixed at the highest level, it will be processed first no matter what state other requests are in. The output REFEX of the FF 101 is a signal that actually executes refresh, and the timing generator 108 receives REFEX and performs refresh processing by changing RAS, CAS, and WE.
Below, RAS, CAS, and WE are collectively referred to as DRAMf11j.
Reference numeral 113, called the ii signal, is a memory circuit consisting of a DRAM element. When the refresh process is completed, the timing generator 108 issues a refresh request release signal RE.
Generates FCLR and resets FFIII.

Similarly, WRCLR and RDCLR are generated every time a write process or a read process is executed, and are sent to, for example, a CPU (not shown) to cancel each request. On the other hand, if the request is not accepted and the execution process is not performed due to a request from a higher rank, the request cancellation signal is naturally not issued and the requests continue for 11 times.

The above is an explanation of the operation of the conventional example shown in FIG.

It is true that refreshing is indispensable in DRAM, and therefore, by making REFRQt-the highest level request, refreshing can be performed reliably. However, refresh is not directly related to data processing itself.

Therefore, if the refresh request is placed lower than other requests, the refresh will have to wait each time a refresh request is made, which is not suitable for the conventional fixed dredging point ranking system.

The above disadvantages are caused by, for example, the image memory of high-speed facsimiles,
Particularly in the case of storing compressed image information, the writing of the image information into memory, which should be fast due to refresh, is often delayed, and the processing speed of the fruiting device itself is also slowed down, which is a serious problem.

The purpose of the present invention has been made in view of the drawbacks of the conventional examples described above.The purpose of the present invention is to provide a resource sharing system that resolves access conflicts using the optimal priority at that time even when there is conflict for access to resources. It is there to provide.

Figure 1@2 is a conceptual diagram of an example according to the above purpose.
(access means), and the priority determining means resolves the access conflict according to the priority within the ranking holding means.

The priority determining means further determines the degree of access contention and causes the ranking changing means to change the ranking as appropriate. The degree of judgment to change the ranking is, for example, if the access of the lowest priority quester has been waited once and is likely to be waited for a second time, its ranking is temporarily raised to the highest. In order to make the explanation concrete, a case where this embodiment is applied to the above-mentioned DRAM circuit will be explained using FIG. 3.

In FIG. 3, XTAL107. timing generator 1
08. The refresh counter 110°FFIII and the memory circuit 113 are the same as in the conventional example shown in FIG.

In this example, the request priorities are WRRQ, RDRQ, and RE.
The order is FRQ, and REFRQ is usually at the bottom. Therefore, WRRQ and RDRQ are accepted and processed without having to wait for REFRQ.

Therefore, the speed of data processing becomes faster.

However, if higher-order requests such as WRRQ and RDRQ occur N consecutively, REFRQ will continue to wait. Therefore, the refresh request is made to wait once, and when the next refresh time is reached, the refresh counter 110
When the output is issued again, the gate 212 outputs the forced refresh request signal REFOV/C (if the signal name ends with "/'", the signal indicates negative logic). / is FF201 and 20
Since it is input to the CLR/terminal of No. 2, WRRQ.

RDRQ will not be latched and those requests will not be accepted. During this time, the FF 203 continues to latch REFRQ, so the refresh request (i.e., REFRQ) is kept latched.
EX) is processed first.

The purpose of gate 213 is for the following reasons.

That is, some DRAM devices usually require refreshing a predetermined number of times within one unit time. Therefore, in the case of RAM like this, it is not possible to reduce the average number of refreshes, so even if the refresh by forced refresh ends, it is necessary to ensure the average specified number of refreshes without resetting FFIII by REFCLR. .

Figure 4 is a timing chart of the above explanation. In Figure 0, three refresh times occur, but at the first refresh time, there were no other competing requests, so the refresh ended normally. It shows the state in which At the second refresh time, there was another competing request, so even if FF203 was set, REFE was not set.
X cannot be set to 1''', so the next refresh time will arrive with FFIII still set.
At the next refresh time, the gate 212
Since OV/ is '0''', even if there is a conflict, FF
Since the FF 201 and FF 202 are cleared, a forced refresh is performed, and the memory circuit 113 is refreshed. As mentioned above, depending on the REFCLR generated by this forced refresh, the FF for the gate 213 is
Since III is not reset, the FF 203 is set again by the primary RQSPL. Therefore, in the next memory cycle, refresh can be performed according to the normal priority order if there is no other conflict, and as a result, the average number of refreshes is secured.

As explained above, according to the above embodiment, it is easy to balance giving priority to access requests other than refresh and ensuring necessary refresh operations that are not directly related to data processing. This can be achieved with a circuit, which in turn speeds up the entire system. In particular, when storing a signal with redundancy suppressed in a facsimile, requests for writing and reading signals are issued at irregular intervals from the redundancy suppressing process. By giving priority to access requests other than refresh requests, efficient speed-up can be achieved.

In addition, as mentioned above, not only memory but also when the resource is another file device or a path line, efficient system operation can be achieved by temporarily raising the rank of a lower priority requester. .

As explained above, 1. According to the resource sharing system of the present invention, even if there is conflict for access to resources, the system resolves the conflict while determining the optimal priority for the system in real time, increasing the throughput of the entire system. .

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the prior art. FIG. 2 is a conceptual diagram of the embodiment. FIG. 3 is a circuit diagram when the embodiment is applied to a DRAM circuit, and FIG. 4!84 is a timing chart of the embodiment. In the figure, 110...refresh counter, 113...
・Memory circuit, 108...timing gene L/-'
), 111, 201, 202, 203-...
Flip-flop (FF), 212,213°214・
...It's a gate.

Claims (3)

[Claims] (1) One or more resources, a plurality of resource access means for accessing the resource, a holding means for holding the priority order of access competition between the resource and the resource access means, and a resource held in the holding means. A resource having a ranking means for ranking said access conflicts according to priority, and a ranking changing means for raising the priority of the resource access means that is not accepted when a low priority access is not accepted a predetermined number of times. shared system. (2) The resource sharing system according to claim 1, wherein the resource is a storage means for storing data. (3) The resource is a memory circuit consisting of a dynamic RAM element, and one of the plurality of resource access means is a refresh request means for the dynamic RAM, and the priority of the refresh request means is the lowest. A resource sharing system according to claim 2, characterized in that: