JPS6114707B2 - - Google Patents

Info

Publication number
JPS6114707B2
JPS6114707B2 JP5108080A JP5108080A JPS6114707B2 JP S6114707 B2 JPS6114707 B2 JP S6114707B2 JP 5108080 A JP5108080 A JP 5108080A JP 5108080 A JP5108080 A JP 5108080A JP S6114707 B2 JPS6114707 B2 JP S6114707B2
Authority
JP
Japan
Prior art keywords
channel
channels
circuit
sub
television
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5108080A
Other languages
Japanese (ja)
Other versions
JPS56146378A (en
Inventor
Kazuhiro Nakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5108080A priority Critical patent/JPS56146378A/en
Publication of JPS56146378A publication Critical patent/JPS56146378A/en
Publication of JPS6114707B2 publication Critical patent/JPS6114707B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/2624Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Description

【発明の詳細な説明】 本発明は一画面中に複数のチヤンネルの画像を
同時に映出することができるテレビジヨン受像機
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television receiver capable of simultaneously displaying images of a plurality of channels on one screen.

従来から斯種のテレビジヨン受像機としては特
願昭47−39273号(特開昭49−2419号)等のよう
に一画面中に主と副の2つのチヤンネルの画像を
同時に映出するものが既に提案され一部実用化さ
れている。
Traditionally, this type of television receiver has been capable of simultaneously projecting images from two channels, the main and sub channels, on one screen, as in the case of Japanese Patent Application No. 47-39273 (Japanese Unexamined Patent Publication No. 49-2419). have already been proposed and some have been put into practical use.

ここでまず主と副の2つのチヤンネルの画像を
同時に映出できる従来のテレビジヨン受像機につ
いて第1図に従つてその基本動作を説明する。
First, the basic operation of a conventional television receiver capable of simultaneously displaying images of two channels, the main channel and the sub channel, will be explained with reference to FIG.

第1図においてアンテナ、2は主チヤンネル受
信用のチユーナ、3は同中間周波増幅回路、4は
同映像検波回路、5は同映像増幅回路、6は同音
声検波回路、7は同音声増幅回路、8はスピー
カ、9は副チヤンネル受信用のチユーナ、10は
同中間周波増幅回路、11は同映像検波回路、1
2は同映像増幅回路、13は同期分離回路、14
は垂直偏向回路、15は水平偏向回路、16は信
号切換回路、17は映像出力回路、18は受像
管、19は副チヤンネル用同期分離回路、20は
記憶装置、21は制御信号発生回路であり、また
22は主チヤンネル用選局スイツチSW1,SW2
……SW9及び副チヤンネル用選局スイツチ
SW1′,SW2′……SW9′を有する選局操作部、23
はスイツチングトランジスタTR1,TR2,……
TR9主チヤンネル設定用可変抵抗VR1,VR2,…
…VR9及びダイオードD1,D2,……D9を有する
主チヤンネル選局回路、24はスイツチングトラ
ンジスタTR1′,TR2′,……TR9′、副チヤンネル
設定用可変抵抗VR1′,VR2′,……VR9′、及びダ
イオードD1′,D2′,……D9′を有する副チヤンネ
ル選局回路である。
In Fig. 1, there is an antenna, 2 a tuner for receiving the main channel, 3 an intermediate frequency amplification circuit, 4 a video detection circuit, 5 a video amplification circuit, 6 an audio detection circuit, and 7 an audio amplification circuit. , 8 is a speaker, 9 is a tuner for sub-channel reception, 10 is the same intermediate frequency amplification circuit, 11 is the same video detection circuit, 1
2 is the video amplification circuit, 13 is the synchronous separation circuit, 14
15 is a vertical deflection circuit, 15 is a horizontal deflection circuit, 16 is a signal switching circuit, 17 is a video output circuit, 18 is a picture tube, 19 is a synchronization separation circuit for sub-channels, 20 is a storage device, and 21 is a control signal generation circuit. , and 22 are main channel selection switches SW 1 , SW 2 ,
...SW 9 and secondary channel selection switch
A channel selection operation unit having SW 1 ′, SW 2 ′...SW 9 ′, 23
are switching transistors TR 1 , TR 2 , ...
TR 9 Variable resistor for main channel setting VR 1 , VR 2 ,…
...VR 9 and a main channel selection circuit having diodes D 1 , D 2 , ...D 9 , 24 is a switching transistor TR 1 ′, TR 2 ′, ... TR 9 ′, and a variable resistor VR 1 for setting the sub channel. ′, VR 2 ′, . . . VR 9 ′, and diodes D 1 ′, D 2 ′, . . . D 9 ′.

ここでいま選局操作部22の主チヤンネル用選
局スイツチSW1〜SW9の何れか1つをオン状態に
した場合には、そのスイツチに対応した選局回路
23にスイツチングトランジスタTR1〜TR9の1
つがオン状態となり、可変抵抗VR1〜VR9によつ
て予め設め設定された同調電圧がダイオードD1
〜D9を介して主チヤンネル受信用チユーナ2に
供給され、選局スイツチSW1〜SW9に対応したチ
ヤンネルが受信される。即ちこのとき主チヤンネ
ル受信用のチユーナ2、中間周波増幅回路3、映
像検波回路4及び映像増幅回路5で受信処理され
た主チヤンネルのテレビジヨン信号が信号切換回
路16及び映像出力回路17を介して受像管18
に供給され、該受像管18の主要部には主チヤン
ネルの画像が映出される。またこのとき映像増幅
回路5より得られる主チヤンネルの音声中間周波
数信号が音声検波され、検波後の音声信号が温声
増幅回路7にて増幅されスピーカ8に供給され、
該スピーカ8から主チヤンネルの音声が放声され
る。
If any one of the main channel selection switches SW 1 to SW 9 of the channel selection operation unit 22 is turned on, the switching transistors TR 1 to TR are connected to the channel selection circuit 23 corresponding to that switch. TR 9 no 1
is turned on, and the tuning voltage preset by variable resistors VR 1 to VR 9 is applied to the diode D 1 .
~ D9 to the main channel reception tuner 2, and the channels corresponding to the channel selection switches SW1 ~ SW9 are received. That is, at this time, the main channel television signal received and processed by the tuner 2 for main channel reception, the intermediate frequency amplification circuit 3, the video detection circuit 4, and the video amplification circuit 5 is transmitted via the signal switching circuit 16 and the video output circuit 17. Picture tube 18
The main channel image is projected onto the main part of the picture tube 18. Also, at this time, the audio intermediate frequency signal of the main channel obtained from the video amplification circuit 5 is audio detected, and the audio signal after detection is amplified by the warm voice amplification circuit 7 and supplied to the speaker 8.
The audio of the main channel is emitted from the speaker 8.

一方これと同時に選局操作部22の副チヤンネ
ル用選局スイツチSW1′〜SW9′の1つをオン状態
にすれば、上記の場合と同様に可変抵抗VR1′〜
VR9′によつて予め設定された同調電圧がダイオ
ードD1′〜D9′を介して副チヤンネル受信用チユー
ナ9に供給され、選局スイツチSW1′〜SW9′に対
応したチヤンネルが受信される。即ちこのとき、
副チヤンネル受信用のチユーナ9、中間周波増幅
回路10、映像検波回路11、及び映像増幅回路
12にて受信処理された幅チヤンネルのテレビジ
ヨン信号が記憶装置20に供給され、ここで制御
信号発生回路21による制御信号に基き減少され
た本数の走査線例えば3本に1本の割合で抜取ら
れた各走査線のテレビジヨン信号が順次記憶装置
20に書込まれるとともにこうして一旦書込まれ
た信号が書込み速度の3倍の速度で間歇的に順次
読み出され、この結果記憶装置20から時間軸が
1/3に圧縮された副チヤンネルのテレビジヨン信
号が導出される。この圧縮された副チヤンネルテ
レビジヨン信号が信号切換回路16に供給される
と、これが制御信号発生回路21の制御信号に基
いて切換えられ映像増幅回路5から得られる主チ
ヤンネルのテレビジヨン信号に代えて受像管18
に供給され、この結果受像管18の主チヤンネル
の画面の一部に1/3の大きさの副チヤンネルの画
像が同時に映出されることになる。なおここで副
チヤンネルの画像の大きさは記憶装置20におい
て副チヤンネルテレビジヨン信号の時間軸圧縮さ
れる割合によつて決定される。また副チヤンネル
の画像の位置は制御信号発生回路21の制御信号
によつて決定される。
On the other hand, if one of the sub channel selection switches SW 1 ′ to SW 9 ′ of the selection operation section 22 is turned on at the same time, the variable resistors VR 1 ′ to SW 9 ′ are turned on in the same way as in the above case.
The tuning voltage preset by VR 9 ' is supplied to the tuner 9 for receiving sub-channels via the diodes D1 ' to D9 ', and the channels corresponding to the channel selection switches SW1 ' to SW9 ' are received. be done. That is, at this time,
The television signal of the width channel received and processed by the tuner 9 for sub-channel reception, the intermediate frequency amplification circuit 10, the video detection circuit 11, and the video amplification circuit 12 is supplied to the storage device 20, where it is sent to the control signal generation circuit. Based on the control signal from 21, the television signals of each scanning line of the reduced number of scanning lines, for example, one out of every three scanning lines, are sequentially written into the storage device 20, and the signals once written in this way are It is read out intermittently and sequentially at three times the writing speed, and as a result, the time axis is read out from the storage device 20.
A sub-channel television signal compressed to 1/3 is derived. When this compressed sub-channel television signal is supplied to the signal switching circuit 16, it is switched based on the control signal of the control signal generating circuit 21 and is replaced with the main channel television signal obtained from the video amplifier circuit 5. Picture tube 18
As a result, a sub-channel image of 1/3 the size is simultaneously displayed on a part of the main channel screen of the picture tube 18. Here, the size of the sub-channel image is determined by the rate at which the sub-channel television signal is time-base compressed in the storage device 20. Further, the position of the image on the sub-channel is determined by a control signal from the control signal generation circuit 21.

上記のようにして主チヤンネルのテレビジヨン
画面の一部に副チヤンネルの画像が同時に映出さ
れる。
As described above, the images of the sub-channel are simultaneously displayed on a portion of the main-channel television screen.

ところが、上記のようなテレビジヨン受像機で
は、1つの画面には主と副の2つの画像しか同時
に映出できず、さらに多くの画像を同時に映出し
ようとすればその画像の数だけチユーナを増設し
なければならない。
However, with the above-mentioned television receiver, only two images, the main and sub images, can be displayed on one screen at the same time, and if you want to display more images at the same time, you will have to use the same number of channels as the number of images. Must be expanded.

現在、わが国の放送状態では一地域で受信可能
な放送局はせいぜい9チヤンネルであり、一画面
に9つの画像を同時に映出すればその地域での全
放送チヤンネルを同時に確認することができる
が、この場合通常9個のチユーナと9個のBBD
或いはRAM等記憶素子が必要とされる。
Currently, in Japan, the number of broadcast stations that can be received in one area is nine at most, and if nine images are displayed simultaneously on one screen, it is possible to check all broadcast channels in that area at the same time. In this case there are usually 9 chunas and 9 BBDs.
Alternatively, a memory element such as RAM is required.

本発明は主と副の2つのチヤンネルの画像を同
時に映出することができるテレビジヨン受像機に
おいて、2つのチユーナを有効に利用し、所望時
に同一画面上に複数の例えば2つのチヤンネルの
画像を同時に映出することができるテレビジヨン
受像機を提供するものである。
The present invention effectively utilizes two tuners in a television receiver that can simultaneously display images of two channels, a main channel and a sub channel, and displays images of a plurality of channels, for example, two channels, on the same screen when desired. To provide a television receiver capable of simultaneously displaying images.

以下図面に示す実施例に従つて本発明を説明す
る。第2図は本発明の1実施例をブロツク線図で
示し、ここで第1図と同一部分には同一符号を附
記している。ここでは第1図に示すテレビジヨン
受像機にさらにクロツクパルス発生器25、電子
スイツチング回路26,28,32,8進リング
カウンタ30、信号切換回路31、制御信号発生
回路33、記憶装置27,34、及びアドレスカ
ウンタ35を付加するとともに選局操作部22に
マルチ画面スイツチSW10を設けたものである。
The present invention will be described below with reference to embodiments shown in the drawings. FIG. 2 shows one embodiment of the present invention in a block diagram, in which the same parts as in FIG. 1 are given the same reference numerals. Here, the television receiver shown in FIG. 1 is further equipped with a clock pulse generator 25, electronic switching circuits 26, 28, 32, an octal ring counter 30, a signal switching circuit 31, a control signal generation circuit 33, storage devices 27, 34, In addition to adding an address counter 35, the channel selection operation section 22 is provided with a multi-screen switch SW 10 .

ここで選局操作部22の主チヤンネル用選局ス
イツチSW1〜SW9及び副チヤンネル用選局スイツ
チSW1′〜SW9′がオン状態にある場合の動作は上
述した第1図に動作と全く同様であり、このとき
受受像管18の画面には主と副の2つのチヤンネ
ルの画像が映出される。
Here, the operation when the main channel selection switches SW 1 to SW 9 and the sub channel selection switches SW 1 ′ to SW 9 ′ of the selection operation section 22 are in the on state is shown in FIG. 1 described above. It is exactly the same, and at this time, images of two channels, the main channel and the sub channel, are projected on the screen of the picture tube 18.

ところがいまこのような状態で所望時に選局操
作部22のマルチ画面スイツチSW10をオンした
場合には、主チヤンネル用選局スイツチSW1
SW9はそのままで副チヤンネル用選局スイツチ
SW1′〜SW9′が全てオフ状態となり、またスイツ
チング回路26,28がオン状態となる。
However, if the multi-screen switch SW 10 of the channel selection operation unit 22 is turned on at the desired time in this state, the main channel selection switches SW 1 to
Leave SW 9 as it is and use it as the sub channel selection switch.
SW 1 ′ to SW 9 ′ are all turned off, and the switching circuits 26 and 28 are turned on.

従つてこのとき、主チヤンネル受信用映像増幅
回路5より得られる主チヤンネルの映像信号がス
イツチング回路26を介して記憶装置27に供給
され、ここで走査線3本に対し1本の割合で抜取
られ書込まれるとともに書込み速度の3倍の速度
で間歇的に読み出され、こうして該記憶装置27
からは制御信号発生回路33の制御信号によつて
制御される所定期間ごとに時間軸の圧縮された主
チヤンネルの映像信号が導出され、これが信号切
換回路31及び映像出力回路17を介して受像管
18に供給される。この結果受像管18の画面に
一部例えば第3図に示す右下隅に主チヤンネル
のテレビジヨン画像が縮小されて映出される。
Therefore, at this time, the main channel video signal obtained from the main channel receiving video amplification circuit 5 is supplied to the storage device 27 via the switching circuit 26, where it is extracted at a ratio of one for every three scanning lines. It is written and read intermittently at three times the writing speed, and thus the storage device 27
A video signal of the main channel whose time axis is compressed is derived at predetermined intervals controlled by the control signal of the control signal generation circuit 33, and this is sent to the picture tube via the signal switching circuit 31 and the video output circuit 17. 18. As a result, the television image of the main channel is displayed in a reduced size on the screen of the picture tube 18, for example, in the lower right corner shown in FIG.

一方このとき、クロツクパルス発生器25で発
生されたクロツクパルスがスイツチング回路28
を介して8進リングカウンタ30に供給される。
ここで上記クロツクパルス発生器25では例えば
200msecのクロツクパルスが発生されるため8進
リングカウンタ30では200msecの間隔で→
→→・・・→→と順次切換えられ、1.6
秒ごとに一巡される。
On the other hand, at this time, the clock pulse generated by the clock pulse generator 25 is applied to the switching circuit 28.
is supplied to the octal ring counter 30 via the octal ring counter 30.
Here, in the clock pulse generator 25, for example,
Since a 200msec clock pulse is generated, the octal ring counter 30 has a clock pulse of 200msec →
→→・・・→→, 1.6
It completes one cycle every second.

従つて選局回路24ではスイツチングトランジ
スタTR1′,TR2′,TR3′……TR8′が所定間隔が順
次オンされ、各可変抵抗VR1′,VR2′VR3,……
VR8′に設定された同調電圧が順次切換えられて
副チヤンネル受信用チユーナ9に供給される。こ
のような結果副チヤンネル受信用映像増幅回路1
2からはこうして受信された各チヤンネルの映像
信号が順次導出され、スイツチング回路32を介
して記憶装置34に供給される。なお該スイツチ
ング回路32はクロツクパルス発生器25からク
ロツクパルスが供給されるごとに即ち200msecご
とにオン状態となる。従つてこのとき選局回路2
4の可変抵抗VR1′,VR2′,……VR8′によつて予
め設定されたチヤンネルの映像信号が映像増幅回
路12から導出され、これが順次記憶装置34に
供給される。
Therefore , in the channel selection circuit 24, the switching transistors TR 1 ′, TR 2 , TR 3 .
The tuning voltage set to VR 8 ' is sequentially switched and supplied to the tuner 9 for receiving the sub-channel. As a result, the video amplification circuit 1 for receiving the sub-channel
The video signals of the respective channels received in this way are sequentially derived from 2, and are supplied to the storage device 34 via the switching circuit 32. The switching circuit 32 is turned on every time a clock pulse is supplied from the clock pulse generator 25, that is, every 200 msec. Therefore, at this time, the tuning circuit 2
Four variable resistors VR 1 ′, VR 2 , .

上記記憶装置34はBBD素子のような記憶素
子群からなり、8画面分の記憶容量を有し、また
アドレスカウンタ35によつてその書込み、読出
し位置が指定される。該記憶装置34では各チヤ
ンネルの映像信号が制御信号発生回路33からの
制御信号に基き走査線3本に1本の割合で抜取ら
れ、それぞれ指定されたアドレスの記憶素子に1
フレーム(1画面)分ずつ書込まれる。なおここ
でアドレスカウンタ35は上記クロツクパルス発
生器25のクロツクパルスで駆動され、従つて上
記リングカウンタ30の動作と同期されているた
め、各チヤンネルの映像信号は個々に同一の記憶
素子に書込まれることになる。換言すると各記憶
素子にそれぞれ書込まれた各チヤンネルの映像信
号は1.6秒ごとに新しい信号に間歇的に書換えら
れることになる。
The storage device 34 is composed of a group of storage elements such as BBD elements, has a storage capacity for eight screens, and an address counter 35 specifies the writing and reading positions thereof. In the storage device 34, the video signal of each channel is extracted at a rate of one for every three scanning lines based on the control signal from the control signal generation circuit 33, and one video signal is extracted from the storage element of each designated address.
Each frame (one screen) is written. Note that since the address counter 35 is driven by the clock pulse of the clock pulse generator 25 and is therefore synchronized with the operation of the ring counter 30, the video signals of each channel cannot be individually written to the same memory element. become. In other words, the video signals of each channel written in each memory element are intermittently rewritten with new signals every 1.6 seconds.

一方この間に記憶装置34では制御信号発生回
路33の制御信号に基き、書込み速度よりも高速
(ここでは書込速度の3倍)で各記憶素子から各
チヤンネルの映像信号がアドレスカウンタ34で
指定された順序で連続して順次繰返し読出され
る。
Meanwhile, in the storage device 34, the video signal of each channel from each storage element is designated by the address counter 34 at a higher speed than the writing speed (in this case, three times the writing speed) based on the control signal from the control signal generation circuit 33. The data are sequentially and repeatedly read out in the same order.

こうして上記記憶装置34より読出された各チ
ヤンネルの映像信号は信号切換回路31及び映像
出力回路17を介して受像管18に供給され、こ
の結果受像管18の画面に第3図に示すように8
つのチヤンネルの画像がA,B,C……Hの位置
に同時に映出される。なおこの場合各画像は1.6
秒ごとに新しい画像に切換えられ、この間1.6秒
間は静止画像となるが、発明者らは実験によりこ
の程度の静止画像であれば、若干ストロボ的な動
きとはなるものの、各チヤンネルの放送内容を十
分知り得ることを確認した。もちろんクロツクパ
ルス発生器16のクロツクパルス周期を
150msec,100msecと短くするに従つてより自然
な映像に近づくことは言うまでもないが、チユー
ナ9等の安定な動作を得るためには余り極端にク
ロツクパルス周期を短くすることは不可能であ
る。
The video signals of each channel read out from the storage device 34 are supplied to the picture tube 18 via the signal switching circuit 31 and the video output circuit 17, and as a result, the screen of the picture tube 18 is displayed as 8 as shown in FIG.
Images of three channels are displayed simultaneously at positions A, B, C...H. In this case, each image is 1.6
The image is switched to a new image every second, and the image remains static for 1.6 seconds during this period.The inventors have experimentally found that with a static image of this level, the broadcast contents of each channel can be easily adjusted, although the movement may be a bit strobe-like. I made sure that I knew enough. Of course, the clock pulse period of the clock pulse generator 16 is
It goes without saying that the shorter the clock pulse period is to 150 msec or 100 msec, the closer the image will be to a natural image, but in order to obtain stable operation of the tuner 9, etc., it is impossible to shorten the clock pulse period too much.

こうして本実施例ではマルチ画面スイツチ
SW10をオンした場合に、受像管画面にはその一
部にそれまで受信していた主チヤンネルの画像が
1/9に縮少されて映出されるとともにさらに8つ
のチヤンネルの画像が同時に映出され、視聴者は
選局スイツチSW1〜SW9を順次オンしなくとも各
チヤンネルの放送内容を容易に知ることができ
る。
In this way, in this embodiment, the multi-screen switch
When SW 10 is turned on, part of the picture tube screen displays the image of the main channel that was being received.
The images are reduced to 1/9 and displayed, and the images of eight channels are also displayed simultaneously, allowing viewers to easily know the broadcast contents of each channel without having to turn on the channel selection switches SW 1 to SW 9 in sequence. be able to.

この場合それまで受信していた主チヤンネルの
画像は縮小されるものの引き続き画面の一部に連
続的に映出され、またスピーカ8からはこの主チ
ヤンネルの音声が放声されるため特に不都合を感
じることはない。
In this case, the image of the main channel that had been received up to that point will be reduced but will continue to be displayed continuously on a part of the screen, and the audio of this main channel will be emitted from the speaker 8, which may be particularly inconvenient. There isn't.

上記のようにしてマルチ画面スイツチSW10
オンし各チヤンネルの放送内容を一覧した後、マ
ルチ画面スイツチSW10をオフするとともに所望
とするチヤンネルの選局スイツチSW1〜SW9をオ
ンすれば、このときスイツチング回路26,28
がオフ状態となるとともに信号切換回路31が元
の状態に切換えられ、このとき上記所望のチヤン
ネルが連続的に受信されこの映像が受像が受像管
画面に映出される。
After turning on the multi-screen switch SW 10 and viewing the broadcast contents of each channel as described above, turn off the multi-screen switch SW 10 and turn on the channel selection switches SW 1 to SW 9 of the desired channel. At this time, the switching circuits 26, 28
is turned off, and the signal switching circuit 31 is switched back to its original state. At this time, the desired channel is continuously received and the received image is displayed on the picture tube screen.

なお上記実施例では記憶装置27,34に
BBD素子のようなアナログ記憶素子を用いる例
を述べたが、もちろんRAM等のデイジタル記憶
素子とAD変換器及びDA変換器を用いて映像信号
を一旦デイジタル映像情報に変換して記憶させる
ようにしてもよい。
In the above embodiment, the storage devices 27 and 34
An example of using an analog storage element such as a BBD element has been described, but of course it is also possible to convert the video signal into digital video information and store it using a digital storage element such as RAM and an AD converter and a DA converter. Good too.

本発明によれば、上記のように2つのチユーナ
を有し主と副の2つのチヤンネルの画像を同時に
映出するテレビジヨン受像機において、所望時に
一方のチユーナで選局された特定のチヤンネルの
映像信号を第1の記憶装置に一旦書込み、またこ
のとき他方のチユーナで複数のチヤンネルを一定
周期で順次選局し、こうして得られる複数のチヤ
ンネルの映像信号を個々に第2の記憶装置の所定
のアドレスに間歇的に書込み、さらに上記第1、
第2の各記憶装置から画面位置に対応した所定の
順序で各チヤンネルの映像信号を高速で読出し受
像管に供給しているため、受像管画面には特定の
チヤンネルの画像が縮小されて連続的に映出され
るとともにさらに複数の例えば8つのチヤンネル
の画像が同時にストロボ的に映出され、視聴者は
選局操作を繰返さなくとも各チヤンネルの放送内
容を即座に知ることができ非常に便利なものであ
る。
According to the present invention, in a television receiver having two tuners and displaying images of two channels, the main channel and the sub channel, as described above, a specific channel selected by one of the tuners can be displayed at a desired time. The video signal is once written to the first storage device, and at this time, the other tuner sequentially selects a plurality of channels at a fixed period, and the video signals of the plurality of channels obtained in this way are individually written to a predetermined location in the second storage device. Write intermittently to the address of
Since the video signals of each channel are read out at high speed from the second storage device in a predetermined order corresponding to the screen position and supplied to the picture tube, the picture of a specific channel is reduced and displayed continuously on the picture tube screen. In addition to the images of multiple channels, for example eight, being displayed simultaneously in a strobe-like manner, viewers can instantly know the broadcast contents of each channel without having to repeatedly select channels, which is very convenient. It is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のテレビジヨン受像機のブロツク
線図、第2図は本発明の1実施例のブロツク線
図、第3図は同実施例において映出されるテレビ
ジヨン画面の説明図である。 2……主チヤンネル受信用チユーナ、9……副
チヤンネル受信用チユーナ、22……選局操作
部、23……主チヤンネル用選局回路、24……
副チヤンネル用選局回路、25……クロツクパル
ス発生器、27……記憶装置、30……8進リン
グカウンタ、31……信号切換回路、33……制
御信号発生回路、34……記憶装置、35……ア
ドレスカウンタ。
FIG. 1 is a block diagram of a conventional television receiver, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a television screen displayed in the same embodiment. 2... Tuner for main channel reception, 9... Tuner for sub channel reception, 22... Tuning operation section, 23... Tuning circuit for main channel, 24...
Sub channel selection circuit, 25...Clock pulse generator, 27...Storage device, 30...Octal ring counter, 31...Signal switching circuit, 33...Control signal generation circuit, 34...Storage device, 35 ...address counter.

Claims (1)

【特許請求の範囲】[Claims] 1 2つのチユーナを有し主と副の2つのチヤン
ネルの画像を同時に映出するテレビジヨン受像機
において、所望時に一方のチユーナで選局された
特定のチヤンネルのテレビジヨン信号を一旦書込
み記憶する第1の記憶手段と、これと同時に他方
のチユーナで複数のチヤンネルを一定周期で順次
繰返し選局する選局手段と、該選局手段より得ら
れる各チヤンネルのテレビジヨン信号を所定のア
ドレスに個々に間歇的に書込み記憶する第2の記
憶手段と、上記第1及び第2の各記憶手段から画
面位置に対応した所定の順序で各チヤンネルのテ
レビジヨン信号を書込み時よりも高速で読み出す
読み出し制御手段とを備え、所望時に一画面上の
所定位置に特定チヤンネルの縮小画像を連続的に
映出するとともにさらに複数のチヤンネルのスト
ロボ的な画像を同時に映出できるようにしたこと
を特徴とするテレビジヨン受像機。
1. In a television receiver having two tuners and displaying images of two channels, main and sub, at the same time, the television signal of a specific channel selected by one of the tuners is temporarily written and stored at a desired time. At the same time, the other tuner repeatedly selects a plurality of channels in sequence at a constant cycle, and the television signal of each channel obtained by the channel selection means is individually sent to a predetermined address. a second storage means for intermittently writing and storing; and a readout control means for reading out the television signals of each channel from the first and second storage means in a predetermined order corresponding to the screen position at a higher speed than when they were written. A television, characterized in that it is capable of continuously displaying a reduced image of a specific channel at a predetermined position on one screen when desired, and further displaying strobe-like images of a plurality of channels at the same time. receiver.
JP5108080A 1980-04-15 1980-04-15 Television picture receiver Granted JPS56146378A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5108080A JPS56146378A (en) 1980-04-15 1980-04-15 Television picture receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5108080A JPS56146378A (en) 1980-04-15 1980-04-15 Television picture receiver

Publications (2)

Publication Number Publication Date
JPS56146378A JPS56146378A (en) 1981-11-13
JPS6114707B2 true JPS6114707B2 (en) 1986-04-19

Family

ID=12876829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5108080A Granted JPS56146378A (en) 1980-04-15 1980-04-15 Television picture receiver

Country Status (1)

Country Link
JP (1) JPS56146378A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL192654C (en) * 1989-07-26 1997-11-04 Samsung Electronics Co Ltd Video receiver device suitable for multi-channel reception in a menu-operated multi-channel display device with a picture-in-picture function.
NL192655C (en) * 1989-07-26 1997-11-04 Samsung Electronics Co Ltd Multi-channel editing unit menu type.
JPH0563163U (en) * 1992-01-28 1993-08-20 日本電気ホームエレクトロニクス株式会社 Television receiving system

Also Published As

Publication number Publication date
JPS56146378A (en) 1981-11-13

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