JPS61143860A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To detect a fixed defect of a memory cell array by using a memory means for storing generation of errors and a control means for controlling externally whether or not to execute the correction of errors. CONSTITUTION:An error checking circuit 3 delivers the error detecting signal as well as the error correction signal. An RS type flip-flop 5 is set by the error detecting signal, and the flip-flop 5 is reset when the error correction control signal shows an error correction mode. Whether or not to execut error correction is controlled by the error correction control signal given from a control means. Then an error correction circuit 4 corrects errors with the error correction control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a semiconductor memory device incorporating an error correction circuit.

[Conventional technology]

FIG. 2 is a block diagram of a conventional semiconductor memory device incorporating an error correction circuit, and an example thereof is shown in Japanese Patent Laid-Open No. 59-5500. In FIG. 2, 1 is data for error checking from the write information data! The test data generation circuit that generates, 2 is information data! A memory cell array 3 consists of a memory cell array 2a for storing data and a memory cell array 2b for storing test data generated in the test data generation path 1, and a memory cell array 3 inputs the information data and test data read from the memory cell array 2 and detects errors. An error check circuit 4 that outputs a correction signal is an error correction circuit that corrects information data read from the memory cell array 2 based on the error correction signal output from the error check circuit 3.

Conventional error check circuit 3'%: The built-in semiconductor memory device is constructed as described above, and in FIG. 2, a Hamming code is used for error correction.

Assume that error correction is performed in units of 8 bits Y of information data. When writing data to the memory cell array V2, the test data generation circuit 1 encodes 8 bits of information data to generate 4 bits of error test data, and writes the 12 bits in total to the memory cell array 2 as one unit. be included. When reading data, the 12 bits of data are read out simultaneously, and the error check circuit 3
Decodes the bit data and outputs an error correction signal. This error correction signal is a signal indicating the error position in the read information data, and the error correction circuit 4 corrects the information data using this correction signal. In the case of the Hamming code assumed here, if the error is one bit out of a total of 12 bits of information data and test data, it can be corrected and normal data is read from the semiconductor memory device. Therefore, by incorporating the error correction circuit 4 into the semiconductor memory device, reliability can be greatly improved against errors that occur intermittently in units of one bit, such as soft nibbles caused by alpha rays. is possible.

[Problem that the invention seeks to solve]

Conventional semiconductor memory devices with built-in error correction circuits are configured as described above, so even if a permanently defective bit exists in a memory cell, it will continue to operate normally as long as it is within the correctable range. However, there was a possibility that fixed defective bits could not be discovered from the outside. Items that contain fixed defects have lower reliability against soft errors than those that do not contain fixed defects, but as mentioned above, there is a possibility that the presence of fixed defects cannot be discovered from the outside, so the reliability of the equipment itself is reduced. The problem was that it was not possible to grasp gender.

The present invention was made in order to solve such problems, and an object of the present invention is to obtain a semiconductor memory device with a built-in error correction circuit that can detect fixed defects existing in memory cells from the outside. shall be.

[Means for solving problems]

A semiconductor storage device with a built-in error correction circuit according to the present invention includes a storage means for inputting an error check signal and storing information that the error check circuit has detected an error, and a control means for externally controlling correction execution l of the error correction circuit. [Operation] In the present invention, the error correction circuit suspends execution of error correction under external control and outputs the information data t read from the memory cell as is. On the other hand, when the error check circuit detects an error, an error flag is set by the output from the storage means that receives the error detection signal.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention.
The reference numeral 1.2 is the same as in the conventional example shown in FIG. 3 is externally provided with an error check circuit that outputs an error detection signal in addition to the error correction signal, and a control means (not shown) that controls whether or not to execute error correction. 1 is an error correction circuit whose execution or not of correction is controlled by an error correction control signal from a control means;
This is set by the error detection signal output from the error check circuit 3, and is reset when the error correction control signal indicates execution of error correction. R8 as a means
With type flip flops.

The output is output to the outside as an error flag.

In the semiconductor memory device configured as described above, if the error correction control signal is normally set to the correction execution state, the device shown in FIG. 1 is exactly the same as the device shown in FIG. 2, which is a conventional example. perform the following actions.

Furthermore, when checking whether a permanent defect exists in the memorial cell array 21C, the semiconductor memory device is tested after setting the error correction control signal to a correction inhibited state. In this test, since the data of the memory cell 2a which stores one piece of information is output as is, fixed defects in this part can be found. Fixed defects in the memory cell array 2b storing inspection data can be identified by checking the error flag after the test. In other words, if the test is completed normally but the error flag is set, this means that a fixed defect exists in the memory cell array 2b that stores the test data.

Therefore, in the semiconductor memory device of FIG. 1, it is possible to discover all fixed defects t existing in the memory cell 2.

In the above embodiment, the error flag is reset by the error correction control signal, but a signal for resetting the error flag may be provided separately (it would be better to monitor the error flag during normal operation so that the error flag can be read out). It is sometimes possible to know from the outside whether error correction has been performed.

〔Effect of the invention〕

As described above, the present invention includes a storage means for inputting an error detection signal and storing the occurrence of an error, and a control means for externally controlling whether or not the error correction circuit executes error correction. Therefore, fixed defects existing in the memory cell array can be discovered from the outside, and the reliability of the semiconductor memory device can be ascertained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device showing one embodiment of this invention, and FIG. 2 is a block diagram showing a conventional example. In the figure, 1 is an inspection data generation circuit, 2.2&, 2b
3 is an error check circuit, 4 is an error correction circuit, and 5 is a 7-rip-p-tub. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others)

Claims (1)

[Claims] A test data generation circuit that generates error test data from write information data during data writing, a memory cell array that stores the write information data and the test data, and a memory cell array that stores the information data and test data read from the memory cell array during read. an error check circuit that receives the error detection signal as an input and outputs an error detection signal and an error correction signal; a storage means that receives the error detection signal as an input and stores the occurrence of an error; 1. A semiconductor memory device comprising: an error correction circuit for correcting errors; and a control means for externally controlling whether or not to cause the error correction circuit to perform error correction.