JPS61136147A - Cache memory controller - Google Patents

Abstract

PURPOSE:To avoid using th wrong data with processing of a cache memory controller by providing an F/F to both a cache memory control part and a data processing control part respectively for storage of error information and comparing the outputs of both F/Fs with each other to stop the working of both parts in such a specific case where no coincidence is obtained fro said comparison. CONSTITUTION:A cache memory control part 101 contains a retry F/F 111 and a comparator 113. The contents of the F/F 111 are compared with the contents a holding F/F 110 of a data processing control part 102 for confirma tion of coincidence of working between both parts 101 and 102. Then the part 102 uses the wrong data to stop the progress of processing in case the error information sent from the part 101 is not transmitted to the part 102 owing to a hardware fault.

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a control method for a cache memory in an information processing device, and particularly to a control method when an error is detected in data read from the cache memory. (Conventional Techniques) Conventionally, in an information processing apparatus equipped with a cache memory, when an error is detected in data read from the cache memory, a method has been known in which the corresponding data is read from the main memory. FIG. 4 shows a cassette memory control device that uses the same response signal when returning read data from the cache memory and when an error is detected in the read data and returning data from the main storage device. It is a block diagram showing an example. In FIG. 4, 101 is a cache memory control unit;
02 is a data processing control unit, 40γ is a data register, 4
10 is hold F/F, 420 is AND/NAND game~
, 421 and 422 are AND gates, respectively. Further, 403 is a data line, 404 is a cache memory error occurrence signal line, and 405 is a response signal line. In FIG. 4, a read instruction is sent from the data processing control unit 402 to the cache memory control unit 401, and the cache memory control unit 401 puts read data on the data line 405 and returns a response signal on the response signal line 406. Read data is stored in data register 407. Therefore, the data processing device 402 uses the data stored in the data register 401. If data is read from a cache memory (not shown) on data line 40! If an error is detected in the read data at the time when it is placed on the response signal line 405, the response signal on the response signal line 405 becomes logic value l, and the signal IIJ! Cache memory 2-generated signal on 404 becomes logical value 11C, AND/
The AND output of the NAND gate 420 becomes a logic value IK on the signal line 45Q, and the 1NAND output becomes a logic value 0 on the signal line 451. Also, AND gate 42+. The signal lines 462 and 453 have a logic value of 1.422, respectively. It's OK. In the hold F/F 410, the set signal has a logical value of 1. IJ upper set number is logical value O
Therefore, the above state becomes a logical value 1 in the hold F/F 410. Hold F/F'4 + O is logical value IK
Then, the data processing control unit 402 enters a stopped state. At this time, since an error has been detected in the data stored in the data register 40γ, the data from the cache memory is not used. During the period when the data processing control unit 402 is in a stopped state due to the hold F/F 410, the cache memory control unit 401 reads the data corresponding to the read instruction from the main storage device, and when the read is completed, the above-mentioned The read data is placed on the data line 403, and the response signal on the signal line 406 is set to logic 1. In this case, since the cache memory error occurrence signal on the signal line 404 is the logical value θ, the outputs of the AND gates 421 and 422 are respectively 0.1, and the set signal in the hold F/F 410 is the logical value O, Reset signal is logical 1
becomes. As a result, the contents of the hold F/F 410 become logically OK, and the data processing control unit 402 returns from the stopped state to the operating state. At this time, since the data read from the main memory is stored in the data register 4Q7, the erroneous data can be used. FIG. 5 is a time chart showing the operation of the control circuit shown in FIG. 4. In the time chart of FIG. 5, A and C are cases where no error is detected with respect to the read instruction, and B is a case where an error is detected. Further, Bl is a case where an error is detected and the cache memory control unit 1 returns data from the main storage device in response to a read instruction of 9B. In the time chart of FIG. 5, during the period when an error is detected and the data of 9B is stored in the data register 7, the hold F/F 410 becomes a logical value 1, and the data processing control unit 402 becomes a stop state trap. There is. therefore,
Without realizing that a substantial KB of data was returned,
Operations can be performed using the data in B1. However, due to a hardware failure, the cache memory control unit 4 may perform an operation to detect a data error, and the data processing control unit 402 may temporarily enter a state in which it performs an operation in which no data error is detected. The time chart in FIG. 6 shows the case where the above-mentioned failure condition occurs in the process B in FIG. 5. 6th
In the figure, since the memory error occurrence signal on the signal line 404 cannot be recognized by the data processing control unit 402, the hold F/F 410 does not have a logical value IK, and the data processing control unit 402 does not enter a stopped state. Therefore, during the period in which the cache memory control unit 401 reads data from the main memory for one BK in which an error has been detected and returns the data by BIK, the data processing control unit 402 reads data from the BK in the next read.
is executed, and the data is stored in the data register 407 from the BIK of the response signal of tJcl, and the data of B1 is used as the data of C, which results in the incorrect data being processed. (Problems to be Solved by the Invention) Therefore, as shown in FIG.
Even in the case where the response signal on the signal line 405 is used, there is a drawback that the information processing apparatus may process incorrect data, which is the most important thing to avoid, due to a specific failure of the hardware. The purpose of the present invention is to provide a cache memory system [BKIJ try F/F and a comparator, compare the contents of the retry F/F and the contents of the hold F/F of the data processing control section, and The above drawbacks can be eliminated by checking the consistency of the operation with the processing control unit, and if the error information sent from the cache memory control unit is not transmitted to the data processing control unit due to a hardware failure, the data processing It is an object of the present invention to provide a cache memory control device configured to prevent processing from proceeding due to a control unit using erroneous data. (Means for Solving the Problems) A katsunyu memory control device fl according to the present invention includes a data processing control section and a cache memory control section. The data processing control unit is for giving an R output instruction to the cache memory in order to control the cache memory for transferring and storing data in the main storage device block by block. The cache memory control unit receives a read instruction from the data processing control unit and, if the data exists in the cache memory, transfers the data from the cache memory to the data processing control unit, and confirms that the data exists in the cache memory IJK. If not, it is used to transfer data from the main memory to the data processing control unit. In the above configuration, the data processing control section includes a hold F/F for maintaining a stopped state and a gate means for setting/resetting the hold F/F. On the other hand, the canyu memory control section includes a response signal generating means,
It is equipped with an IJ try F/F, a comparator, a control means, and an error F/F. The response signal generation means is for generating a response signal to be returned together with data from the cache memory or main storage device in response to a read instruction. The retry F/F is used to store error information when an error is detected in the data in the cache memory when the data in the cache memory is returned by a response signal. The comparator is for comparing the value set in the hold F/FK and the value set in the retry F/F. The control means is for returning data from the main memory to the data processing controller if the output of the comparator does not indicate a match. The error F/F is set only when the output of the comparator indicates a mismatch, and is used to temporarily interrupt the functions of the cache memory control section and the data processing control section. In the present invention, in the above configuration, hardware failure

If the error information sent from the cache memory control section is not transmitted to the data control section, the data processing section is configured to prevent the data processing section from proceeding with the process using erroneous data. (Example) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a cache memory control device according to the present invention. In Figure 1, 10
1 cache memory control unit, 102 a data processing control unit, 101 a data register, 108 a response signal generation control unit, 110 hold F/F, 111 retry F'
/F, 112 is error F'/F, 11! Comparator,
20, 21° 24.25 are AND gates, 21
2i1 is an AND/NAND gate. Also, 105
104 is a cache memory error occurrence signal line, 105 is a response signal line, 10B is a hold F/F
Output signal line 109 is a comparator output signal network. In FIG. 1, a read instruction is sent from the data processing control unit 102 to the cache memory control unit 101, the read data is placed on the data line 105 from the cache memory control unit 101, and a response signal is returned on the signal line 106. The read data is stored in the data register 1 (1). Therefore, the data processing device 1 (12) uses the data stored in the data register +07. If the read data from the cache memory is stored in the data line 105
If an error is detected in the read data when it is loaded on the
The response signal on the signal Ifs106 becomes a logic value 1, and the cache memory error occurrence signal on the signal line 104 becomes a logic value IK, and the NAND of the AND/NAND gate 25
Output signal I! i! When the state on the KAND output signal line 161 becomes a logic value 1, the state on the KAND output signal line 161 becomes a logic value 1. The outputs of AND gates 124 and 125 are connected to signal lines 158 and 1.
59, each has a logical value of 0.1. Hold F/F
Since the set signal has a logic value of 1 and the reset signal has a logic value of 0, the output signal of the hold F, /Flo has a logic value of 1 on the signal line 106. The same thing holds true for the cache memory control unit 101 as well. Since the response signal on signal line 105 has a logic value of 1 and the cancel/unmemory error occurrence signal on signal line 104 has a logic value of 1, the state on output signal line 162.15il of AND/NAND gate 22 have a logic value of 0 and a logic value of 1, respectively, and the output signal #i! of the AND gate 120° 121! The states on 150 and 151 are logical 0 and logical 1, respectively. As a result, retry F
/F1111C, the set signal has a logical value of 1 and the reset signal has a logical value of 0, so the retry F/
The state on the output signal line 155 of Fil becomes the logical value IK. Since the output signal lines 1116 and 155 of the hold F/FTIQ and the retry F/Fl11 each have a logical value of 1, the output of the comparator 113 is maintained at the logical value OK in the same way as when a cache memory error occurs. When the hold F/F 110 becomes a logical value 1, the data control unit 102 enters a stopped state. At this time, data register 1
Data from the cache memory stored in 07 and detected in 2- is not used. Data processing control unit +02 indicates stop status L1 from hold F-'FI+OK? During the period when , the cache memory control unit 101 reads the data corresponding to the read instruction IC from the main storage device, and when the read is completed, the read data is placed on the data line 103 and the signal #5!1G&
Let the above response signal have a logic value of 1. In this case, signal line 1 [
Since the memory error occurrence signal on 14 has a logical value θ, the outputs of AND game) 124 and 125 have a logical value of 1 and a logical value of O, respectively, and hold F'/FM
In OIC, the cent signal becomes a logic value O and the reset signal becomes a logic value 1. This allows hold F/F
110 becomes logic #LO, and the data processing control unit 102 returns from the stopped state to the operating state. At this time, since the data read from the main memory is stored in the data register 10γ, error-free data can be used. FIG. 2 is a time chart showing the operation of the Canon memory control device of FIG. 1 described above. A and C in the time chart of FIG. 2 are cases where no error is detected in response to a read instruction, and cases where an error B is detected. Furthermore, Ic, B+ is B where an error was detected.
This is a case where the cache memory control unit 101 returns data from the main storage device in response to a read instruction. During the period when an error is detected according to the time chart in FIG.
/F110 becomes logical value 1, data processing control unit +02
is in a stopped state. It can be seen that the data processing control unit 102 operates using the data of B1 without actually recognizing that the data of B has been returned. However, due to a hardware failure, the cache memory control unit 101 may detect a data error, but the data processing control unit 102 may not detect a data error. In such a case, the data processing control unit 102
However, the process continues using incorrect data. Therefore, in order to avoid this problem, as shown in FIG.
Listen to retry F/Fll+ and hold F'/FM+0, which store error information, and compare their outputs51
13, it is checked from the comparison K whether the error information has been reliably transmitted to the data processing control unit 102. if,
If no error is detected by the data processing control unit 102, the output signal line 10 of the hold F/F 110
The state on B has a logical value of 0, but on the other hand, the output of the retry F/F'll in the cache memory control unit 101 has a logical value of 1, so the output signal line 10g of the comparator 115
has a logical value of 1. At this time, the set signal of the error F/F 112 provided in the cache memory control unit 101 has a logical value of 1, and the error F/F'l + 2 has a logical value of 1.
is stored. When the value set in the error F/F 112 becomes a logical value 1, the cache memory control unit 10
1 and the data processing control unit 102 are both stopped. This prevents the data processing control unit 102 from using all the erroneous data and preventing the processing from proceeding. FIG. 3 is a time chart showing the status of the above error processing. In the time chart of FIG. 3, B is a case where no error is detected in response to the A read instruction, and B is a case where an error is detected in the cache memory control unit 101, but the signal line 1
This is a case where the cache memory error occurrence signal above 04 is not transmitted to the data processing control unit 102, or even if it is transmitted, it cannot be detected. Cache memory control unit IG
1 retry F/F+11 has a logical value IK,
Hold F/F'++[l logical value 01C of data processing control unit 102 is maintained. Therefore, as explained above, the output of the comparator 113 becomes a logic value 1, and the value sent to the error F/Fl i 2 becomes a logic value 1, so the state of the cache memory control unit 101 and the data processing The function of the control unit 102 is stopped, and the read instruction C that should be output next is suppressed. Note that the AND/NAND gate 22.2 in FIG.
The input signal of 3 and the input signal of AND gates 20 and 21 are simplified as if they were the same signal, but even though they are logically the same, in the actual circuit, the control section 108, they pass through mutually different and complex circuits. (Effects of the Invention) As explained above, the present invention provides a cache memory control section, a data processing control section, and an F/F for storing information, and compares their outputs with each other.
In specific cases where they do not match, the operations of the cache memory control unit and data processing control unit are stopped to prevent processing from using incorrect data, eliminating waste and improving processing efficiency. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a Canon Umemo IJ control time chart according to the present invention. FIG. 4 is a block diagram showing an example of a conventional cassonry memory control system. 5 and 6 are time charts showing the operation of the cache memory control device shown in FIG. 4, respectively. 101.4111@-・Cache memory control unit +02
．． 402...Data processing control unit 107.40γ...
Data register 108...Control unit 110.110-Hold F/F 111...Pot/Retry F/F 112...ΦFist...-Error F/F 113.413...Skewer comparator 120.121, 124,126,421゜4ri2...
ΦAND gate 122.12i1, 420--@AND/NAND gate 103-106, 109, 150-15g. 403-406, 450-453...Signal line 21 Fig. 24 Fig. -■ Fig. 5 Fig. 16

Claims (1)

[Claims] In order to control a cache memory for transferring and storing data in the main storage device block by block, there is provided a data processing control section for giving a read instruction to the cache memory, and a data processing control section for receiving read instructions from the data processing control section. If the data exists in the cache memory, the data is transferred from the cache memory to the data processing control unit, and if the data does not exist in the cache memory, the data is transferred from the main storage device to the data processing controller. a cache memory control section for transferring data to a data processing control section, and the data processing control section includes a hold F/F for maintaining a stopped state;
gate means for setting/resetting /F, and the cache memory control unit generates a response signal to be returned together with data from the cache memory or the main storage device in response to the read instruction. a response signal generating means, a retry F/F for storing the error information when an error is detected in the data in the cache memory when the data in the cache memory is returned by the response signal, and the hold F/F
a comparator for comparing the value set in the retry F/F with the value set in the retry F/F, and if the output of the comparator indicates a match, the data from the main storage device is a control means for returning the data to the processing control section and a control means for temporarily interrupting the functions of the cache memory control section and the data processing control section, which is set when the output of the comparator indicates a mismatch; Error F/F
and, if the error information sent from the cache memory control unit is not transmitted to the data control unit due to a hardware failure, the data processing unit can proceed with processing using the erroneous data. A cache memory control device characterized in that the cache memory control device is configured such that the cache memory control device does not have a cache memory.