JPS61136131A - Information processor - Google Patents

Abstract

PURPOSE:To simplify the control with an information processor by attaining the dynamic allocation of registers just in a single block with no intervention of control signals given from other function blocks. CONSTITUTION:A virtual register control circuit 4 contains a conversion table showing the correspondence between logical and physical register numbers. When the signal ASP requesting the new allocation is set at ''0'', the logical register numbers LR1, LR2 and LWR are converted into physical register numbers PR1, PE2 and PWR respectively with retrieval of the conversion table. In the dame way, the numbers LR1 and LR2 are converted into PR1 and PR2 respectively when the signal ASP sent to a register unit 5 is set at ''1''. However the LWR undergoes a different conversion process. That is, a physical number which is not presently registered in the conversion table is selected and then delivered as the PWR. Then the physical register number entered to the conversion table and corresponding to the LWR is rewritten to the selected physical register number.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital computer, and particularly to an information processing device that dynamically allocates registers when processing multiple instructions in parallel to increase speed.

[Background of the invention]

In a machine that aims to speed up processing by processing multiple instructions in parallel, these processes specify the use of the same register even though there is no dependency between the data to be processed in parallel. For this reason, parallel processing may be inhibited, leading to a decrease in processing performance. In order to eliminate this factor that inhibits parallel processing caused by the repeated use of the same register, a method called the virtual register method was proposed in a patent application filed in 1973.
No. 8-237777.

According to the virtual register method, the general-purpose register specified by an instruction is a logical register seen from the programmer and is called a logical register. Also.

Registers that actually hold operation results are called physical registers, and are dynamically associated with logical registers. If instructions to be processed in parallel specify the same logical register, different physical registers are assigned to each, so
The above factors inhibiting parallel processing can be removed.

In the virtual register method, a new physical register is frequently assigned to a certain logical register, but this requires complex state management control of the physical register using control signals from the functional block that uses the physical register. It was necessary to do this.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an information processing apparatus having a simple and effective register allocation method that does not involve control from other functional blocks.

[Summary of the invention]

In order to achieve such an object, the present invention stores the numbers of physical registers that are not allocated to logical registers in a queue, and when a new physical register allocation request is received, the numbers of physical registers to be newly allocated are stored in a queue. Dynamic physical register allocation is performed without involvement of control from other functional blocks by taking the number of the physical register from the queue and using it, and then returning the freed physical register number to the queue. It is unique in that it makes it possible.

(Embodiments of the Invention) The present invention will be described in detail below.For convenience of explanation, a machine based on Hitachi's M series architecture is assumed.

FIG. 2 shows a typical instruction format. Section 2(a)
The figure shows an instruction format called the RR format, in which the operation specified in part 02 uses the contents of the general-purpose register specified in part R1 as the first operand, and the contents of the general-purpose register specified in part R2 as the second operand. is executed as Second (b)
The figure shows an instruction format called the RX format, in which the contents of the general-purpose register specified in the R1 part are combined with the contents of the general-purpose register specified in the first operand, x2 part, and 82 part, respectively.
The operation specified in part 02 is executed using the contents of the memory indicated by the address obtained by adding the contents of part 2 as the second operand.

The third @ shows the overall configuration.

Instruction register 1 holds instructions to be processed. The logic for setting an instruction in the instruction register is not necessary for explaining the present invention, and can be configured using a known technique, so it is not shown in the drawings and its explanation will be omitted. The command held in the command register 1 is sent to the command decoder 2 via the signal line rNS.

The instruction decoder 2 decodes instructions and generates and outputs various control signals and operand addresses. Among these control signals, the meanings of those necessary for explaining the present invention are as follows.

1) OPC: This is part 02 of the instruction and specifies the type of operation to be executed by the operation unit 7.

2) FTP: Indicates that the decoded instruction is an instruction to read an operand from memory.

3) STP: Indicates that the decoded instruction is an instruction to insert the operation result into memory.

4) A[)R: Specifies the address to read the operand from the memory or the address to write the operation result to the memory.

5) NDP: Indicates that the decoded instruction is an instruction to read an operand from a general-purpose register.

6) CHP: Indicates that the decoded instruction is an instruction to write an operation result to a general-purpose register.6) ASP: Indicates that the decoded instruction is an instruction to allocate a new physical register to the logical register specified by the instruction. Show that.

8) LRI: Specifies the logical register number from which the first operand is to be read.6 9) LR2: Specifies the logical register number from which the second operand is to be read.

10) LWR: Specifies the logical register number into which the operation result is to be written.

OPC is for operation units 1 to 7, FTP and STP.

ADH is sent to the storage unit 6, NDP, CI (P is sent to the register unit 5, ASP, LRI, LR2°LWR is sent to the virtual register control circuit 4, and used to control each functional block.

The decoding control circuit 3 sends a signal D when the decoding of the instruction is completed.
Setting S to 1 indicates that a new instruction may be set in instruction register 1. When the decoding of an instruction is inhibited by a certain factor, the decode control circuit 3 sets DS to O to inhibit setting of a new instruction to the instruction register 1. The functions and configuration of this decoding control circuit are the same as those in conventional information processing devices, and are unnecessary for the description of the present invention, so
Details are omitted.

The virtual register control circuit 4 manages the conversion of logical register numbers to physical register numbers and the new assignment of physical register numbers to logical register numbers. An overview will be given here, and details will be given later.

The virtual register control circuit 4 has a conversion table that maintains the correspondence between logical register numbers and physical register numbers. When the signal ASP requesting new allocation is O, the logical register number LRI.

By indexing the conversion table, LR2 and LWR are converted into physical register numbers PRI and PR2°PWR, respectively, and sent to the register unit 5. When ASP is 1, LR1 and LR2 are similarly converted to PRI and PR2, but LWR undergoes a different conversion process. first,
Set the physical register number that is not currently registered in the conversion table to 1.
Then, the physical register number of the entry in the conversion table corresponding to the LWR is rewritten to the selected physical register number. A new physical register number is now assigned to the logical register number LWR.

The register unit 5 has physical registers for holding calculation results. Control of the register unit 5 is performed by 16
There is almost no difference from the conventional system, except that the general-purpose registers of the book have been replaced with 16 or more physical registers. That is, when the register successive output request signal NDP is 1, PRY.

The contents of the physical register specified by PR2 are read as the first operand and second operand, respectively, and the signal line O
It is sent to the arithmetic unit 7 via LR and 02R. Further, when the register write request signal CT (P is 1), the operation result sent from the operation unit 7 via the signal line RST is written into the physical register designated by PWR.

The storage unit 6 is composed of a memory and its control circuit. When FTP is 1, the storage unit 6 reads the operand from the memory address indicated by ADH and sends it to the signal line 02.
It is sent to the arithmetic unit 7 via M. Further, when STP is 1, the calculation result sent via R3T is written to the memory address indicated by ADH.

The calculation unit 7 executes the calculation specified by the oPC. The first operand is obtained via OIR. The second operand is obtained via either 02R or 02M depending on the type of operation. The calculation result is sent to the register unit 5 and storage unit 6 via R5T.

! ts1 shows the internal configuration of the virtual register control circuit 4.

The conversion unit 41 manages a conversion table (hereinafter referred to as RxT) 411,
Convert logical register number to physical register number. RX
T411 holds the number of the physical register assigned to each logical register in the entry corresponding to the logical register.

Therefore, by indexing RXT 411 with a certain logical register number, the number of the physical register assigned to that logical register can be obtained. Logical register numbers LRI and LR2 specifying read registers are set to 1 or more.

These are converted into physical register numbers PRI and PR2, respectively.

For writing to a register, write that write.

The operation differs depending on whether it is performed on an already allocated physical register or a newly allocated physical register. Whether or not to allocate a new physical register to the write register is determined by the physical register allocation request signal ASP. In the case of ASP'hSO,
Since no new physical register is allocated, the logical register number LWR specifying the write register is RXT
By indexing 411, the physical register number PW
Converted to R. If ASP is 1, a new physical register is allocated to the logical register specified by the logical register number LWR. The physical register to be newly allocated is specified by the allocated physical register number PAS sent from the queue section 42. The conversion unit 41 is.

Regardless of the logical register number specifying the write register or the value of WR, the value of PAS is sent as is as the physical register number PWR. Next, it is necessary to reflect this new allocation of physical registers in the RXT 411°.

For this purpose, first, RXT4 with logical register number LWR.
The physical register number obtained by indexing 1L is output to the released physical register number PRL and sent to the queue section 42.

This is to reuse the released physical registers. Then, RXT4 corresponding to the logical register number LWR
The newly allocated physical register number PAS is registered in entry No. 11.

The queue part 42 is a physical register number queue (hereinafter referred to as PRQ).
)421. All physical register numbers not registered in the RXT 411 are held in the PRQ 421. PR0421 sets the entry point to an inpointer (hereinafter referred to as QIP
)422. Exit point out pointer (hereinafter referred to as QOP) 42
First in/first out (F
Configure a queue for IFO) control. It is not necessary to configure this FIFO queue in this way; for example, it may be configured using a shift register.

The queue part 42 is the PRQ4 indicated by the QOP423.
The contents of 21 are output to the conversion unit 41 as the physical register number PAS to be newly allocated. The value of this PAS is actually used by the conversion unit 41 when the physical register allocation request signal ASP is 1, as described above. At this time, the cue section 42 performs the following operations.

First, the released physical register number PRL sent from the conversion unit 41 is converted into the PR indicated by the QIP 422.
It is held in the entry of Q421. And QIP422
, QOP423 is incremented. This increment causes PRQ 421 to operate as a FIFO queue.

Since the length of PRQ421 is finite, QIP422,
Incrementing QOP423 causes it to wrap around with PRQ421.

Thereby, the PRQ 421 can be thought of as a ring with the lower end and the upper end connected, and each entry of the PRO 421 can be reused.

FIG. 4 shows the new physical register allocation operation. FIG. 4(b) shows the state after processing the addition instruction AR2, AR3 from the state of FIG. 4(a).

Figure 4 shows RXT411 and PRQ421 (a part of the 71 contents, and the PRQ commanded by QIP422 and QOP423).
421 entries are shown. Also, this addition instruction performs addition with the contents of logical register number 2 (hereinafter abbreviated as LR#2) as the first operand and the contents of LR#3 as the second operand, and stores the operation result in LR#2. This means that the 6I2XT 411 holds in the entry corresponding to the logical register number the number of the physical register that is assigned to that logical register. In the figure, for example, physical register 3 is used for LR#O.
No. 3 (hereinafter abbreviated as PR433), PR for LR#1
#7 is assigned.

The PRQ 421 queues physical register numbers that are not assigned to logical registers. In the figure, the number of the physical register that was released the earliest and should be allocated when requested is 13, and! &
The number of physical registers released later is 15, and the numbers of physical registers released during that time are queued in order.

The operation when the addition instruction is decoded in this state will be described below.

First, the physical register number that specifies the physical register from which the operand is to be read is the read logical register number.
411. Therefore, read logical register numbers 2.3 are converted to physical register numbers 19.1, respectively. Next, a physical register number designating the physical register into which the operation result is to be written is determined.

Assuming that the addition instruction requests allocation of a new physical register, in this case, the contents of the entry of PRQ 421 pointed to by QOP 422 become the write physical register number. Therefore, the write physical register number is 13. In the end, the addition instruction adds the contents of PR#19 and PH10 and stores the result in PR#13.

Furthermore, new physical register allocation is made to RXT411.
, the cell needs to be reflected in PRQ421. for that,
Register the physical register number specifying the newly allocated physical register in RXT411, and register the physical register number specifying the freed physical register in PRQ4.
Queue on 21. In detail, physical register number 19 held in the entry of RXT411 corresponding to write logical register number 2 is written to the entry of PRQ421 indicated by QIP422, and QOP42
Write physical register number 13 held in the entry of PRQ421 pointed to by RXT411(1)xintrini! corresponding to write logical register number 2! *L,
Then, Q I P422°QOP423 is incremented.

The number of physical registers when a machine is constructed using the present invention will be described below.

When dynamically allocating registers as in the present invention, the number of physical registers is generally required to be greater than the number of logical registers (for example, 16 in the ■ series architecture), and if this is the case, conflicts may occur. However, when trying to speed up processing by processing multiple instructions in parallel, ! It is important that instructions to be processed in parallel do not specify the use (rewriting) of the same physical register.6 This is because the factors inhibiting parallel processing caused by the repeated use of the same register can be completely removed. In addition, the logic for detecting repeated use of the same register and the logic for queuing processing upon detection can be omitted, and the amount of hardware can be significantly reduced. Therefore, a sufficient number of physical registers should be prepared to prevent repeated use of the same physical register, and the number n can be determined as follows. In other words, among the instructions processed in parallel in the machine at any given time, the maximum number of instructions from the earliest to the latest instruction is N.
In other words, if the maximum number of instructions that may start processing before the processing of a certain instruction is completed is N, then the largest register that can be rewritten by these N instructions is and the number of registers being allocated, that is.

The sum with the number of logical registers is the minimum number n of physical registers that should be prepared. In a machine that does not allow overtaking of instruction processing, the number N of instructions can always be determined uniquely, but in a machine that allows unlimited overtaking of instruction processing, C cannot determine the number N of instructions. However, if a limit is placed on the overtaking of instruction processing, the number N of instructions can be uniquely determined even in such an instruction processing device.

In a machine configured using the present invention and having n or more physical registers obtained as described above,
The following shows that instructions processed in parallel do not use the same physical registers.

First, instruction i specifies writing to LR#R and newly writes PR.
Suppose that #p is assigned6, then instruction 3j is assigned to LR#
If you specify the addition to ρ, PR#p will be released and its physical register number p will be returned to PRQ421.
What is the length of Q421?

The physical register number p returned to PRQ421 is the value obtained by subtracting the number of physical registers from the number of physical registers, and is greater than the maximum number of registers that can be rewritten by N instructions.

It will not be reallocated until at least N instructions have been processed. At this time, the processing of instructions before instruction j, including instruction i using PR#p, has already reached N7. Therefore, instructions processed in parallel do not use the same physical register.

However, as described above, the number n of physical registers described here is not essential to the present invention.

〔Effect of the invention〕

As described above, according to the present invention, control signals from other functional blocks are not involved.

Since dynamic register allocation control is possible with only one functional block (virtual register control circuit 4), the control can be simplified. In addition, if you prepare more physical registers than the number of registers used by the maximum number of instructions that can be processed in parallel, you can not only completely eliminate the factors that inhibit parallel processing caused by the repeated use of the same register, but also This has the advantage that it is possible to omit the logic for detecting repeated use and the logic for queuing processing upon detection.

[Brief explanation of the drawing]

The figures are all related to the present invention; Fig. 1 is an internal configuration diagram of the virtual register control circuit, Fig. 2 is a diagram showing a typical instruction format, Fig. 3 is a diagram showing the overall configuration, and Fig. 4 is a diagram showing the overall configuration. FIG. 3 is a diagram showing the operation of a virtual register control circuit. 1...Instruction register, 2...Instruction decoder, 3...
・Decode control circuit, 4...virtual register control circuit,
41... Conversion unit, 411... Conversion table (RXT), 4
2...Queue part, 421...Physical register number queue (PRQ), 422...In pointer (QIP)
. 423...Out pointer (QOP), 5...Register unit, 6...Storage unit, 7...Arithmetic unit. "I-+■ ¥-20 (α) V, 2nd item (17) Continuation of the 3rd page Shigeo Kazamata Hitachi Ultra LSI Engineering Co., Ltd., 14791 JJ, Kodaira City

Claims (1)

[Claims] 1. In an information processing device that processes a plurality of instructions in parallel, one or more first registers are logically specified by the instruction, and one register actually holds the operation result of the instruction. or a plurality of second registers, and a first register holding the number of the second register assigned to the number of the first register.
and second means for holding a second register number that has not been assigned to the first register number, and assigning a new second register to the first register. When a request is made, the number of the second register to be newly allocated is taken out from the second means and held in the first means, and the number of the second register to be newly allocated is taken out from the first means, and the number of the second register to be newly allocated is taken out from the first means. An information processing apparatus characterized in that dynamic allocation of a second register to a first register is performed by returning the number of the register to the second means.