JPS61134794A - Image memory circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sequential scanning display device used as a display device of an information processing device. In particular, the present invention relates to a display device that rotates an image by 90 degrees.

INDUSTRIAL APPLICATION This invention is utilized for the CRT display apparatus which handles an image, a printer apparatus, an image storage circuit used in a printer apparatus, etc.

[Conventional technology]

Conventionally, when images are temporarily stored in a sequential scanning type display device, a common method is to store image data for one screen in an image memory, and to sequentially read out the image data from the image memory in synchronization with scanning and display the data. In this case, the image memory has a structure suitable for reading out in the order of main scanning of the screen, and 8-bit or 16-bit image data can be obtained with one reading, and the image data is stored in the image memory. Things are common.

[Problem that the invention seeks to solve]

However, when using such an image memory and displaying an image rotated by 90 degrees, even if 8 or 16 bits of data in the row direction are read out in one readout, the valid data in the column direction will be Since the image data is 1 bit, it is not possible to display 90'' rotation at a constant speed unless the readout speed of the image data is increased accordingly.
If the storage method is such that the image data obtained in one readout is, for example, 4×4, then when rotating an image, the effective image data obtained in one readout is 4×4.
Of these, the valid data in the column direction is 1.
It is a bit, and the usage efficiency is 25%. For this reason, there is a drawback that a readout capability that is four times higher than the scanning speed is required.

The present invention eliminates the above-mentioned drawbacks, and enables instantaneous switching between the main scanning direction and the sub-scanning direction, making it possible to effectively use all the read data.・When scanning in one row direction, it also scans in the column direction. It is an object of the present invention to provide an image storage circuit which can be used at the same successive speed.

[Means for solving problems]

The present invention provides an address conversion circuit that generates a column-direction main address signal, a row-direction main address signal, and a sub-address signal based on a given write/read selection signal, read-out direction selection signal, and address signal, and a column-direction main address signal in the read mode. and a storage circuit that outputs N×N bits of data corresponding to the main address in the row direction, and stores N bits of write data in the write mode in positions corresponding to the main address in the column direction, the main address in the row direction, and the sub address. , in write mode,
A write data expansion circuit generates N×N write data from given N bits of write data, and in a read mode, the N×N output of the memory circuit is made to correspond to a matrix of N rows and N columns. When the read direction selection signal is in the row direction, one of the N rows is selected according to the sub-address signal output from the address conversion circuit.
A first read data selection circuit selectively outputs bit data, and when the read direction selection signal is in the column direction, the N bits of one column from among the N columns are selected according to the sub address signal output from the address conversion circuit. It is characterized by comprising a second read data selection circuit that selectively outputs data, and a third read data selection circuit that outputs the read direction selection signal in a manner opposite to that in the row direction.

[Effect]

N-bit write data is converted into N sets of data with the same content,
That is, the expanded data is expanded into N×N bit matrix data and written into the storage circuit at the same time. Reading is performed simultaneously for each N×N bit of data. Then, from the read matrix data of N×N bits, either N-bit data in the row direction or N-bit data in the column direction is selected according to the selection signal, and the read data is Output as .

Therefore, the writing and reading speeds are the same as in the past, and all parts of the read data can be used.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

In this embodiment, the size of the image memory is 1024 bits in each of the row and column directions. Further, it is assumed that the data read in one access is 8 bits.

FIG. 1 is a block diagram showing the entire image storage circuit according to an embodiment of the present invention. The output of the address conversion circuit 1, which is supplied with the address signal a, the write/read selection signal C1, the read direction selection signal d, is coupled to the storage circuit 2 by the column direction main address signal f1, the row direction main address signal g, and the sub address signal k. . The sub address signal is input manually to the write data expansion circuit 3, the first read data selection circuit 4, and the second read data selection circuit 5. The output of the write data expansion circuit 3 to which the write data b is input and the successive write selection signal C are input to the memory circuit 2. The third read data selection circuit 6, the second read data selection circuit 5, and the first read data selection circuit 4 include:
A read direction selection signal d is input to each. Further, the output i of the storage circuit 2 is connected to the input of a third read data selection circuit 6 via the first and second read data selection circuits 5 described above.

FIG. 2 is a diagram showing details of the memory circuit 2 of FIG. 1.

Output a1 of the decoding circuit 7 to which the sub address signal k is input
The outputs C3I to C38 of the AND gate circuit 8 of ~a8 and the write/read selection signal C are input to the storage section 9. For example, the sub address signals are Am, ASI, A,. A decoding circuit 7 in which only one of the outputs a1 to a8 becomes "0" due to the combination shown in FIG. The output of 7 is used as a memory element operation control signal.
・・・〜°・・′! ″b-ctlゝ・!1JiA, bm,
7>r, 11 A gate circuit 8 in which all of cs+ to cse are "0" when the selection signal C is "0", that is, in a read mode, and a 1-bit memory element each having a depth of 64 mm. The storage unit 9 is constructed by arranging eight C1j (ij=1 to 8) in a matrix in the row direction and the column direction. Here, when the storage element operation control signal cs+""cse is "0", the connected storage element ctj (ij=1 to 8) is enabled. C31 enables Cw (j=1 to 8) to operate. cS
I is Cy (j = 1 ~ 8), cst is Cl7 (j = 1 ~
8), csff is C5j (J1 to 8), C34 is C41 (j=1 to 8), Cll5 is C5j (j-1 to
8), C3& is C6j (j-1 to 8), cl is 07j
(j=1-8), and C38 is connected to C5j (J=1-8), respectively.

FIG. 3 is a diagram showing the correspondence between the storage memory of the storage circuit 2 and images. Image data is stored after being decomposed into sub-matrices 5aj (ij=1 to 128) consisting of 8.times.8 bits.

Figure 4 shows a submatrix S consisting of 8x8 bits.
It is a figure which shows the correspondence between +J (1%J=1-128) and an image.

FIG. 5 is a diagram showing the functions of the address conversion circuit 1 in FIG. 1, and shows column-direction main addresses for each of the write mode, row-direction read mode, and column-direction read mode, for example, A1+6 to A, 1. , and row direction main address AV6~
It is a diagram showing the correspondence between AvO and sub-addresses AS2 to A S +1 and addresses A16 to A0 given from the outside.

FIG. 6 is a diagram showing the function of the first read data selection circuit 40 that operates in the row direction read mode, and is a diagram showing the function of the first read data selection circuit 40 operating in the row direction read mode. 0 (FIG. 5), which 8 bits of the output DRzz (is j = 1 to 8) of the memory circuit 2 are DS7 to D. FIG.

FIG. 7 is a diagram showing the function of the second read data selection circuit 5 that operates in the column direction read mode, and corresponds to the sub address A. -A. The output DR of the memory circuit 2 (ij
8) is a diagram showing which 8 bits of =1 to 8) are output as Di7 to I)so.

When the image storage circuit of the above embodiment is used, the signals given from the outside are address signal a1, write data b, write/read selection signal C, and read direction selection signal d, and other timing signals are omitted. It is assumed that the "weight" of the bits A16 to A0 of the address signal a is such that Ao is the lowest and Al1 is the highest. The address signal a applied from the outside is set to the column direction main addresses AX6 to Axo and the row direction addresses Ay6 to Ay6, as shown in FIG.
Ayo and sub-addresses A3z~A5. Output. Here, X6~τ. indicates a negative logic symbol of A6 to A0.

The write data expansion circuit 3 receives 8 bits (1 row) of write data b (D) given from the outside in the write mode.
, ~no) into 8 lines of data where the contents of each line are exactly the same, and 1. ~D, output as 11111. Hereinafter, "Wj" means "write" and "rRJ" means "read". The memory circuit 2 has a column-direction main address A in the read mode. ~AXO and row direction main address Ay,
When ~Ay0 is given, the corresponding submatrix 31J(i
3= D R+ the image data stored in 1 to B)
Output as +~DRsg. In addition, in the write mode, write data DI output from the write data expansion circuit 3, 1. ．． ~DI,, lll+ as column direction main address A, L6~A y O1 row direction main address A
Submatrix S+j (ij
=1-128), sub-addresses A, 2-A,. Store only in the row selected by .

The first read data selection circuit 4 operates only when the read direction selection signal d is in the row direction mode, and selects the sub-address A sz "-A 3 output from the address conversion circuit 1.
Submatrix 5iJ (ij=1~12B) by 0
8 bits in the row direction are selected from the data DR, . . . -DRe++ as shown in FIG.

Output as .

The second read data selection circuit 5 operates only when the read direction selection signal d is in the column direction mode, and operates according to the sub-addresses A...~A... output from the address conversion circuit 1.
Then, 8 bits in the column direction are selected as shown in FIG. 6 from among the data DR, .

~D. Output as .

As shown in FIG. 8, the third read data selection circuit 6 selects D when the read direction selection signal d is in the row direction mode.
-'I-D s. , and outputs it as ~D0, which corresponds to the column direction mode.

Next, the operation of the memory circuit 2 will be explained using FIG.

When the sub-address k is 0, the decoding circuit 7 only sets al to “
a1 outputted from the decoding circuit 7 which selectively sets a3 to a8 to "0" when the values are 2 to 7.
~a8 is connected to the gate circuit 8, and the write/read selection signal C and negative logic are ORed, and cs+~
It is output as SS8 and connected to the storage section 9. When the write/read selection signal C is "0", that is, in the read mode, cs and %css are all "0", and all of the storage elements Cij become operable regardless of the sub-address k. Further, when the write/read selection signal C is "I", that is, in the write mode, one of C5t (j=1 to 8) selected by the sub address k becomes "0". Therefore, only the memory elements to which C□ (i=1 to 8) that has become "0" are connected become operable.

Next, the operation in the write mode will be explained.

The write data b given from the outside is 8 from D7 to D0.
This bit is connected to the write data expansion circuit 3. This write data expansion circuit 3 writes write data b, DWII~D W s +, D, DW, □
~D W, , D, D8.3~D183, D4 D%
4,4~D approval. 4. DS Ri. 1. ~I)+IS, D2
pw+6 ~ Dumb, DI DIII, ~D-81
, Do is expanded to D11111 to DIllll+ and obtained by expanding. , 1 to D, 4es are provided to the memory circuit 2.

On the other hand, an address signal a given from outside the device is converted by an address conversion circuit 1 into a column direction main address f, a row direction main address g and a sub address.
given to. Submatrix 5iJ (iS j-1 to 1
28) is selected, and the submatrix s! selected by the subaddress k is selected. A row within j (i, j=1 to 128) is selected and the write data is stored. Next, the operation when the operation mode is the row direction read mode, that is, the image stored in the storage circuit 2 is read out "without rotation" will be explained.

The address signals acA+b to AO) applied from the outside are incremented by 1 starting from 0. When the address signal a is 0, the column direction main address f and the row direction main address g given to the memory circuit 2 are both O, and as shown in FIG. submatrix 8 of
1.1 image data is read data i DRl, ~D
Rall (FIG. 6). At this time, since the sub address is also 0, the first read data selection circuit 4
From DR, which is the data of the first row of the submatrix 81.1, to DR111 8. ~I) is output as to (Figure 6).

From the third read data selection circuit 6, D3. ~D.

is output as is as read data e, ~Do (FIG. 8).

Similarly, the main 7 addresses f in the column direction to the memory circuit 2 increase sequentially until 127 sub-matrices S1.1, S+, t,
Each submatrix S1.S+, s'-3+, +ia in this order.
l~S1. The data in the first row of llI is read out sequentially (FIG. 3). When the address signal a becomes 128, the column direction main address f and the row direction main address g applied to the memory circuit FIPi2 become O again, and the submatrix S3. ,
is selected. At this time, since the sub address is 1, the first read data selection circuit 4 selects the sub matrix S.
DRlI-DR211 which is the second line data of 3.1
(For example, FIG. 6) is output. Thereafter, the submatrices S1.1 to S are used until the column direction main address f becomes 127 again.
5. The data in the second row of 1□8 is read out sequentially.

The above operations are repeated for sub-matrices 81.1 to S3.
When reading up to the 8th row of 1□8 is performed and the address signal a further increases by 1, the row direction main address g to the storage circuit 2 increases by 1, and the column direction main address f and sub address k become O. . Therefore, the column direction main address f is 0 to 12.
When changing to 7, S... 1~S2. I□
The first row of 8 is sequentially read out. By repeating the above operations, all of the image data stored in the memory circuit 2 is read out in order in the row direction as the address signal a increases.

Next, the operation mode is "rotate" in column direction read mode.
The operation in this case will be explained.

The address signal a applied from the outside is incremented by 1 starting from 0 as in the row direction read mode. The address signal a is converted by the address conversion circuit 1, and the address signal a is converted by the address conversion circuit 1.
The lower 6 of the address signal a is used as the main address g in the row direction.
Bisoto negative logic A6 to 80 are given, and A, which is the upper 6 bits of the address signal a, is given as the column direction main address f.
16 to A 16 are given.

In addition, A9 to A of address signal a are used as sub-addresses,
is given. First, when the address signal a is 0, the main address g in the column direction is 0, and the address in the row direction is 127. Therefore, from the storage circuit 2, the image data of the submatrix S1□81 is read from the read data i DR++ to DR111.
Output as 1. In addition, in the column direction read mode, the first read data selection circuit 4 does not operate, and the second read data selection circuit 5 operates, and depending on the subaddress k, DR, which is the data of the first column of s+ge, +, 1~D
R+, + are outputted as second data, which is further converted by the third read data selection circuit 6 as shown in FIG. 8 to read data e.
is output as

Next, when the address signal a increases by 1, the row direction main address g decreases by 1 and becomes 126, so the subma, trix S, . ．． ．． , the data in the first column is read out. Similarly, when the address signal a becomes 128, the main address g in the row direction becomes 127 again and the sub address becomes 1.

The column direction main address f is 0.

Therefore, submatrix 3 1211. The image data of the second column of l is read out, and thereafter the row direction address signal g
submatrix S+zs. until becomes "0" again. ＋〜
The second column image data of 51.1 is read out.

Repeat the above operations until Sltll. l ””'S1. I
When the reading up to the 8th column is performed and the address signal a further increases by 1, the column direction main address f becomes 1,
The main address in the row direction is I27 and the subaddress is 0, so the submatrix 81□. The image data in the first column of No. 2 is read out. After repeating the above operation, address signal a becomes O
The image data stored in the storage circuit 2 is sequentially read out in the column direction when the image data is sequentially increased from .

As described above, "reading out sequentially in the column direction" is equivalent to "rotating the image data stored in the storage circuit 2 by 90 degrees clockwise."

〔Effect of the invention〕

As mentioned above, the memory circuit is configured with N×N memory elements, and the column-direction main address and the row-direction main address are converted using the address conversion circuit that outputs the column-direction main address, row-direction main address, and sub-address from the address signal. By setting N×N image data as an address of an N×N storage element and reading out N×N image data at once, and changing the readout direction selection signal by selectively outputting the necessary data using the sub-address according to the scanning direction. A device can be obtained in which the reading direction can be changed instantaneously, the reading speed is equivalent to the speed of the data being used, and all of the read data is effectively used.

[Brief explanation of the drawing]

FIG. F is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a detailed configuration diagram of the memory circuit shown in FIG. 1. FIG. 3 is a diagram showing the correspondence between the storage memory of the storage circuit and images. FIG. 4 is a diagram showing the correspondence between the submatrix of FIG. 3 and images. FIG. 5 is a diagram showing the function of the address conversion circuit. FIG. 6 is a diagram showing the function of the first read data selection circuit. FIG. 7 is a diagram showing the function of the second read data selection circuit. FIG. 8 is a diagram showing the function of the third read data selection circuit. 1...address conversion circuit, 2...memory circuit, 3...
・Write 1 Write data expansion circuit, 4...
First read data selection circuit, 5... Second read data selection circuit, 6... Third read data selection circuit, 7... Decode circuit, 8... Gate circuit, 9
...Storage unit, a... Address signal, b... Write data, C... Write/read selection signal, d...
・Reading direction selection signal, e...reading data, f
... Column direction main address, g... Row direction main address,
h...Extended write data, i...Submatrix read data, j...Row/column read data, k.
...Sub address signal, CBI~cse...Storage element operation control signal. Agent Patent Attorney Naotaka Ide 111th Edition 1986-
134794 (9) Rotation 0 ψ ψ OO. 6 + A φ N L/1 Oo. l+lL/IL/IOOn! I ψ N

Claims (1)

[Claims] (1) A memory circuit in which image data is stored, a means for writing write data given from the outside into this memory circuit, a means for reading data stored in the memory circuit, and an address for supplying an address signal to the memory circuit. The reading means and the addressing means include means for outputting the data stored in the storage circuit as read data of a second image rotated by 90 degrees from the first image in which the data is written. In the image storage circuit including the above-mentioned writing means, the above-mentioned write data N bits (N
is multiple) and then converts it into N pieces of data with the same content (hereinafter referred to as "N×
"N bits of data." ), the memory circuit is configured to be able to store this N×N bit data, and the reading means reads data from the memory circuit. N
A first read data selection circuit that selects N pieces of data in the row direction corresponding to the data of the first image and corresponding to the data of the second image when the data of each ×N is set as a matrix. a second read data selection circuit that selects N pieces of data in the column direction, and a second read data selection circuit that outputs data selected by either the first read data selection circuit or the second read data selection circuit as read data. 3. An image storage circuit comprising a read data selection circuit.