JPS61131142A - Lru mechanism - Google Patents

Abstract

PURPOSE:To detect surely a page with low operating frequency without detecting an uncertain page by detecting a page of level 0 in searching so as to execute page-out/in of the said page. CONSTITUTION:When a search request takes place, a search controller 12 brings all of parallel data input DI and load terminals LD of an LRU address counter 13 to H level 1, brings U/D terminals to L level 0 to allow the counter 13 to start down-count. At each count of the counter 13, the count is outputted to a page table 3 via an address line 130 to access the table in the order of high- order. Then 2 bits of page-in information are fed to a reference comparator 6 via an bus DB. The comparator 6 is a circuit detecting a minimum value of a reference value in the page table 3 having a tri-state value and every time the count is decremented, a reference bit of each page is fed to the comparator 6.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a computer system, and in particular to a memory management unit (MMU) that manages a storage device according to a virtual storage method to effectively utilize the storage device. (LRU) mechanism.

[Conventional technology]

In computer systems that require a large amount of memory, systems using virtual storage (VS), that is, virtual memory, are often used. ``vS is a storage system that operates as if there is a larger amount of memory than the actual memory by managing the actual real memory with a memory management unit (MMU). For example, v and s are divided into tens of bytes (pages) and managed by the MMU, and when necessary, they are read out from the auxiliary storage device described above in page units and stored in real memory ( On the other hand, pages that are not needed are stored in auxiliary storage in page units (page-in).
(page out), opens and passes that real memory page to the page that needs it. Memory is managed using the methods described above, but in order to prevent an increase in the number of pages when the memory capacity of virtual memory is further increased, multiple pages are treated as one segment and they are further managed in segment units. .

In some cases, the vS system described above may be expanded into a system (multi-virtual storage, MVS) that supports multiple computer users on a one-to-one basis and operates as if each computer user had exclusive virtual storage space. In some cases. In the case of the MVS system, in addition to the above-mentioned pages, this is used to manage virtual memory for individual users.

A continuous text is provided for each user, and page-in and page-out between the real memory and the auxiliary storage device are managed using the continuous text, segments, and pages.

On the other hand, the above-mentioned MMU generally uses a management method called the LRU method (Least Recently Sent Rule). This LRU method is a method of paging out old pages, i.e. pages that have not been accessed by the computer for a certain period of time, and pages that are infrequently accessed, and page-in necessary pages. This is based on the assumption that a page that has been previously accessed is unlikely to be accessed at all in the future. The MMU consists of the LRU unit that manages the pages stored in the real memory mentioned above and a table that manages each page allocated to a VS or MVS address.

Conventionally, two methods were used to manage old pages in the LRU section mentioned above.
value (1 bit) was used. In other words, for example, if the binary values corresponding to the access frequency are level O and level 1, when the level is 0, the page existing in the real memory is an old page, and when the level is 1, it is likely that it will be used in the future. is stored in the page table as a high page (new page), and when it becomes necessary to page in another page, the level 0 page is paged out, and the page to be paged in is stored in the page table as level 1. , and then stored the page in real memory. When the newly stored page is not used for a specific period of time after processing, the level stored in the page table is set to 0 level.

When a new page is to be paged in as described above, the page table is referred to, and the page where the O level is detected in one phosphorescent period is paged out and the new page is stored.

In the conventional method described above, the detection of the 0 level is simply the order of the page table, and furthermore, the detection of the 0 level is simply the order of the page table, and the pages that have become 0 level without being accessed for a specific time and the 0 level pages that have not been accessed for a much longer time than the specific time. In some cases, pages that have not been accessed for a long time and remain in real memory may be left as they are, and pages that have just reached level 0 may be paged out. A page that has just reached level 0 has the possibility of being accessed again, and there are cases where it is necessary to page in again. Naturally, page-in and page-out require time to store from real memory to auxiliary storage, and further time to store from auxiliary storage to real memory, which results in a lot of wasted time in the above-mentioned cases. He was taking care of himself.

[Objective of the Invention] The present invention is intended to solve the above-mentioned problems, and its purpose is to reduce unnecessary page-out and page-in operations, and to speed up the execution processing time of the computer system by using VS (virtual storage). ) To provide an LRU mechanism for the memory management unit (MMU) of the system.

[Structure of the invention]

The present invention is characterized by a memory management unit that manages virtual memory on a page-by-page basis, and a page table that stores the levels of multiple pages stored in real memory, and a memory management unit that manages virtual memory on a page-by-page basis. and LRU means for lowering the level, and the level is three or more values.

(For production) ■An old page in MMU processing of the S system.

There are multiple levels for managing new pages, and the levels are lowered after a certain amount of time has passed.

When that page is accessed within a certain time, the level is increased, and when a page that does not exist in real memory is accessed, the lowest level page stored in real memory is paged out and a new page is created. is stored in real memory.

[Embodiments of the invention]

The present invention will be described in detail below using one drawing.

FIG. 1 is a configuration diagram of an MMU according to an embodiment of the present invention. The address buffer 1 stores a logical address from a CPU (not shown), and sends a continue text and a segment number to each circuit making up the MMU.

Each specific field of page number and offset is added. That is, the logical address signal consists of a total of 4 bits for the continuous text, 9 bits for the segment number, 4 bits for the page number, and 10 bits for the address offset. The continuous text is a number assigned to correspond to the user currently using the computer system.
1 can be used by up to 16 users at the same time.

As described above, the segment number is an address that indicates the number of one segment, which is a set of a plurality of pages allocated to each user, for example.

A total of 13 bits, 4 bits of continuous text and 9 bits of segment number, are output from address buffer 1 and added to the address of segment table 2.
Specify a specific segment table 2. Segment table 2 is a table consisting of 8 bytes, and stores the page table address corresponding to the segment number of a specific user. Give to 3. The above-mentioned correspondence means to indicate in which position in the page table 3 the page management data specified by the continuous text and the segment number is stored. on the other hand.

In the embodiment of the present invention, 512 pages are allocated to each segment, and page numbers specifying pages within these segments are also output from the address buffer and added to the page table.

Therefore, a total of 12 bits, 8 bits of S in segment table 2 and 4 bits of the page number of address buffer 1, are added to page table 3 as an address.
Page management data corresponding to the logical address signal in address buffer 1 is output from page table 3.

FIG. 2 is a data configuration diagram showing the data configuration of page management data output from the page table 3. In the vS system, there are many users.

There are various ways of using the area, such as using the area in common or accessing a specific user area by many users. Page management data manages this.
The bits (b23 to b19) are page information.

Fixed bit (Fix) b23 is a reference bit (REFERENCE A, B) that corresponds to the access frequency level described below when this bit is 1.
0.

21 is fixed and does not change depending on the state of use. Change bit b22 is reference bit (RHFERENCIE A, B) page valid pit (PAGIl+VALID) b
This bit indicates that 19 etc. can be changed. Reference bits (RHFERENCE A, B) represent the usage frequency status of the page currently corresponding to the table2.
It's bit. Page Valid (PAGE! VALI
D) is a bit indicating that the memory page currently specified in the page table is valid.

Protection data from bits 18 to 13 are read by the user or supervisor.

It is composed of 6 bits representing the possibility of writing and execution. User read (USERREAD) b 13 is a bit indicating whether the user can read the area, and user write (USERWRITE)
b14 is a bit that indicates whether or not the area can be written by the user.
REXECUTION) b 15 is a bit indicating whether the area is executable. Supervisor read (SUPERVISORREAD) b 16 indicates whether the area is readable by a supervisor, for example, a system program, and Supervisor write (SUPERVISORWRITE) b
17 is.

Indicates whether it is writable, and also indicates whether the supervisor executor is writeable.
ECUTION>b18 is a bit indicating whether actual operation is possible.

Bits bo-b12 are the physical address of the memory (PHYS
ICAL ADR), and represents the upper address of the real memory where the page exists.

The 10-bit offset of address buffer 1 is added as a lower address and added to the real memory as a 23-bit system address (SYSTEM AB), that is, the physical address of the real memory.

The page valid pit (b23) and the above-mentioned protection data (b18 to b13) of 6 bits are added to the page hint checker 10. The page hit checker 10 determines these added bits and, for example, when the page is readable only by the user, it refers to the protection data and informs the CPU that the access to the memo 1 is an error (B[IS ERROR). Output to. Furthermore, it also refers to the page valid data and
Output to. for example.

It also outputs an error when the page is not valid.

The aforementioned address buffer 1. A virtual address in the vS is converted into a real memory address by the segment table 2, page table 3, and page bit checker 10, and as a result, real memory management is performed. That is, these circuits add the logical address given by the CPU (not shown) to the address buffer, and the physical address value is added to the system address bus connected to the real memory via the segment table and page table, and the address of the real memory is changed. Can be accessed. Naturally, when these accesses are inaccessible, the CPU is notified as a bus error.

The above operation is the memory access operation of the MMU section. On the other hand, the MMU section not only manages access to real memory, but also has to manage page-in, page-out, and the like. This is done by the LRU circuit 11 in FIG. 1, which performs page-in.

Search request (SERCHRQ) when page out
) search operation that determines the page of real memory for

Decrement of reference level by timer (
(lowering) and incrementing (raising) the reference level by memory access from the CPU.

First, the search request (SERCI RQ) will be explained. The search request is a signal added by the CPU as an I10 command when a page-in request occurs, and the LRU unit performs an operation to detect the page of the real address to be page-in.

When a search request (SERCHRQ) occurs, a high level 1 is applied to the search controller 12.

The search controller 12 uses this signal to set all the parallel data inputs DI of the LRU address counter 13 to high level 1, and also sets the load terminal to high level 1 via the ○R gate 14.

The LRU address counter 13 is a loadable 12-bit up/down counter, and when the = side output 120 of the search controller becomes high level 1, all bits of the counter become 1. The other output 121 of the search controller is a search request (SERCI).
When RQ) becomes high level 1, it becomes low level O, contrary to one output, and the U/75 terminal of the counter becomes low level O, so that the LRU address counter 13 starts counting down. (This down-count clock is a signal added from the timing generator 15). Each time the LRU address counter 13 counts down, the count value is output to the page table 3 via the address line 130, and the table is accessed in order from the top.

2 At this time, in the search request state, 2 bits (REFE-R[
ENCE A, B) b 21. 20 is connected to the reference comparator 6 via the LRU data bus LRUDB.
join. The reference comparator 6 is the minimum value OO of the reference value having three values, that is, the page table 3.
This circuit detects the minimum value of the reference values in the page. Each time the count value is sequentially decremented, the reference pick (REFERENCEA, B) of each page of the page table is added to the reference comparator 6.

The input data is input to the comparator circuit 6-1 as shown in FIG.
It is added to the reference data latch 6-3 and the NOR gate 6-2. Comparison circuit 6-1 compares the input reference with the value currently stored in reference data latch 6-3. Incidentally, at the time of starting execution of the search request, level 2 is stored in the reference date clutch 6-3 by a circuit not shown. In this comparison, input A=
(Ao, A+) is smaller than input B = (Bo, B+) (A
<B) That is, when the input reference data is smaller than the data stored in the reference data clutch 6-3, a high level 1 is output from the output 6-11. Since the output is added to the latch input of the reference day clutch 6-3, the input reference data is input to the reference day clutch 6-3.
Incorporate into 3.

On the other hand, the output of the comparison circuit 6-1 is also applied to the page address latch 18 in FIG. 1, and takes in the counter value of the output Do of the LRU address counter 13. That is, among the pages of the page table 3, the address value for the page having the minimum value in the search up to now among the reference data of the sequentially output pages is fetched. When the reference data is the minimum value OO, the comparison circuit 6-11 outputs 1, and the address value of the page corresponding to the page address launch 18 is launched, and the NOR gate 6-2 outputs 1, which is sent to the search controller via the OR gate 16. 12, resets it and sends the search end (SERCII OR
TIMEREND). Finally, if the reference data is not OO, page table 3
The address having the minimum value of the reference data within is taken into the page address launch 18, and furthermore, after the LRU address counter 13 becomes low level 0, the carry C resets the search controller 12 via the OR gate 16, and the search end ( SERC II O
RTIMEREND). Reference focus (RUFERENCE) by rooftop movement
The page table address with the smallest value of A, B) is detected. First, in order to read the page table address, the CPU launches the CPUREAD signal 180 into the page address latch 18, and the CPU data bus (
CPU DB) 181A reads the contents of the page address launch 18. Next, data in the same page is paged out to the auxiliary storage device by a circuit not shown, and data to be paged in is stored in the same page. Then, the page management data of the page paged into page table 3 is transferred to the CPU data bus (CP
UDB) 181B.

FIG. 4 shows the read/write control circuit 9 in the LRU circuit 11 shown in FIG. Search controller 12
．． FIG. 2 is a circuit configuration diagram showing the timer controller 17 in detail. The normal process and timer process will be explained below using FIGS. 1 and 4. The timer process forcibly lowers the reference value, that is, the level value, of each page currently existing on the real memory when a specific period of time has elapsed. When the timer process starts, the timing generator 15 adds 1 to the human power 150 of the AND gate 171 in the timing controller 17 . This signal indicates that the timer process has started executing. Flip-flop 1 of search controller 12
When no search request is input to the clock terminal CL of 2-1, the inverted output ζ is 1, and this output is applied to the AND gate 17-1 of the timer controller 17, so the output of the 2-AND gate 17-1 is Since it is high level 1, the timing generator 1
A pulse signal outputted from 5 through the one-shot/7-shot circuit 12-2 is applied to the load terminal of the LRU address counter 13 via the OR gate 14. However, in this case, there is no search request input, so flip-flop 1
Since the black terminal CL of 2-1 is at low level O and in a reset state, the non-inverted output Q is at low level O, and furthermore, the output Q is added to the data input D of the LRU address counter 13. Therefore, low level 0 (all 12 bits) is loaded into the LRU address counter 13. on the other hand.

As mentioned above, the inverted output ζ of the flip-flop 12-1 is at high level 1 at this time, so U/D = 1 and the amplifier count is specified. Increase by +1.

At this time, the output Do of the LRU address counter 13 accesses the page table 3, and the page table 3 contains reference data (REFERENCIIE A, B).

The changed bits and fixed bits are connected to the LRU data bus (LRU
DB). Since the AND gate 17-1 outputs 1 as described above, the flip-flop whose D input of the read/write control circuit 9 is at high level 11 is in the cent state, so the inverted output direction is low level O9 non-inverted output Q goes to high level 1, causing the normal process read modify write circuit 4 of FIG. 1 to be inactive and the timer process read modify write circuit 5 to be operational.

During operation, the timer process read modify write circuit 5 lowers the reference value, that is, the level value input from the LRU data bus (LRU DB) by 1 when the change bit is 1 (when the level is O, it is set to 0) and buffers it. The LRU data bus (LRU
DB). This output data is rewritten to the data inputted from the reference value of the page table 3 under the control of a circuit not shown.

Since the LRU address counter 13 is sequentially incremented, this operation is also performed simultaneously and sequentially until the carry C from the LRU address counter 13 is added to the reset of the read/write control circuit.

As a result, the reference values of all pages in the page table 3 become values with lower levels. In addition.

At the end of the timer process, the carry C of the LRU address counter 13 is output and sent to the CP via the OR circuit 16.
It is communicated to the CPU by joining the UI. As a result of this operation, the level of all pages that have passed a certain period of time is lowered.

The timer process lowers the level of each page at a specific time, whereas the normal process raises the level. The normal process raises the level when a page is used, and these two processes express information as to whether the usage frequency is low or high as a level value. After the timer process ends, the read/write control circuit 9 is normally in a reset state, and since the non-inverted output Q of the circuit 9 in FIG. 1 is added to the process read modify write circuit 4 and it is in an operating state. On the other hand, O is added to the timer process read modify write circuit 5 and it is in a non-operating state. At this time, when an address value is stored in the address buffer 1 from the address bus and a page of the real memory is accessed via the segment table 2, page table 3, etc., the normal process read modify write circuit 4 goes low.
Detects and inputs the changed bit 1 output to the RU data bus (LRU DB)
1? Decrease the value of EFERENCE A, B) by 1. Note that when the change bit is 0 or the level value is 2, no change is made. This means that the level of the page has been increased by +1.

As a result of the above operations, the level of a page decreases over time, but increases each time a used page is accessed, and as a result, this level value represents the frequency of use. In FIG. 4, the one-shot multi-hibrator 12-2 whose input 123 is connected to the output Q of the flip-flop 12-1 and whose output is connected to the OR gate 14 has an output Q of the flip-flop 12-1. LR only when changing from low level O to high level 1
This circuit generates a clock for loading data into the U address counter 13.

The reference data bit (REFERENC) mentioned above
EA, B) are two bits that represent three values.

Its meaning is whether the corresponding page is used at a high or low rate by the CPU.

Table 1 shows its usage status and level value.

The reference bits in Table 1 have three values from level O to level 2, and level O is the previous interval and current time within a specific time (interval time of the timer process executed by the timing generator 15 via the timer controller 17). If the page has not been accessed in the ink-pulse (before the process is being executed during the current timer process described later), or if it has been accessed once in the previous time and the timer process is executed on this page this time. , and the page is a page that is used very infrequently. Level 1 indicates that it was used in the previous interval but was not used before the current timer process execution for this page, or it was level O last time. Indicates the case where is executed once during this interval.

The page is a page that is used with average frequency. Level 2 is a page that has been used during the previous and current intervals, or has been used multiple times during the current interval, and is a page that is used very frequently.

As described above, these levels differ before and after the timer process is executed. For example, even if a page is used very frequently, the level drops to level 1 immediately after the timer process is executed, and becomes an average level. Even if the page has never been used, if the CPU accesses the page immediately after executing the timer process, the page becomes level 1, which is also an average level. That is, the above-mentioned level 1 includes both frequently used pages and also pages that are used very infrequently. In other words, pages that are likely to be used frequently and pages that are likely to be used less frequently are classified as level 1.
Toshi, l? 1. Pages that are used with high frequency are classified as level 2, and pages that are definitely used with low frequency are classified as level 0.
A page to be paged out can be reliably detected.

As described above, in the embodiments of the present invention, the timer process, search by search request, etc. are all explained as operating separately from the CPU clock, but this is not limited to this. For example, when the CPU is not accessing the memory, It is also possible to perform a cycle-stealing operation.

〔Effect of the invention〕

In the embodiment of the present invention, a level O page is detected in the above-mentioned search (if there is no level O page, a level 1 page is detected).
but it is very rare that there is no level 0)
Since the page is then paged out and paged in, it is possible to reliably detect a page that is used infrequently without detecting an uncertain page (it is unclear whether it is used infrequently or frequently). Therefore, according to the present invention, it is possible to prevent unnecessary page-out and page-in operations, and to obtain an LRU mechanism that shortens the execution time of a computer system.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a bit configuration diagram showing the bit configuration of a page table, and FIG. 3 is a detailed circuit diagram of a reference circuit. FIG. 4 is a detailed circuit diagram of the timer controller and search controller. 1...Address buffer, 2...Segment table, 3...Page table,
4... Normal process read modify write circuit, 5... Timer process read modify write circuit, 6... Reference comparator, 7, 8... Buffer circuit,
9... Read/write control circuit, 10
...Besighi 7 Tochienoka circuit, 11...
・LRU circuit. 12...Search controller, 13...L
RU address counter, 14.16...OR gate, 15...timing generator, 17...timer controller,
1st...Page Address Lunch. 6-1... Comparison circuit, 6-2... Noah gate, 6-3... Reference launch. 12-1...Flip-flop. 12-2...One shot multi-bye break 17-
1...ANDGATE patent Applicant: Casio Computer Co., Ltd.bno□b+s
baa-bu3b+2b. REFA REFB NT

Claims (6)

[Claims] (1) In a memory management unit that manages virtual memory on a page-by-page basis, there is a page table that stores levels corresponding to the frequency of use of multiple pages stored in real memory, and a page table that manages the table on a specific time basis. has an LRU means for changing the level, and the level is 3.
LRU mechanism characterized by being greater than or equal to the value. (2) The LRU mechanism according to claim 1, wherein the level is ternary. (3) The LRU mechanism according to claim 1, wherein the LRU means includes means for detecting the lowest level among the contents of the page table. (4) The LRU mechanism according to claim 1, wherein the LRU means lowers the level stored in the page table after a specific period of time has elapsed. (5) The LRU mechanism according to claim 1, wherein the LRU means raises the level of the page table contents corresponding to the page that has been paged in. (6) The LRU mechanism according to claim 1, wherein the LRU means includes a timer and a counter.