JPS61129910A - Digital frequency modulator - Google Patents

Abstract

PURPOSE:To decrease the 3rd order harmonic of a modulation signal by counting a carry signal of a counter starting counting of a clock signal when an input digital signal is loaded and using the carry signal as an address signal so as to a waveform data. CONSTITUTION:A digital signal latched by a latch circuit 2 is fed to the 1st counter 3 and loaded thereto by using its carry signal. The loaded digitial signal is decremented by the clock signal from a clock signal generator 4 and when the content of count is zero, the counter 3 generates a carry signal. The 2nd counter 5 counts 16 carry signals of the counter 3. On the other hand, a sinusoidal waveform data divided equally into 16 are stored in an ROM6 and the stored content is read sequentially by using the content of count of the counter 5 as an address signal. This signal is outputted as a frequency modulation signal via a D/A converter 7 and a filter 8.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to digital frequency modulators.

[Conventional technology]

Conventional digital frequency modulators have used counters and switched capacitor filters.

[Problem that the invention seeks to solve]

However, in such conventional digital frequency modulators, the cutoff frequency of the filter is fixed;
There are drawbacks such as if the third harmonic of the modulated signal remains in the frequency modulated signal for the low frequency modulated signal, and furthermore, if there is a drift in the initial value of the filter, correct modulation cannot be performed.

In view of this point, the present invention attempts to propose a digital frequency modulator that does not have such drawbacks.

[Means for solving problems]

A digital frequency modulator according to the invention comprises a first frequency modulator which is loaded with an input digital signal and which counts a clock signal.
A counter (3), a 20th counter (5) that counts the carry signal from the first counter (3), and the counting output of the second counter (5) are supplied as address signals and stored. The present invention is characterized in that it has a storage element (6) from which waveform data is read out, and a digital frequency modulated signal is superior to this storage element (6).

[Effect]

According to the present invention, by supplying the address signal from the second counter (51 to the memory element (6)),
The frequency quality vI4 signal of the input digital signal whose carrier wave is the stored waveform data from the storage element (6) is superior.

[Embodiment 1] An embodiment of the invention will be described below with reference to FIG. (2j is a latch circuit, to which one sample from the input terminal (1) is supplied with a serialized 8-bit digital signal (for example, a digital still image signal), and the carry from the second counter (5), which will be described later) The signal is latched one sample at a time.

The digital signal latched by the latch circuit (2) is
(3) and is loaded by its carry signal.

(4) is a clock signal generator. If the value of one sample of the digital signal loaded into the counter (3) is expressed in decimal notation and is, for example, 12, then the counter (3) receives a clock signal from the clock signal generator (crystal excavator) (4). is supplied and its loaded digital value 12
But 12.11.10. @・-・・, 2.1.0 and m
It is subtracted. When the count content of the counter (3) becomes 0, a carry signal is obtained from the counter (3) and is supplied to the second counter (for example, a binary counter) (5), and the counter (3) itself is loaded. Also supplied to the terminals. Thus, the same digital signal latched in the latch circuit (2) is again loaded into the counter (3) and its loaded digital value 12 becomes 12,11.

10, . . . , 2, 1, 0 are sequentially subtracted. When the count of the counter (3) becomes 0, a carry signal is obtained from this. Below, this is repeated and the counter (
5], when 16 carry signals from the counter (3) are supplied, the carry signal is obtained from the counter (5), is supplied to the latch circuit (2), and the next signal from the input terminal (1) is One sample of the digital signal is latched. The digital signal latched by this launch circuit (2) is supplied to a counter (3) and loaded by its carry signal. Thereafter, operations similar to those described above are repeated.

On the other hand, 8-bit digital values (waveform data) representing quantum numbers corresponding to the 16 equal divisions of the horizontal axis of one cycle of a sine wave are stored in addresses θ to 15 of ROM +61, as shown in Figure 2. It is assumed that

In this way, each time the carry signal from counter (3) is supplied to counter (5), the count contents of counter (5) will be 0 ('0OOOJ) and 1 (roooxJ).
, 2 (1'-0010j), ......, 15 (
"1111"), and the ROM (61
The contents of memory at addresses 0.1.2, . . . , 15 of (or a bandpass filter) (a simple filter using passive elements may be used) (8).

Thus, a smoothed sine wave signal as shown in FIG. 3 is output to the output terminal (9).

Therefore, if τ is the period of the clock signal from the clock generator (4), and N is the value (in decimal notation) of one sample of the digital signal loaded into the counter (3), then R
The period T of the 1 cycle sine wave obtained from OM+61 or the output terminal (9) is T=16Nτ.

Therefore, the frequency modulated signal obtained from the ROM (61) or the output terminal (9) is strictly a period modulated signal of the input digital signal supplied to the input terminal (1). When obtaining a frequency modulated signal in the strict sense from the terminal (9), the input digital signal must be antilogarithmically converted in advance, or digital and analog antilogarithmically converted to the output side of the ROM 161 or the filter (8), respectively. All you have to do is set up a container.

The analog frequency modulated signal obtained from the output terminal (9) can be easily transmitted over a telephone line.

Next, the present invention will be described in detail with reference to FIG. FIG. 4 shows a transmission system for transmitting still image signals using a telephone line. αD and (121 respectively indicate the transmitting side and the receiving side, and the CPU (central processing unit) (13,
Connected to this are a memory (capable of storing still image signals for two frames), a monitor receiver 4, and an external storage device (for example, a floppy disk drive device for storing still image signals) H.

On the transmitting side (11) (1) the magnetic field of an electronic still camera (not shown) that projects the subject image from the optical system onto the optical conversion element and records the imaging signal from the photoelectric conversion element on a magnetic disk; The reproduced signal from the disk is written to the memory α, read out and subjected to anti-logarithmic conversion, and then supplied to the digital frequency modulator (11) to which the present invention is applied for modulation.

Then, the analog frequency modulated signal is passed through an acoustic coupler (
The signal is supplied to the telephone (19) via the telephone (not shown), and the transmitted signal is transmitted to the telephone (a) on the receiving side α2 via the telephone line.The received signal from the telephone via the digital frequency demodulator to obtain the original still image digital signal and write it into the memory (141-).

Then, the signal read out from the memory is sent to the monitor receiver (
I5I, an external storage device, etc. for monitoring and storage.

〔Effect of the invention〕

According to the present invention described above, it is possible to obtain a frequency modulated signal in which the third harmonic component of the modulated signal is significantly reduced, and also to obtain a digital frequency modulator that has high accuracy and stability and is suitable for IC implementation. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams for explaining the same, and FIG. 4 is a still image signal transmission system suitable for applying the present invention. It is a block diagram. (1) is the input terminal, (2) is the latch circuit, (3) is the first
counter, (41 is a clock signal generator, (5) is a second counter, (6) is a storage element (ROM'), (7
1 is a D/A converter, and (8) is a filter.

Claims (1)

[Claims] When an input digital signal is loaded, a first counter that counts a clock signal, a second counter that counts a carry signal from the first counter, and a count output of the second counter are used as an address signal. 1. A digital frequency modulator comprising: a storage element from which waveform data is supplied and stored therein; and a digital frequency modulated signal is obtained from the storage element.