JPS61126689A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease the number of the word decoder of a cell array divided memory by controlling a selecting gate with a block selecting line and a word selecting line, and selecting a word line of a blocked memory cell. CONSTITUTION:Respective word lines WL0-WL3 of memory cell array blocks CA0-CA3, which are plurally divided in the word line direction, are selected through selecting gates GR0-GL3 controlled by respective word decoders WDR and WDL and block selecting line R0-L3. Consequently, it is not necessary to install a word decoder by the blocks Ca0-C3, the number of word decoders can be decreased to two and the integrating of the blocked large capacity memory can be further improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device in which a cell array is divided into a plurality of blocks, and particularly to a word line selection circuit thereof.

[Conventional technology]

In large-capacity memories, it has been considered to divide the cell array into multiple blocks from the viewpoint of high-speed operation and low power consumption. FIG. 4 shows an example in which the cell array is divided into four in the word line direction. Since each cell array is operated independently, for example, in the case of a DRAM (dynamic random access memory), the number of bit lines to be precharged and discharged during access is reduced to 1/N (N is the number of divisions), reducing power consumption. Further, by shortening the word line length, speed delays caused by the resistance of the word line itself can be improved, and furthermore, since the capacitance of the word line is reduced, high-speed operation is possible.

In this figure, CB is a counter and buffer (address ao) that generates the refresh address RA.

al, ...and its inverse ao, a+, ...
.), AB is an address buffer that receives an external address and generates a normal access address AA (also generates an address bit and its inverted bit).

DRAM requires refreshing, but if the cell array is divided into multiple blocks and each block can operate independently,
It is possible to perform normal access in one cell array block and refresh in other blocks at the same time.If you control the refresh to be performed in parallel with normal access so that no collision occurs, normal access can be performed because refresh is in progress. You'll have fewer people waiting, and you'll be able to reduce your busy rate! [Problems to be Solved by the Invention] However, in order to operate each cell array block independently, N word decoders are required for each cell array block in the above example, and an address line runs through the word decoder, resulting in a large Since several output transistors are used and space is required, the area occupied by the word decoder increases considerably as the number increases.

The present invention aims to reduce the required number of word decoders and further improve the degree of integration of block-based large-capacity memories.

[Means for solving problems]

The present invention provides a semiconductor memory device in which a memory cell array is divided into a plurality of blocks in the word line direction, in which a plurality of selection gates are arranged on the word lines of each block, and a plurality of mutually independent word decoder output lines and block selection lines are provided. The invention is characterized in that the word line can be selected from a plurality of word decoders by controlling the gate.

〔Example〕

Referring to the drawings, FIG. 1 shows an example in which the cell array is divided into four, and CAO to CA3 are each of the blocks. WLO to WL3 are word lines of each cell array block. In the figure, only one is shown (the other one is shown by a dotted line), but of course there are many in reality. These word lines WLO~W
L3 is one word line before cell array division, and therefore has the property of being selected by the same word address. In order to divide the cell array and select each cell play block independently, in FIG. 4, each cell array block is provided with a word decoder, the same address signal is given to them, and a select signal is used to specify which block should operate. (This is the upper two bits of the column address in this example), but in FIG. 1, word decoders are only placed on both sides of the cell array block groups CAO to CA3. WDR is a right word decoder, and WDL is a left word decoder. In this figure, WDR and WDL indicate a part of the word decoder that selects one word line, and therefore WDR.

It is assumed that there are as many WDLs as the number of word lines (indicated by dotted lines), but for convenience of explanation, these will also represent the entire word decoder. Word decoder WDR.

Output lines WLR and WLL for selecting word lines extend from WDL, and each word line WLO-WL3 has word line selection gates GRO and GLO, GRl and GLl, . . . on both sides.
... will be established. Lines RO to R3, LO- running in a direction perpendicular to the word line, ie, in the direction of the bit line (not shown)
L3 is a selection line for blocks CAO to CA3; the former is for selection from the right side, and the latter is for selection from the left side. Therefore, the selection gates (anto gates)) GRO to GR3 are the output lines W
The potentials of LR and any one of RO to R3 are inputted, and the selection gates GLO to GL3 receive the potentials of output lines WLL and any one of LO to L3. Although not shown, each block CAO-CA3 is provided with a column decoder that selects the bit line of the block.

In this device, a word line is selected by the right word decoder WDR, specifically, the output line WLR is set to H (high) level, and one of the lines RO to R3 is selected.For example, when R1 is set to H level, the AND gate GRI The output of WLI becomes H level, and word line WLI is selected. The other word lines WLO, WL2, and WL3 are AND gated GRO because RO, R2, and R3 are not selected, that is, they are at L (low) level.

The outputs of GR2 and GR3 are at L level and are not selected. Each block CAO-CA3 has a large number of bit lines running in a direction perpendicular to the word line, and these bit lines are selected by the upper two bits of the column address.
If so, the selection signal on line RO-R3 is the upper two bits.

The operation of this memory (DRAM) is well known; when a word line is selected, the corresponding memory cell group is connected to the bit line group, changes the bit line potential according to the stored data, and this is expanded by the sense amplifier group. , the bit line selected by the column decoder is connected to the data bus,
The bit line potential, that is, the storage data of the selected cell is taken out to the outside.

This is a read operation, but in the case of a write, the data flow is reversed. A word line is selected by the left word decoder WDL, that is, WLL is set to H, and LO to L3 are selected.
For example, if you select LO, the AND gate GL
The output of O becomes H, and word line WLO is selected. L
The selection signal of O-L3 is also the same as that of RO-R3.

In this way, in this device, a memory cell block is divided into one word decoder WDR or WDL and block selection line RO-R.
3 or LO to L3, and the number of word decoders can be significantly reduced compared to the case where each block is provided with a word decoder.

Also, if provided on both sides, when one word decoder is selecting memory cells in a certain block, the other word decoder can select memory cells in the other block, and if this is used for refreshing, the busy rate can be reduced.

Right word decoder WDR and left word decoder WDL
are used for reading and writing, and one for reading and the other for reading and writing.
The other may be dedicated for writing, or one may be used for normal access (read/write) and the other for refresh. In other words, this two-word decoder system is extremely flexible and can be used in various ways.

If cell array blocks are selected independently by two word decoders, a collision may occur, that is, the same block may be selected at the same time, and this must be avoided by providing a priority control circuit.

As a priority control method, it is conceivable to simply fix it so that the right access system has priority.

One side of the word decoder is used for normal access, and the other is used for refreshing. Refreshing must be performed at a predetermined period to prevent loss of the memory contents of the memory cells. If the period is set to the maximum allowable limit, collision avoidance is normally not possible. This may be done by making access standby, but if there is enough time in the cycle, refresh can be made to wait.

Since refreshing can be done in order from the end, a simple method can be used in which the access address is generated using a circular shift register that stores only one H data and the rest L data, and a predetermined number of bits can be generated. There is no need to use a complicated word decoder consisting of an address line, an address buffer for creating an inverted bit, a NOR gate, etc.

For selection games) GRO, GLO, etc., two transistors are sufficient. FIG. 2 shows the selection gate of the cell array block CAL, and shows the selection gate of the field effect transistor QL.
, Q2 also connects the gate GRI to the field effect transistor Q3.
．． Q4 constitutes gate GLI. Transistor Q2.
Q4 is for bootstrap. That is, transistor Q
2. The gate of Q4 is connected to potential VCC. Therefore, R1 is raised to H (Vc
c) and the capacitance of the gate node of transistor Q1 is charged to Vcc, and when WLR is turned on in this state, Ql
The gate of becomes equal to or higher than Vcc, Ql is completely turned on, and the potential Vcc of WLR can be directly applied to the word line wL1. The same applies to transistor Q3.

The devices shown in FIGS. 1 and 2 require two output lines WLR and WLL for each word line. The word line of a DRAM also serves as the gate of the transistor in a one-transistor, one-capacitor type memory cell, so it is generally made of polycrystalline silicon, and the output lines WLR, WLL are made of aluminum and have different layers, but the output lines WLR, The WLLs are on the same layer, and there is a risk that the wiring spacing will be quite close. FIG. 4 improves this point, and output lines WLR and WLL each make it possible to select any one of the two word lines WLI and WLI'. In this way, since there are two output lines for two word lines, there is one output line per word line, and the number of output lines can be halved.

To explain the operation of FIG. 3, now when WLR and R1 are set to H, the output of AND gate GR1 becomes H, and word line WLI is selected. When WLR and R1' are set to H, the output of AND gate GR1' becomes H, and the word line WLI'
is selected. The operation of the left side selection circuit is also similar. The selection signal for the selection lines R1 and R1'L1 and LL' is one bit of the word line address signal, and the least significant bit is removed (and the word line address signal is added to the word decoder), and the least significant bit is used to select R1, R1', When either LL or LL' is selected, WLI'' is the next word line (WL2) after WLI.
become.

In the embodiment, an example is given in which the cell array is divided into four, but of course it may be divided into a larger number, such as eight, and in that case, it is sufficient to provide only two word decoders in total, one on the left and one on the right. Of course, the word decoder may be arranged only on the right or left side, that is, closer to one side, and the gates GRO, GLO, etc. may also be arranged closer to one end of the word line. In addition, in FIG. 3, one output line, for example WLR, and two word lines WLI, WLI'
However, if the selection lines R1 and R1' are made four, four word lines can be selected, and generally, n word lines can be selected by using n selection lines. Further, although DRAM is taken as an example, it may also be SRAM (static RAM).

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the number of word decoders in a cell array divided memory, and it is also possible to use the memory in a variety of ways, which is extremely effective.

[Brief explanation of the drawing]

1 to 3 are explanatory diagrams showing embodiments of the present invention, and FIG. 4 is an explanatory block diagram of a memory having a divided cell array. In the drawing, CAO to CA3 are cell array blocks, WLO
-WL3 is a word line, GRO...GL3 is a selection gate, WDR, WDL are word decoders, RO...
...L3 is a block selection line.

Claims (3)

[Claims] (1) The memory cell array is divided into multiple blocks in the word line direction, multiple selection gates are provided on the word lines of each block, and multiple word decoders and block selection lines that operate independently are provided. A semiconductor memory device characterized in that one word line can be selected from a plurality of word decoders by controlling the gate by an output line of a decoder and a block selection line. (2) The word decoder is arranged on one side and the other side of the cell array block group, and the output line extends across the cell array block in parallel with the word line. The semiconductor storage device described above. (3) A plurality of pairs of block selection lines are provided in each cell array block, and the selection gates are opened and closed by the selection lines so that one output line of the word decoder can select a plurality of word lines. A semiconductor memory device according to claim 2.