JPS61125012A - Epitaxial wafer - Google Patents

Epitaxial wafer

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Publication number
JPS61125012A
JPS61125012A JP24650484A JP24650484A JPS61125012A JP S61125012 A JPS61125012 A JP S61125012A JP 24650484 A JP24650484 A JP 24650484A JP 24650484 A JP24650484 A JP 24650484A JP S61125012 A JPS61125012 A JP S61125012A
Authority
JP
Japan
Prior art keywords
wafer
epitaxial layer
gas
epitaxial
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24650484A
Other languages
Japanese (ja)
Inventor
Yoshiaki Matsushita
松下　嘉明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24650484A priority Critical patent/JPS61125012A/en
Publication of JPS61125012A publication Critical patent/JPS61125012A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

PURPOSE:To make a wafer highly resistant to thermal strain and thereby to prevent it substantially from the occurrence of slip, by a method wherein an epitaxial layer having two or more regions different in the concentration of nitrogen is provided on a substrate wafer. CONSTITUTION:A silicon wafer 10 is set on a susceptor 2 in a chamber 1, and in the state in which the wafer is heated by a high-frequency coil 3, H2 gas and HCl gas are made to flow into the chamber 1 through an introduction pipe 4 so as to etch the surface of the wafer 10 for purification. Next, the supply of the HCl gas is stopped and temperature is lowered. Thereafter H2 carrier gas is supplied, and SiH2Cl2 gas and B2H6 gas are made to flow into the chamber 1 so as to make an epitaxial layer grow. On the occasion, N2 gas having a concentration of 1ppm-1% is supplied to introduce N2 into the epitaxial layer, then the inflow of nitrogen gas is stopped, and the epitaxial layer is made to grow further continuously. By setting the concentration of nitrogen in a region near an interface of the epitaxial layer with the wafer at 1X10<15>cm<-3>-1X10<16>cm<-3> in this way, a slip due to thermal strain can be prevented from affecting the whole of the layer.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、エピタキシャルウェハに関し、特にＬＳＩ用
の大口径シリコン基板に適したエピタキシャルウェハに
係わる。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an epitaxial wafer, and particularly to an epitaxial wafer suitable for a large-diameter silicon substrate for LSI.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来、バイポーラ用素子として使用されているシリコン
エビタシャルウェハはウェハ表面に埋込み拡散等を還択
的に施した後、気相成長用のエピタキシャル炉中で水素
をキャリアとして　ＳｉＣλ噂の水素還元又はＳｉｔ−
ｈｃｇ２の熱分解によりシリコンをウェハ上にエピタキ
シャル成長させたものが用いられている。また、ＭＯ８
素子用基板として使用されるエピタキシャルウェハは、
シリコンウェハ上にＳｉＣＭ＋野水素還元又は５ｉＨ２
Ｃｆｆｉｚ等の熱分解によりシリコンをエピタキシャル
成長させたものが用いられている。しかしながら、かか
るエピタキシャルウェハは、そのエピタキシセル層を形
成する際に、積層欠陥や微少欠陥、転位等が導入され、
該エピタキシャル層の高品質化を阻害する。Conventionally, the silicon epitaxial wafer used as a bipolar device is subjected to reductive embedding and diffusion on the wafer surface, and then undergoes SiCλ rumored hydrogen reduction or SiC using hydrogen as a carrier in an epitaxial furnace for vapor phase growth. −
Silicon is epitaxially grown on a wafer by thermal decomposition of hcg2. Also, MO8
Epitaxial wafers used as device substrates are
SiCM + wild hydrogen reduction or 5iH2 on silicon wafer
Silicon epitaxially grown by thermal decomposition such as Cffiz is used. However, in such epitaxial wafers, stacking faults, micro defects, dislocations, etc. are introduced when forming the epitaxial cell layer.
This impedes improvement in the quality of the epitaxial layer.

このようなことから、裏面に損備を与えたエクストリン
シックゲッタリングウェハ（ＥＧウェハ）や内部に微少
欠陥を発生させたイントリンシックゲッタリングウェハ
（ＩＧウェハ）を使用し、その基板ウェハ上にエピタキ
シャル成長を行ない、積層欠陥や微少欠陥の発生を防止
している。しかしながら、エピタキシャル成長工程では
、１０分間程度で１１５ｃｍ程度まで昇温し、ＳｉＱ＃
４の水素還元又はＳ　ｉ　８２　Ｃ１，２の熱分解を行
なってシリコンをエピタキシャル成長し、その後１５〜
２０分間程度で室温まで冷却している。この際、基板ウ
ェハとエピタキシャル層との界面にスリップが導入され
、更に熱歪みによりスリップがエピタキシャル層全体に
波、及する。エピタキシャル層全体にスリップが発生す
ると、該エピタキシャル層にパターンを形成した場合、
段切れが生じたり、素子を形成した場合、ジャンクショ
ンリーク等を起こす。こうしたスリップの発生はＥＧウ
ェハやＩＧウェハを用いても防止できない。特に、直径
が１２５ｍ以上の大口径ウェハの場合には前記スリップ
発生が顕著となり、７ウエハの端から１０＃１以上の領
域までスリップが発生し、全体の２０％以上の領域での
素子形成が不可能となることもある。For this reason, we use extrinsic gettering wafers (EG wafers) with defects on the back side or intrinsic gettering wafers (IG wafers) with micro defects inside, and perform epitaxial growth on the substrate wafer. This prevents stacking faults and micro-defects from occurring. However, in the epitaxial growth process, the temperature is raised to about 115 cm in about 10 minutes, and SiQ#
Silicon is epitaxially grown by hydrogen reduction of 4 or thermal decomposition of Si 82 C1,2, and then 15~
It is cooled to room temperature in about 20 minutes. At this time, slip is introduced at the interface between the substrate wafer and the epitaxial layer, and the slip spreads throughout the epitaxial layer due to thermal strain. If slip occurs in the entire epitaxial layer, when a pattern is formed on the epitaxial layer,
If a step break occurs or an element is formed, junction leakage etc. will occur. The occurrence of such slips cannot be prevented even by using EG wafers or IG wafers. In particular, in the case of large-diameter wafers with a diameter of 125 m or more, the above-mentioned slipping becomes noticeable, and slipping occurs from the edge of 7 wafers to an area of 10#1 or more, and device formation is impossible in an area of 20% or more of the total wafer. Sometimes it is impossible.

また、０ＭＯ８のラッチアップ防止に対しては、低抵抗
のウェハ上に高抵抗のエピタキシャル層を成長させたエ
ピタキシャルウェハ（例えばｐ“型ウェハ上にｐ型エピ
タキシャル層を成長させたエピタキシャルウェハ）が有
効である。しかしながら、かかるエピタキシャルウェハ
では、基板ウェハとエピタキシャル層の界面でポテンシ
ャル障壁が生じる。例えば、第３図に示すようにｐ＋型
ウェハとｐ型エピタキシャル層との接合ではポテンシャ
ル障壁が大きいため、α線等の入射によりエピタキシャ
ル層に電子が偶発的に発生した場合、該電子は前記接合
でエピタキシャル層側に追返されウェハ側への拡散が阻
止される。従って、α線の入射によるソフトエラーに対
しては単なるＩＧウェハより悪い結果を示す欠点があっ
た。Additionally, epitaxial wafers in which a high-resistance epitaxial layer is grown on a low-resistance wafer (e.g., an epitaxial wafer in which a p-type epitaxial layer is grown on a p-type wafer) are effective for preventing 0MO8 latch-up. However, in such an epitaxial wafer, a potential barrier occurs at the interface between the substrate wafer and the epitaxial layer.For example, as shown in FIG. 3, the potential barrier is large at the junction between the p + type wafer and the p type epitaxial layer. If electrons are accidentally generated in the epitaxial layer due to the incidence of alpha rays, etc., the electrons are repelled to the epitaxial layer side by the junction and prevented from diffusing to the wafer side.Therefore, soft errors due to the incidence of alpha rays are prevented. However, the wafer had the drawback of showing worse results than a simple IG wafer.

〔発明の目的〕[Purpose of the invention]

本発明は、大口径化した場合でも熱歪みに強く、スリッ
プの発生し難いと共に、ＭＯ８ＬＳＩに適用した場合に
ソフトエラーに対して強いエピタキシャルウェハを提供
しようとするものである。The present invention aims to provide an epitaxial wafer that is resistant to thermal distortion even when the diameter is increased, is less prone to slip, and is resistant to soft errors when applied to MO8LSI.

〔発明の概要〕[Summary of the invention]

本発明は、基板ウェハ上に窒素濃度の異なる少なくとも
２つ以上の領域を有するエピタキシャル層を設けてなる
エピタキシャルウェハである。かかる本発明によれば、
既述の如く大口径化した場合でも熱歪みに強く、スリッ
プの発生し難いと共に、ＭＯ８ＬＳＩに適用した場合に
ソフトエラーに対して強いエピタキシャルウェハを得る
ことができる。エピタキシャル層中への窒素の導入は、
例えばエピタキシャル成長工程中のキャリアにＮ２ガス
又はＮＨ３ガスを微量混入させる方法が採用し得る。The present invention is an epitaxial wafer in which an epitaxial layer having at least two regions having different nitrogen concentrations is provided on a substrate wafer. According to this invention,
As described above, even when the diameter is increased, it is possible to obtain an epitaxial wafer that is resistant to thermal distortion, hardly causes slip, and is resistant to soft errors when applied to MO8LSI. The introduction of nitrogen into the epitaxial layer is
For example, a method may be adopted in which a trace amount of N2 gas or NH3 gas is mixed into the carrier during the epitaxial growth process.

上記エピタキシャル層としては、例えば表面付近の領域
の窒素濃度が基板ウェハとの界面付近の領域の濃度より
恢いもの等を挙げることができる。Examples of the epitaxial layer include those in which the nitrogen concentration in the region near the surface is lower than the concentration in the region near the interface with the substrate wafer.

かかる窒素濃度の高い領域の濃度はｌＸ１０１５ｃｍ−
３〜１　Ｘ　１０１６ｃｍ−３の範囲に、窒素濃度の低
い領域の濃度はｌＸ１０ｔ’ｅＩＮ”３以下にすること
が好ましい。このように窒素濃度の高い領域の濃度を限
定した理由は、その濃度をｌＸ１０１５０“３未満にす
ると、エピタキシャル層へのスリップの発生抑制作用を
充分に発揮できず、かといってその濃度がｌＸｌ０１６
ｃＩＲ”を越えると、然歪みによるスリップの発生を抑
制できるものの、窒化硅素がエピタキシャル層に析出し
、その箇所から積層欠陥や転位が発生し、エピタキシャ
ル層の結晶性を著しく損う。また、素子領域として利用
される窒素濃度の低い領域の上限濃度を限定した理由は
、その濃度がｌＸｌ０”Ｃ１３を越えると、窒素のドナ
ー化のために抵抗値の変動を生じたり、ディープトラッ
プによりライフタイムが短くなったりする恐れがある。The concentration of such a region with high nitrogen concentration is 1×1015 cm−
3 to 1 x 1016 cm-3, and the concentration in the region with low nitrogen concentration is preferably 1 x 10t'eIN''3 or less.The reason for limiting the concentration in the region with high nitrogen concentration in this way is to When the concentration is less than 1X10150"3, the effect of suppressing the occurrence of slip in the epitaxial layer cannot be sufficiently exerted.
cIR'', although it is possible to suppress the occurrence of slip due to natural strain, silicon nitride precipitates in the epitaxial layer, and stacking faults and dislocations occur from that location, significantly impairing the crystallinity of the epitaxial layer. The reason for limiting the upper limit concentration of the region with low nitrogen concentration used as the region is that if the concentration exceeds lXl0''C13, the resistance value will fluctuate due to nitrogen becoming a donor, and the lifetime will be shortened due to deep traps. There is a possibility that it may become shorter.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を第１図を参照して説明する。 Embodiments of the present invention will be described below with reference to FIG.

第１図は本実施例に使用するエピタキシャル成長炉の概
略図である。図中の１チヤンバであり、該チャンバ１内
にはサセプタ２が配設されている。FIG. 1 is a schematic diagram of an epitaxial growth furnace used in this example. This is one chamber in the figure, and a susceptor 2 is disposed within the chamber 1.

このサセプタ２の下面付近には高周波コイル３が配設さ
れている。また、前記サセプタ２の中心には、チャンバ
１外から延出されたガス導入管４が貫通して設けられて
いる。このガス導入管４には、Ｈ２ボンベ５、Ｎ２ボン
ベ６．５ｉＨ２Ｃλ２ボンベ７、Ｂ２　Ｈ６ボンベ８及
びＨ（ｌボンベ９が夫々連結されている。A high frequency coil 3 is disposed near the bottom surface of the susceptor 2. Further, a gas introduction pipe 4 extending from outside the chamber 1 is provided through the center of the susceptor 2 . A H2 cylinder 5, a N2 cylinder 6.5iH2Cλ2 cylinder 7, a B2H6 cylinder 8, and an H(l cylinder 9) are connected to the gas introduction pipe 4, respectively.

次に、前述した第１図図示のエピタキシャル成長炉を用
いてエピタキシャルウェハの製造方法を説明する。Next, a method for manufacturing an epitaxial wafer using the epitaxial growth furnace shown in FIG. 1 described above will be explained.

まず、チャンバ１内のサセプタ２上に直径１５０ｍ、抵
抗０．０８Ω・αのｐ型（ボロンドープ）シリコンウェ
ハ１０をセットした。つづいて、高周波コイル３により
１１８０℃まで加熱した状態でＨ２ボンベ５及びＨ（ｌ
ボンベ９から夫々ＨＣｆｆｉ１１度が３％となるように
Ｎ２ガスとＨＣλＣβガス入管４からチャンバ１内に約
２分間流して、ウェハ１０表面をエツチングして清浄化
した。First, a p-type (boron-doped) silicon wafer 10 having a diameter of 150 m and a resistance of 0.08 Ω·α was set on the susceptor 2 in the chamber 1 . Next, the H2 cylinder 5 and H(l
The surface of the wafer 10 was etched and cleaned by flowing N2 gas and HCλCβ gas from the cylinder 9 into the chamber 1 from the inlet tube 4 for about 2 minutes so that the HCffi11 degrees was 3%.

ひきつづき、ＨＣβガスの供給を停止し、温度を１１５
０℃まで下げた後、Ｈ２をキャリアが又としてＳ　ｉ　
Ｈ２Ｃλ２ボンベ７及び８２　Ｈ６ボンベ８から夫々５
ｉＨ２Ｃｊ２２ガスと８２１−１ｓガスを導入管４から
チャンバ１内に流してウェハ１０上に厚さ３μｍのエピ
タキシャル層を成長した。この際、Ｎ２ボンベ６からＮ
２ガスを１００ｍ〜１％の濃度でＮ２ガスと共に、チャ
ンバ１内に流してエピタキシャル層中にＮ２を導入した
。次いで、窒素ガスの流入を停止し、更に前記エピタキ
シャル層上に厚さ４μｍのエピタキシャル層を連続的に
成長して総厚さ７μｍのエピタキシャル層を有するエピ
タキシャルウェハを製造した。Continuing, the supply of HCβ gas was stopped and the temperature was lowered to 115.
After cooling down to 0°C, Si
H2Cλ2 cylinder 7 and 82 5 each from H6 cylinder 8
An epitaxial layer having a thickness of 3 μm was grown on the wafer 10 by flowing iH2Cj22 gas and 821-1s gas into the chamber 1 from the introduction pipe 4. At this time, from N2 cylinder 6
2 gas was flowed into the chamber 1 together with N2 gas at a concentration of 100 m to 1% to introduce N2 into the epitaxial layer. Next, the flow of nitrogen gas was stopped, and an epitaxial layer with a thickness of 4 μm was continuously grown on the epitaxial layer to produce an epitaxial wafer having an epitaxial layer with a total thickness of 7 μm.

しかして、得られたエピタキシャルウェハについて、そ
のエピタキシャル層中の窒素の深さ方向分布をプロトン
照射による放射化分析法（Ｉ　Ａ　Ｎ（ｐ、α）ＩＩＣ
）により測定し。その結果、表面から４μｍのエピタキ
シャル層領域の濃度は検出限界（ＩＸｌｏ”ａＲ’）以
下であり、該４μｍの深さからウェハ界面までのエピタ
キシャル層領域の濃度は７Ｘ　１０”　ｒｓ”であった
。このようにエピタキシャル層のウェハとの界面付近領
域の窒素濃度を７×１０１５ｃＩＲ”にすることによっ
て、該界面付近のエピタキシャル層領域へのスリップの
導入を抑制でき、ひいては熱歪みによりスリップがエピ
タキシャル層全体に波及するのを防止できる。事実、ウ
ェハとの界面付近領域のＮ２８度が零、Ｎ２濃度が０．
６Ｘ　１０”　’　ｃＩＲ”、ｌＸｌ０”　ｃｍ”、２
．５”　ａｓ”、　５×１０”　ａｎ”、７×１０１５
　ａｓ”、９×１０１５ｔｙｔｔ”　、２　Ｑｘ　１０
”　’　ａｎ”及び４０ｘ１０ｘｓ国°３のエピタキシ
ャル層を有するウェハについて、それらエピタキシャル
層のウェハ界面付近の［におけるスリップ最大長さを調
べた。その結果、第２図に示す特性図を得た。なお、Ｎ
２１１度の測定は前述したプロトン照射による放射化分
析法（１’　Ｎ　＜１）、α）１１Ｃ）により行なった
。この第２図より、ウェハ界面領域にＮ２が　１×１０
１５ｃｍ−３以上導入されたエピタキシャル層は、発生
するスリップの大きさが数−で、明らかにＮ２の導入に
よりスリップの発生が抑制されることがわかる。また、
Ｎ２の濃度が１ｘｉｏｚα″３を越えても、スリップの
発生抑制作用を示すものの、エピタキシャル層中に窒化
硅素の析出が現われ、その箇所から積層欠陥や転位が発
生して無欠陥のエピタキシャル層を成長できなかった。For the obtained epitaxial wafer, the depth distribution of nitrogen in the epitaxial layer was measured using an activation analysis method (I A N (p, α) IIC) using proton irradiation.
). As a result, the concentration in the epitaxial layer region 4 μm from the surface was below the detection limit (IXlo"aR'), and the concentration in the epitaxial layer region from the 4 μm depth to the wafer interface was 7×10"rs". In this way, by setting the nitrogen concentration in the region near the interface between the epitaxial layer and the wafer to 7×1015 cIR, it is possible to suppress the introduction of slip into the epitaxial layer region near the interface. This can prevent it from spreading. In fact, the N28 degree and N2 concentration near the interface with the wafer are 0.
6X 10"'cIR", lXl0"cm", 2
．． 5”as”, 5×10”an”, 7×1015
as”, 9×1015tytt”, 2 Qx 10
The maximum slip length of the epitaxial layers near the wafer interface was investigated for wafers having an epitaxial layer of 40x10xs and 3°C. As a result, a characteristic diagram shown in FIG. 2 was obtained. In addition, N
The measurement at 211 degrees was carried out by the activation analysis method using proton irradiation (1' N <1), α) 11C) described above. From this figure 2, it can be seen that the amount of N2 in the wafer interface area is 1×10
In the epitaxial layer in which 15 cm<-3> or more was introduced, the size of the slip generated was several -, which clearly shows that the introduction of N2 suppresses the occurrence of slip. Also,
Even if the concentration of N2 exceeds 1xiozα''3, although it shows the effect of suppressing the occurrence of slip, silicon nitride precipitation appears in the epitaxial layer, and stacking faults and dislocations occur from that location, making it difficult to grow a defect-free epitaxial layer. could not.

従って、ウェハ界面のエピタキシャル層領域の窒素濃度
を例えば７Ｘ１０１Ｓα゛３として、該界面付近領域で
のスリップの発生抑制、ひいてはエピタキシャル層全体
へのスリップの波及を防止すると共に、エピタキシャル
層の表面付近領域の窒素濃度が１ｘｌＯ１’α゛３以下
と低濃度にすることによって、該ウェハからＭＯ８ＬＳ
［を製造した場合、ライフタイムが短縮されることなく
、ジャンクションリーク等を改善できる。Therefore, by setting the nitrogen concentration in the epitaxial layer region at the wafer interface to, for example, 7X101Sα゛3, it is possible to suppress the occurrence of slip in the region near the interface and prevent the spread of slip to the entire epitaxial layer. By keeping the nitrogen concentration as low as 1xlO1'α゛3 or less, MO8LS can be extracted from the wafer.
[If manufactured, junction leaks, etc. can be improved without shortening the lifetime.

また、本発明のエピタキシャルウェハは、低抵抗のｐ＋
型シリコンウェハの主面上に３μｍの厚さの窒素を高濃
度含む高抵抗のシリコン層が設けられ、そのシリコン層
上に厚さ４μｍの窒素濃度の極めて低い高抵抗のシリコ
ン層を成長した構造になっている。従って、シリコン層
中の窒素は深い単位を形成するため、偶発的に発生した
少数キャリアの再結合中心になる。また、エビタキシャ
ル層中の窒素濃度の高いウェハ界面付近のシリコン層と
表面付近側の窒素濃度の低いシリコンとの境界には、ポ
テンシャル障壁が存在しないため、ソフトエラーを効果
的に回避できる。事実、本実施例で製造されたエピタキ
シャルウェハの窒素濃度の低い高抵抗シリコン層に２５
６にビットダイナミックＲＡＭを製作し、ソフトエラー
を評価したところ、通常のｐ／ｐ＋のエピタキシャルウ
ェハに対して約２〜３倍の耐ソフトエラー性を有するこ
とが確認された。Furthermore, the epitaxial wafer of the present invention has a low resistance p+
A structure in which a 3-μm-thick high-resistance silicon layer containing a high concentration of nitrogen is provided on the main surface of a mold silicon wafer, and a 4-μm-thick high-resistance silicon layer with an extremely low nitrogen concentration is grown on the silicon layer. It has become. Therefore, nitrogen in the silicon layer forms deep units and becomes a recombination center for incidentally generated minority carriers. Further, since there is no potential barrier at the boundary between the silicon layer near the wafer interface where the nitrogen concentration is high in the epitaxial layer and the silicon layer near the surface where the nitrogen concentration is low, soft errors can be effectively avoided. In fact, 25% of the high resistance silicon layer with low nitrogen concentration of the epitaxial wafer manufactured in this example
When a bit dynamic RAM was manufactured in No. 6 and soft error evaluation was performed, it was confirmed that the soft error resistance was about 2 to 3 times that of a normal p/p+ epitaxial wafer.

なお、上記実施例ではシリコン源として５ｉ８２　Ｇ（
１２を使用したが、ＳｉＣｇ＋、　５１１−１ｃλａ、
５ｉ）（＋、５ｉ２ｆ−１ｓを用いても同様にエピタキ
シャル成長が可能であり、それに窒素を導入することに
より、スリップの発生を抑制したエピタキシャル層を形
成できる。特に、３ｉＨ４ヤＳ　ｉ　２　Ｈｓ　Ｔ：ハ
、１０００℃以下でエピタキシャル成長が可能で、窒素
導入により直径１５０ｔｔｙｒ以上の大口径のウェハで
も、その上にスリップの全くないエピタキシャル層を形
成できる。In the above example, 5i82G (
12 was used, but SiCg+, 511-1cλa,
5i) (+, 5i2f-1s can be similarly used for epitaxial growth, and by introducing nitrogen into it, an epitaxial layer that suppresses the occurrence of slip can be formed. In particular, 3iH4 and S i 2 Hs T: C. Epitaxial growth is possible at temperatures below 1000° C., and by introducing nitrogen, an epitaxial layer with no slip can be formed on a wafer with a large diameter of 150 ttyr or more.

上記実施例では、窒素源としてＮ２ガスを使用したが、
この代わりにＮＨ３を用いても同様なエピタキシャル層
を形成できる。In the above example, N2 gas was used as the nitrogen source, but
A similar epitaxial layer can be formed by using NH3 instead.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く、本究明によれば大口径化した場合で
も熱歪みに強く、スリップの発生が少なく、エピタキシ
ャル層に配線形成時の段切れや、素子を形成した場合に
よるジャンクションリータを抑制できると共に、ＭＯ３
ＬＳ　Ｉに適用した場合にソフトエラーに対して強い高
信頼性のエピタキシャルウェハを提供できる。As detailed above, according to this research, even when the diameter is increased, it is resistant to thermal distortion, has less slippage, and can suppress step breakage when forming wiring in the epitaxial layer and junction retarding when forming elements. together with MO3
When applied to LSI, it is possible to provide a highly reliable epitaxial wafer that is resistant to soft errors.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本実施例に使用するエピタキシャル成長炉の概
略図、第２図はエピタキシャル層中のＮ２ｍ度とスリッ
プの最大長さとの関係を示す特性図、第３図はＤ／ｐ＋
エピタキシャルウェハのポテンシャルの断面方向の分布
を示す特性図である。 １・・・チャンバ、２・・・サセプタ、３・−・高周波
コイル、４・・・ガス導入管、５〜９・・・ボンベ、１
０・・・ｐ型シリコンウェハ。Fig. 1 is a schematic diagram of the epitaxial growth furnace used in this example, Fig. 2 is a characteristic diagram showing the relationship between N2m degrees in the epitaxial layer and the maximum slip length, and Fig. 3 is a D/p+
FIG. 2 is a characteristic diagram showing a distribution of potential in a cross-sectional direction of an epitaxial wafer. DESCRIPTION OF SYMBOLS 1... Chamber, 2... Susceptor, 3... High frequency coil, 4... Gas introduction pipe, 5-9... Cylinder, 1
0...p-type silicon wafer.

Claims (3)

【特許請求の範囲】[Claims] （１）基板ウェハ上に窒素濃度の異なる少なくとも２つ
以上の領域を有するエピタキシャル層を設けてなるエピ
タキシャルウェハ。(1) An epitaxial wafer in which an epitaxial layer having at least two regions having different nitrogen concentrations is provided on a substrate wafer. （２）エピタキシャル層として、表面付近の領域の窒素
濃度が基板ウェハとの界面付近の領域の窒素濃度より低
いものを用いることを特徴とする特許請求の範囲第１項
記載のエピタキシャルウェハ。(2) The epitaxial wafer according to claim 1, wherein the epitaxial layer has a nitrogen concentration lower in a region near the surface than in a region near the interface with the substrate wafer. （３）エピタキシャル層中の窒素濃度の高い領域の濃度
が１×１０＾１＾５ｃｍ＾−＾３〜１×１０＾１＾６で
、窒素濃度の低い領域の濃度が１×１０＾１＾５ｃｍ＾
−＾３以下であることを特徴とする特許請求の範囲第１
項又は第２項記載のエピタキシャルウェハ。(3) The concentration in the region with high nitrogen concentration in the epitaxial layer is 1 × 10^1^5 cm^-^3 to 1 × 10^1^6, and the concentration in the region with low nitrogen concentration is 1 × 10^1^ 5cm^
Claim 1 characterized in that -^3 or less
The epitaxial wafer according to item 1 or 2.
JP24650484A 1984-11-21 1984-11-21 Epitaxial wafer Pending JPS61125012A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24650484A JPS61125012A (en) 1984-11-21 1984-11-21 Epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24650484A JPS61125012A (en) 1984-11-21 1984-11-21 Epitaxial wafer

Publications (1)

Publication Number Publication Date
JPS61125012A true JPS61125012A (en) 1986-06-12

Family

ID=17149380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24650484A Pending JPS61125012A (en) 1984-11-21 1984-11-21 Epitaxial wafer

Country Status (1)

Country Link
JP (1) JPS61125012A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250434A (en) * 1988-08-11 1990-02-20 Nec Corp Semiconductor device
WO2004034453A1 (en) * 2002-10-04 2004-04-22 Silicon Genesis Corporation Method for treating semiconductor material
JP2016500475A (en) * 2012-12-06 2016-01-12 ジルトロニック アクチエンゲゼルシャフトＳｉｌｔｒｏｎｉｃ ＡＧ Epitaxial wafer and method for manufacturing the same
US9640711B2 (en) 2006-09-08 2017-05-02 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
CN110349841A (en) * 2019-07-18 2019-10-18 中国电子科技集团公司第四十六研究所 A kind of preparation method of double-layer structure silicon epitaxial wafer
CN111463116A (en) * 2020-04-27 2020-07-28 中国电子科技集团公司第四十六研究所 Preparation method of double-layer epitaxy for MOS device structure
US11444221B2 (en) 2008-05-07 2022-09-13 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250434A (en) * 1988-08-11 1990-02-20 Nec Corp Semiconductor device
WO2004034453A1 (en) * 2002-10-04 2004-04-22 Silicon Genesis Corporation Method for treating semiconductor material
US7147709B1 (en) 2002-10-04 2006-12-12 Silicon Genesis Corporation Non-contact etch annealing of strained layers
US9640711B2 (en) 2006-09-08 2017-05-02 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US11444221B2 (en) 2008-05-07 2022-09-13 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
JP2016500475A (en) * 2012-12-06 2016-01-12 ジルトロニック アクチエンゲゼルシャフトＳｉｌｔｒｏｎｉｃ ＡＧ Epitaxial wafer and method for manufacturing the same
US9691632B2 (en) 2012-12-06 2017-06-27 Siltronic Ag Epitaxial wafer and a method of manufacturing thereof
CN110349841A (en) * 2019-07-18 2019-10-18 中国电子科技集团公司第四十六研究所 A kind of preparation method of double-layer structure silicon epitaxial wafer
CN110349841B (en) * 2019-07-18 2021-04-09 中国电子科技集团公司第四十六研究所 Preparation method of double-layer structure silicon epitaxial wafer
CN111463116A (en) * 2020-04-27 2020-07-28 中国电子科技集团公司第四十六研究所 Preparation method of double-layer epitaxy for MOS device structure
CN111463116B (en) * 2020-04-27 2022-04-12 中国电子科技集团公司第四十六研究所 Preparation method of double-layer epitaxy for MOS device structure

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