JPS61116682A - Electronic timepiece - Google Patents

Electronic timepiece

Info

Publication number
JPS61116682A
JPS61116682A JP25309085A JP25309085A JPS61116682A JP S61116682 A JPS61116682 A JP S61116682A JP 25309085 A JP25309085 A JP 25309085A JP 25309085 A JP25309085 A JP 25309085A JP S61116682 A JPS61116682 A JP S61116682A
Authority
JP
Japan
Prior art keywords
pulse
circuit
drive
output
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25309085A
Other languages
Japanese (ja)
Other versions
JPS6334435B2 (en
Inventor
Akio Nakajima
中島 章夫
Tadayasu Machida
町田 任康
Kenji Yamada
健次 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP25309085A priority Critical patent/JPS61116682A/en
Publication of JPS61116682A publication Critical patent/JPS61116682A/en
Publication of JPS6334435B2 publication Critical patent/JPS6334435B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04CELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/14Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electromechanical Clocks (AREA)
  • Control Of Stepping Motors (AREA)

Abstract

PURPOSE:To elevate the load resistance characteristic, impact resistance and stability, by a method wherein a drive coil is grounded at end thereof through a transistor low in the output resistance while being done at the other end thereof through a transistor high in the output resistance while no drive pulse is applied. CONSTITUTION:This electronic timepiece is made up of an oscillation circuit 115, a frequency dividing circuit 116, a pulse generation circuit 117, a pulse motor driving circuit 118 comprising a plurality of MOSFETs 218-223 to be controlled independently, a detection circuit 233 which detects an induced voltage to be generated in a drive coil after a drive pulse to a pulse motor is interrupted and the like. A drive coil 217 is connected between common drains (a) and (b) of MOSFETs 222 and 223 high in the output resistance while terminals (a) and (b) are connected o respective input gates of induced voltage detection inverters 225 and 224. Then, while no drive pulse is applied, the MOSFET 221 is OFF and the MOSFETs 220 and 223 are ON. The (a) terminal is grounded through the MOSFET 220 low in the output resistance while the (b) terminal is grounded through the MOSFET 223 high in the output resistance.

Description

【発明の詳細な説明】 本発明は電子時計におけるノルスモータの駆動回路に関
するものであり、本発明の目的はパルスモータの低消費
電力化を計ると共に高信頼化をも達成することにある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a Norse motor in an electronic timepiece, and an object of the present invention is to reduce the power consumption of a pulse motor and also to achieve high reliability.

電子時計用として使用されているパルスモータの駆動回
路について、定常時は低出力で良いため比較的狭い・2
ルス巾の駆動パルスとして消費電流を低減し、曜日送り
負荷時、衝撃負荷時等の異常時にノ!ルス巾を駆動コイ
ルの誘起電圧によって制御してステップ状に広く設定し
高出力とする方式が提案されている。
Regarding the drive circuit of the pulse motor used for electronic watches, it is relatively narrow because low output is required during steady state.
The current consumption is reduced by using pulse-width drive pulses, and it can be used during abnormalities such as day-of-the-week feed loads and shock loads. A method has been proposed in which the pulse width is controlled by the induced voltage of the drive coil and set widely in steps to achieve high output.

しかるに上記方式は駆動コイルの誘起電圧を検出するた
めに、駆動・やルスが切れた直後に駆動コイルを開回路
とするため、誘起電圧による制動力が・母ルスモータの
回転子にまつ°たく働かず、したがって、回転が不安定
となシステップ送り等の誤動作が生じやすく、また誘起
電圧が直接検出用インバータ入力に印加されるため、イ
ン・ぐ−夕のし ゛きい値電圧に合せて駆動コイルの巻
数を設定する必要があるという欠点がある。
However, in the above method, in order to detect the induced voltage in the drive coil, the drive coil is opened immediately after the drive pulse is cut off, so the braking force due to the induced voltage is not applied to the rotor of the main pulse motor. Therefore, malfunctions such as step feed due to unstable rotation are likely to occur, and since the induced voltage is directly applied to the input of the inverter for detection, it is difficult to drive according to the threshold voltage of the inverter. The disadvantage is that the number of turns of the coil must be set.

更に、2相の交互、駆動パルスの1つの相の駆動パルス
が切れた直後の誘起電圧で次の相の1パルスのパルス巾
を制御するため誘起電圧がしきい値電圧近傍のときはパ
ルス巾が1パルス毎に切換り必要な出力が得られないだ
め誤動作する場合が生じるという欠点もあった。
Furthermore, in the two-phase alternating drive pulse, the pulse width of one pulse of the next phase is controlled by the induced voltage immediately after the driving pulse of one phase is cut off, so when the induced voltage is near the threshold voltage, the pulse width There was also a drawback that the output was switched for each pulse, resulting in a malfunction if the required output could not be obtained.

本発明は上述の欠点のない耐負荷特性、耐衝撃性が良く
安定度が高いパルスモータ駆動回路を提供するものであ
る。
The present invention provides a pulse motor drive circuit that does not have the above-mentioned drawbacks and has good load-bearing characteristics, good impact resistance, and high stability.

本発明は定常時と異常時が相異なる一定・2ルス巾の駆
動パルスによって駆動される時計用パルスモータにおい
て、駆動パルスが印加されていない間は駆動コイルの一
端は出力抵抗の低いトランジスタ、他端は出力抵抗の高
いトランジスタを介して接地されることを特徴とする時
計用・母ルスモータ駆動回路を提供することを目的とす
る。
The present invention provides a pulse motor for a watch that is driven by a constant 2-pulse width drive pulse that is different during normal and abnormal times, and when the drive pulse is not applied, one end of the drive coil is connected to a transistor with low output resistance, etc. An object of the present invention is to provide a clock/main pulse motor drive circuit whose end is grounded via a transistor with high output resistance.

又、本発明は定常時と異常時が相異なる一定・2ルス巾
の駆動パルスによって駆動される時計用パルスモータに
おいて、異常時には一定時間持続して定常時とは異なる
一定パルス巾のパルスヲ供給することを特徴とするパル
スモータ駆動回路を提供することを目的とする。
Further, the present invention provides a pulse motor for a watch that is driven by driving pulses with a constant pulse width of 2 pulses, which are different during normal times and abnormal times, and which, during abnormal times, supplies a pulse with a constant pulse width that lasts for a certain period of time and is different from that during normal times. An object of the present invention is to provide a pulse motor drive circuit characterized by the following.

以下実施例について説明する。Examples will be described below.

第1図は、時計用パルスモータの一実施例で101は少
なくとも2極の磁極を有する磁石よりなる回転子、10
2.103は磁性材よりなる固定子、104は駆動コイ
ル、a、bは駆動コイル端子であり、a、bに印加され
る2相のパルス電圧による電流のため駆動コイルに発生
する磁束を固定子に導いて回転子を定方向にステップ状
に回転させるものである。また、第2図は時計用・2ル
スモータの他の実施例である。
FIG. 1 shows an example of a pulse motor for a watch, and 101 is a rotor made of a magnet having at least two magnetic poles;
2. 103 is a stator made of magnetic material, 104 is a drive coil, and a and b are drive coil terminals, which fix the magnetic flux generated in the drive coil due to the current due to the two-phase pulse voltage applied to a and b. The rotor is rotated in a fixed direction in a stepwise manner. Moreover, FIG. 2 shows another embodiment of a 2-ruth motor for a watch.

第3図は従来の時計用パルスモータ駆動回路の一実施例
のブロック図で110は発振回路、111は分周回路、
112は・にルス発生回路、113は駆動回路、114
は検出制御回路を示す。第4図は本発明の時計用パルス
モータ駆動回路の一実施例のブロック図で115は発振
回路、116は分周回路、117はパルス発生回路、1
18は駆動回路、119は検出制御回路、120は計数
回路を示す。第5図は本発明の駆動回路の具体的一実施
例であシ、第6図は駆動コイルの状態説明図、第7図、
第8図は各部の波形図であり、第7図は定常時、第8図
は負荷時の状態を示し、第9図は駆動回路の他の具体的
実施例を示す。
FIG. 3 is a block diagram of an embodiment of a conventional pulse motor drive circuit for a watch, in which 110 is an oscillation circuit, 111 is a frequency dividing circuit,
112 is a pulse generation circuit, 113 is a drive circuit, 114
indicates a detection control circuit. FIG. 4 is a block diagram of an embodiment of the pulse motor drive circuit for a watch according to the present invention, in which 115 is an oscillation circuit, 116 is a frequency dividing circuit, 117 is a pulse generation circuit, 1
18 is a drive circuit, 119 is a detection control circuit, and 120 is a counting circuit. FIG. 5 shows a specific embodiment of the drive circuit of the present invention, FIG. 6 is an explanatory diagram of the state of the drive coil, FIG.
FIG. 8 is a waveform diagram of each part, FIG. 7 shows a steady state, FIG. 8 shows a state under load, and FIG. 9 shows another specific example of the drive circuit.

第5図において、分周回路116のフリップ・70ツf
(以下FFと称する)208,209の出力はA?ルス
発生回路117のダート回路211の入力となっており
、定常時はF F 208の出力がパルス発生回路11
7のF F 214.215のリセット端子R,、R,
lに印加されて各出力Fl 、F2には短かい・2ルス
巾の・2ルスφ1、φ2が交互に発生する。また各出力
F、、F2は検出制御回路119のOR回路227の入
力に接続され、その出力はりセノトーセノトフリノプフ
ロノプ(以下R8−FFと称する)のS、端子に接続さ
れている。F F 214の他の出力F1はF F 2
16及びAND回路212.213で構成される制御回
路232のF F 216の入力及び、駆動回路118
のP−ahMOSトランノスタ218の入力に、F F
 215の出力P2はF F 216の他の入力及び駆
動回路118のP−chMOsトランジスタ219の入
力に接続され、F F 216の出力F、はN−chM
Osトランソスタ220、AND回路212の各入力に
、出力F3はN−chMOSトランノスタ221.AN
D回路213の各入力に接続されている。
In FIG. 5, the flip 70 f of the frequency dividing circuit 116
(hereinafter referred to as FF) 208, 209 output is A? It is the input to the dirt circuit 211 of the pulse generation circuit 117, and the output of the F F 208 is the input to the pulse generation circuit 11 during normal operation.
7 F F 214.215 reset terminal R,, R,
Short pulses φ1 and φ2 each having a width of 2 pulses are generated alternately at the respective outputs Fl and F2. In addition, each output F, F2 is connected to the input of the OR circuit 227 of the detection control circuit 119, and the output thereof is connected to the S terminal of the beam Senotosenotoflinopfuronop (hereinafter referred to as R8-FF). . The other output F1 of F F 214 is F F 2
16 and the input of F F 216 of the control circuit 232 composed of AND circuits 212 and 213, and the drive circuit 118
At the input of the P-ahMOS transistor 218, F F
The output P2 of the F F 215 is connected to the other input of the F F 216 and the input of the P-ch MOs transistor 219 of the drive circuit 118, and the output F of the F F 216 is connected to the N-ch M
The output F3 is connected to each input of the Os transformer 220 and the AND circuit 212, and the output F3 is connected to the N-chMOS transformer 221. AN
It is connected to each input of the D circuit 213.

制御回路232のAND回路212の他の入力にはF 
F 210の出力F0が、AND回路213の他の入力
には出力F。が接続され、AND回路212の出力はN
−chMOsトランジスタ223、AND回路213の
出力はN−chMOsトランジスタ222の各入力に接
続されている。駆動コイル217はMOSトランジスタ
の共通ドレインa、b間に接続され、a端子は誘起電圧
検出インバータ224.225及び出力抵抗の高いトラ
ンジスタ222,223で構成された検出回路233の
誘起電圧検出インバータ225、b端子は誘起電圧検出
インバータ224の各人力r−トに接続され、各出力は
r−ト回路226の入力に接続され、またダート回路2
26の他の入力にはF F 210の出力F0、Foが
接続され、出力nはR8−FF228のリセット端子R
4に接続されている。まだ、出力抵抗の高いトランジス
タ222.223、の代シに第9図に示す如くスイッチ
素子として動作する抵抗の低いトランジスタ303.3
04と高抵抗301.302の直列接続を用いてもよい
。AND回路229はR8−FF228の出力F4、及
びF F 210の入力φ。を2人力とし、その出力j
はR8−FF230のリセット端子R5に接続されてお
り、定常時はj=0に設定される。R8−FF 230
のセット端子S。
The other input of the AND circuit 212 of the control circuit 232 is F.
The output F0 of F210 is the output F0 to the other input of the AND circuit 213. is connected, and the output of the AND circuit 212 is N
The outputs of the -ch MOs transistor 223 and the AND circuit 213 are connected to each input of the N-ch MOs transistor 222. The drive coil 217 is connected between the common drains a and b of the MOS transistors, and the a terminal is connected to the induced voltage detection inverter 225 of the detection circuit 233, which is composed of induced voltage detection inverters 224 and 225 and transistors 222 and 223 with high output resistance. The b terminal is connected to each human power r-t of the induced voltage detection inverter 224, each output is connected to the input of the r-t circuit 226, and the dart circuit 2
The other inputs of FF26 are connected to the outputs F0 and Fo of FF210, and the output n is the reset terminal R of R8-FF228.
Connected to 4. In place of the transistors 222 and 223, which have high output resistance, a transistor 303 and 303, which has low resistance and operates as a switching element, is used as shown in FIG.
A series connection of 04 and high resistance 301, 302 may also be used. AND circuit 229 receives output F4 of R8-FF 228 and input φ of FF 210. is powered by two people, and the output j
is connected to the reset terminal R5 of R8-FF230, and is set to j=0 during normal operation. R8-FF 230
Set terminal S.

には計数回路120の出力が、出力F、にはリセット端
子R6が接続されており、またR8−FF230の各出
力FM 、F5はf−)回路211の入力に接続されこ
のy−ト回路211出力に応じてパルス発生回路117
はパルス巾の異なる出力パルスを発生する。
The output of the counting circuit 120 is connected to the output F, the reset terminal R6 is connected to the output F, and the outputs FM and F5 of R8-FF230 are connected to the input of the f-) circuit 211. Pulse generation circuit 117 according to the output
generates output pulses with different pulse widths.

第7図において、1 = 1.でφI/41ルスが発生
し、第5図の駆動回路118内のP−ah MOS ト
ランジスタ218はオンとなシ、N−ch M OS 
)ランジスタ221はオンとなっているため第6図(1
)の如くにな)駆動コイルa端子に駆動電圧が印加され
a→bに電流が流れ固定子102.103は励磁され回
転子101は右方向に180°回転し一定時間振動して
停止する。1 = 12で駆動パルスが切れた直後にN
−chMOsトランジスタ221はオフとなり、N−a
hMOSトランノスタ220、及び出力抵抗の高いN−
chMOSトランジスタ223(等価抵抗をrとする)
がオフとなシ、a端子ははソ直接、b端子は抵抗rを介
して接地され第6図(2)の如くになる。
In FIG. 7, 1 = 1. φI/41 pulse occurs, the P-ah MOS transistor 218 in the drive circuit 118 in FIG. 5 is turned on, and the N-ch MOS
) Since the transistor 221 is on, the
) A drive voltage is applied to the drive coil a terminal, a current flows from a to b, the stators 102 and 103 are excited, and the rotor 101 rotates 180° clockwise, vibrates for a certain period of time, and then stops. Immediately after the drive pulse ends at 1 = 12, N
-chMOs transistor 221 is turned off, and N-a
hMOS trannostar 220 and high output resistance N-
chMOS transistor 223 (equivalent resistance is r)
When it is off, the a terminal is directly grounded and the b terminal is grounded through the resistor r, as shown in FIG. 6(2).

回転子の回転にともなう誘起電圧は分圧されて検出回路
233の検出インバータ224に印加され、L= 1.
〜t4で誘起電圧がインバータのしきい値電圧以上とな
!IM”−ト回路出力nが発生する。φ1によって1=
1.でR8−FF288の出力i = lにセットされ
たものがe−)回路出力nによpt=t、でi=0にリ
セットされる。したがってAND回路出力j=oであシ
、R8−F’F230の出力F、=1、F。
The induced voltage caused by the rotation of the rotor is divided and applied to the detection inverter 224 of the detection circuit 233, so that L=1.
~At t4, the induced voltage exceeds the threshold voltage of the inverter! IM”-to circuit output n is generated. 1= due to φ1
1. The output i of R8-FF288 which is set to l is reset to e-) pt=t by the circuit output n, and i=0 by the circuit output n. Therefore, the AND circuit output j=o, and the output F of R8-F'F230 is 1, F.

=Oとなっておシ、r−ト回路211は高い周波数の分
周出力をノクルス発生回路117のF F 214.2
15゜の各リセット端子R,、R2に印加するから駆動
パルス巾は狭く設定されている。
=O, and the r-to circuit 211 sends the high frequency divided output to the Noculus generating circuit 117's F F 214.2.
Since the driving pulse width is applied to each of the reset terminals R, R2 at an angle of 15 degrees, the width of the driving pulse is set narrow.

次に1 = 1.でφ2/#ルスが発生し、P−chM
Osトランジスタ219はオンとなシ、N−chMOs
トランジスタ220はオンとなっているため、第6図(
3)の如くになシ、駆動コイルのb端子に駆動電圧が印
加されb→aに電流が流れ固定子102,103は前と
は逆に励磁され回転子は右方向に再び180゜回転し一
定時間振動して停止する。1=1.で駆動ノンルスが切
れた直後にN−ah M OS )ランジスタ220は
オフとなシ、N−ah M OS トランジスタ221
、及び出力抵抗の高いN−ah M OS )う/ジメ
タ222(等価抵抗をrとする)がオンとなり、b端子
ははソ直接、a端子は抵抗rを介して接地され第6図(
4)の如くになる。回転子の回転にともなう誘起電圧は
分圧されて検出回路233の検出イン、バーク225に
印加され、1 = 17〜t8で誘起電圧がインバータ
ーのしきい値電圧以上とな、by−ト回路出力が発生し
、以下は前と同様にして駆動・千ルス巾は狭く設定され
る。すなわち定常時に無負荷状態で駆動コイルの誘起電
圧が検出用インバーターのしきい値電圧以上あれば、・
やルス巾は狭く設定され、駆動・2ルスが印加されてい
ない間は駆動コイルは等価抵抗rを介して閉回路となシ
、誘起電圧により制動電流が流れるため回転子の動作の
安定化が著しく向上する。駆動パルスが切れた直後の駆
動コイルの誘起電圧をV、駆動コイル抵抗をRとすれば
、検出用インバーターに印加される電圧はrv/(R+
r)となシ、等価抵抗rを変えることによシ検出インバ
ーターのしきい値電圧に合せることが可能である。負荷
がかかって異常状態となった場合を考えてみる。第8図
に於て最初は正常で1 = 1.、〜1.□で狭い駆動
・マルスが駆動コイルに印加され、1 = 1.、〜t
14で検出インバーター出力が発生している。この状態
で負荷がかかってくると回転子の角速度が低下し1 =
 1.5以後の誘起電圧が検出用インバーターのしきい
値電圧以下となシ、1 = 1.でj出力が発生し、R
8−FF230のF、=0、F、=1にリセットされ、
r−ト回路211が切換り、低い周波数の分周出力がノ
ルス発生回路117のF F 214.215のR,、
R2に印加され駆動パルス巾はステップ状に広くなる。
Then 1 = 1. φ2/# rus occurs, and P-chM
Os transistor 219 is on, N-ch MOs
Since the transistor 220 is on, FIG.
As shown in 3), a driving voltage is applied to the b terminal of the driving coil, a current flows from b to a, the stators 102 and 103 are excited in the opposite direction, and the rotor rotates 180 degrees clockwise again. It vibrates for a certain period of time and then stops. 1=1. The N-ah M OS transistor 220 is turned off immediately after the drive non-current is cut off, and the N-ah M OS transistor 221 is turned off.
, and N-ah MOS with high output resistance) is turned on, and the b terminal is grounded directly and the a terminal is grounded through the resistor r, as shown in Fig. 6 (
4) It will look like this. The induced voltage accompanying the rotation of the rotor is divided and applied to the detection input of the detection circuit 233 and the bark 225, and when the induced voltage exceeds the threshold voltage of the inverter from 1 = 17 to t8, the by-to circuit outputs. occurs, and the following is the same as before, and the 1,000 rus width is set narrow. In other words, if the induced voltage of the drive coil is higher than the threshold voltage of the detection inverter under no-load condition during steady state,
The pulse width is set narrowly, and the drive coil is closed circuit through the equivalent resistance r while the drive/2 pulse is not applied, and the braking current flows due to the induced voltage, which stabilizes the operation of the rotor. Significantly improved. If the induced voltage in the drive coil immediately after the drive pulse is cut off is V, and the drive coil resistance is R, the voltage applied to the detection inverter is rv/(R+
r), it is possible to match the threshold voltage of the detection inverter by changing the equivalent resistance r. Let's consider a case where an abnormal state occurs due to a load. In Figure 8, initially it is normal and 1 = 1. ,~1. A narrow drive/malus is applied to the drive coil at □, 1 = 1. ,~t
Detection inverter output is generated at 14. When a load is applied in this state, the angular velocity of the rotor decreases and 1 =
The induced voltage after 1.5 must be below the threshold voltage of the detection inverter, 1 = 1. j output occurs, and R
8-FF230 F, = 0, F, = 1 is reset,
The r-t circuit 211 switches, and the low frequency divided output is sent to the Nors generation circuit 117's F F 214, R of 215,...
The width of the drive pulse applied to R2 increases stepwise.

−力計数回路120のリセットは解除され、駆動パルス
数の計数を開始する。例えば曜日送りに要するパルス数
程度にパルス計数回路を設定しておけば、曜日送り開始
にともない駆動パルス巾が広くなり、曜日送シ終了後に
計数出力が発生しR8−FF230のS、端子にセット
パルスが印加され、F、=1、F。
- The reset of the force counting circuit 120 is released and starts counting the number of drive pulses. For example, if the pulse counting circuit is set to the number of pulses required to feed the day of the week, the width of the drive pulse will become wider as the day of the week feed starts, and a count output will be generated after the day of the week feed is finished and set to the S terminal of R8-FF230. A pulse is applied,F,=1,F.

=0となり、計数回路120はOリセットされ、ケ゛−
ト回路211が切換り負荷がない状態に戻シ狭いパルス
巾とすることができる。
= 0, the counting circuit 120 is reset to
The output circuit 211 can be switched back to a no-load condition with a narrow pulse width.

本願の如く構成すれば、定常時は変換機の駆動に必要な
最小限のパルス巾5ミリ冠以下の駆動パルスで駆動し、
曜日送り負荷が加わっている間を含む一定時間は5ミリ
冠以上のパルス巾にすることにより、負荷に耐え得る駆
動力を変換機に与えて誤動作を防止することにより、平
均消費電流を1μA以下に低減することが可能である。
If configured as in the present application, during normal operation, the converter is driven with a drive pulse with a minimum pulse width of 5 mm or less necessary for driving the converter,
By setting the pulse width to 5 mm or more during a certain period of time, including the period when the day of the week feed load is applied, the converter is given driving force that can withstand the load and prevents malfunction, thereby reducing the average current consumption to 1 μA or less. It is possible to reduce it to

また、駆動パルスの印加終了時に駆動コイルは抵抗の低
いトランジスタと抵抗の高いトランジスタ、又は第9図
に示す如く抵抗の低いトランジスタ及び高い抵抗を介し
て閉回路となり、誘起電圧による制動電流が流れるため
回転子の動作は著しく安定し2ステノグ送り等の誤動作
が防止できる。
Furthermore, when the application of the drive pulse ends, the drive coil becomes a closed circuit via a low resistance transistor and a high resistance transistor, or a low resistance transistor and a high resistance as shown in Figure 9, and a braking current due to the induced voltage flows. The operation of the rotor is extremely stable, and malfunctions such as 2-stenog feed can be prevented.

検出用インバータに印加する電圧は高い出力抵抗のトラ
ンジスタの等価抵抗r又は第9図に示す高抵抗301,
302の値を変えることにより容易にインバータのしき
い値電圧に合せ込みができるためパルスモータの回転子
の磁気モーメント、駆動コイルの巻数等の基本仕様を変
える必要がない利点も有する。
The voltage applied to the detection inverter is the equivalent resistance r of a transistor with a high output resistance, or the high resistance 301 shown in FIG.
Since the threshold voltage of the inverter can be easily adjusted by changing the value of 302, there is also the advantage that there is no need to change the basic specifications such as the magnetic moment of the rotor of the pulse motor and the number of turns of the drive coil.

本実施例では、出力抵抗の高いトランジスタを用いたが
、第9図に示す如く抵抗の低いトランジスタ303.3
04と高抵抗301.302を用いてもよい。抵抗の代
りに容量を用いることも可能であり、この場合はエネル
ギー蓄積が可能である。
In this embodiment, a transistor with high output resistance is used, but as shown in FIG.
04 and high resistance 301.302 may be used. It is also possible to use capacitors instead of resistors, in which case energy storage is possible.

さらに駆動コイルの誘起電圧をCMOSインバータで検
出するため、特に変換機に検出コイルを設けるとか、変
換機に接続した輪列に接点又は半導体を設けるとかの検
出機構を必要としない利点も有している。本実施例では
異常時に、駆動ノクルス巾が定常時の2倍になるように
設定したがステップ状に任意の・やルス巾に設定するこ
とも可能である。
Furthermore, since the induced voltage of the drive coil is detected by a CMOS inverter, there is an advantage that there is no need for a detection mechanism such as providing a detection coil in the converter or providing a contact or a semiconductor in the wheel train connected to the converter. There is. In this embodiment, the width of the driving nozzle is set to be twice as large as that during normal operation when there is an abnormality, but it is also possible to set the drive nozzle width to an arbitrary or somewhat arbitrary width in steps.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は時計用パルスモータの一実施例説明図、第2図
は他の実施例説明図、第3図は従来の時計用ノやルスモ
ータ駆動回路の一実施例のブロック図、第4図は本発明
の時計用パルスモータ駆動回路の一実施例のブロック図
、第5図は本発明の、駆動回路の具体的一実施例を示す
回路図、第6図(1)、(2)(3)、(4)は駆動コ
イルの状態説明図、第7図、第8図は各部の波形図、第
9図は駆動回路の他の具体的実施例を示す部分回路図で
ある。 112.117・・・・・−a4ルス発生回路113・
・・・・・・・・・・・・・・駆動回路114.119
・・・・・検出制御回路120・・・・・・・・・・・
・・・・計数回路218.219・・・・・・P−ch
MOsトランノスタ220、221 、222、223
 − =・N−c hMO8トランジスタ224.22
5・・・・・・検出用インバータ301.302・・・
・・・高抵抗 232・・・・・・・・・・・・・・・制御回路233
・・・・・・・・・・・・・検出回路第1図 第2図 第3図 第9図 第7図
Fig. 1 is an explanatory diagram of one embodiment of a pulse motor for a watch, Fig. 2 is an explanatory diagram of another embodiment, Fig. 3 is a block diagram of an embodiment of a conventional pulse motor drive circuit for a watch, and Fig. 4 is an explanatory diagram of an embodiment of a pulse motor for a watch. is a block diagram of an embodiment of the pulse motor drive circuit for a watch according to the present invention, FIG. 5 is a circuit diagram showing a specific embodiment of the drive circuit of the present invention, and FIGS. 6 (1), (2) ( 3) and (4) are state explanatory diagrams of the drive coil, FIGS. 7 and 8 are waveform diagrams of various parts, and FIG. 9 is a partial circuit diagram showing another specific example of the drive circuit. 112.117...-a4 pulse generation circuit 113.
・・・・・・・・・・・・・・・Drive circuit 114.119
...Detection control circuit 120...
...Counting circuit 218.219...P-ch
MOs Tranostar 220, 221, 222, 223
−=・N−c hMO8 transistor 224.22
5...Detection inverter 301.302...
...High resistance 232... Control circuit 233
・・・・・・・・・・・・Detection circuit Fig. 1 Fig. 2 Fig. 3 Fig. 9 Fig. 7

Claims (1)

【特許請求の範囲】[Claims] 発振回路、分周回路、各々独立に制御される複数のMO
Sトランジスタからなるパルスモータ駆動回路、駆動コ
イル及びロータを含むパルスモータ、前記パルスモータ
への駆動パルスを遮断した後に前記駆動コイルに発生す
る誘起電圧を検出する検出回路、パルス巾の異なる出力
パルスを発生するパルス発生回路、前記検出回路によっ
て制御され前記パルス発生回路のパルス巾大なる出力パ
ルスを前記パルスモータ駆動回路に供給する電子時計に
おいて、前記検出回路は前記パルスモータ駆動回路を構
成する駆動コイルの両端から同電位ラインに接続された
一対のMOSトランジスタの少なくとも一方に対して並
列接続された高抵抗とスイッチング素子との直列回路と
、前記高抵抗に発生する誘起電圧を検出するための検出
素子からなり、前記スイッチング素子と前記一対のMO
Sトランジスタの制御端子には各々スイッチング素子が
接続された側のMOSトランジスタにはスイッチング素
子と排他的にスイッチするための制御信号が供給され、
他方のMOSトランジスタにはスイッチング素子と同時
にスイッチするための制御信号が供給されることを特徴
とする電子時計。
Oscillator circuit, frequency divider circuit, multiple MOs each controlled independently
A pulse motor drive circuit consisting of an S transistor, a pulse motor including a drive coil and a rotor, a detection circuit that detects an induced voltage generated in the drive coil after cutting off a drive pulse to the pulse motor, and a detection circuit that detects an induced voltage generated in the drive coil after cutting off a drive pulse to the pulse motor, and output pulses with different pulse widths. In an electronic timepiece that is controlled by a pulse generation circuit that generates a pulse, and that is controlled by the detection circuit and supplies an output pulse having a large pulse width from the pulse generation circuit to the pulse motor drive circuit, the detection circuit includes a drive coil that constitutes the pulse motor drive circuit. a series circuit of a high resistor and a switching element connected in parallel to at least one of a pair of MOS transistors connected to the same potential line from both ends of the resistor, and a detection element for detecting the induced voltage generated in the high resistor. the switching element and the pair of MOs;
A control signal for switching exclusively with the switching element is supplied to the MOS transistor on the side to which the switching element is connected to the control terminal of the S transistor, and
An electronic timepiece characterized in that the other MOS transistor is supplied with a control signal for switching simultaneously with the switching element.
JP25309085A 1985-11-12 1985-11-12 Electronic timepiece Granted JPS61116682A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25309085A JPS61116682A (en) 1985-11-12 1985-11-12 Electronic timepiece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25309085A JPS61116682A (en) 1985-11-12 1985-11-12 Electronic timepiece

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP7663977A Division JPS5412777A (en) 1977-06-29 1977-06-29 Pulse motor driving circuit for watches

Publications (2)

Publication Number Publication Date
JPS61116682A true JPS61116682A (en) 1986-06-04
JPS6334435B2 JPS6334435B2 (en) 1988-07-11

Family

ID=17246349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25309085A Granted JPS61116682A (en) 1985-11-12 1985-11-12 Electronic timepiece

Country Status (1)

Country Link
JP (1) JPS61116682A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11127595A (en) * 1997-08-11 1999-05-11 Seiko Epson Corp Electronic equipment

Also Published As

Publication number Publication date
JPS6334435B2 (en) 1988-07-11

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