JPS61105587A - Crt controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a CRT control device whose purpose is to display large amounts of data at high speed.

[Background of the invention]

FIG. 2 shows a conventional display control device for code format data, and FIG. 3 shows a conventional display control device for bit correspondence format data.

In FIG. 2, the display dot clock generated by oscillator 1 (one dot is displayed in one cycle of this clock) is frequency-divided by divider 2 and input as the clock to refresh counter 3. The refresh counter counts the address of the CR1 display character, and that address is selected by the selector 5, and the contents of the display address in the refresh memory 6 are sequentially read out. When displaying data on a CRT, the selector uses the selection line 25,
The contents of the refresh memory are RD by the processor of 4.
/WR, select selection 1j124.

Display characters are stored in the refresh memory in CG code format. The CG code read from the refresh memory is converted into display character dot data within the CG memory and output as parallel data. If this parallel data line 27 has m bits, the 20 minute period produces a clock 22 which is the frequency of the display dot clock 21 divided by 1/m.

The m-bit parallel display data output from the CG memory is
The signal is converted from parallel to direct by the shift register No. 7, and sent as video data to the CRT display at the timing of the display dot clock 2B generated by the oscillator No. 1.

As shown in FIG. 3, refresh memory 6 stores one bit of bit data to be displayed on the CRT display and one bit of memory data in a 1:11 correspondence.

The n-bit parallel data read from the refresh memory is parallel/serial converted into video data by a shift register 7 without passing through a CG memory as shown at 8 in FIG.

[Purpose of the invention]

An object of the present invention is to reduce the conversion speed of a shift register that converts the read contents of a display memory from parallel to direct, thereby making it possible to operate with a low-speed clock.

[Summary of the invention]

The present invention provides a plurality of shift registers that perform parallel/serial conversion of parallel dot data read from memory to generate serial video data, divides the parallel read data from memory, performs parallel/serial conversion, and outputs each data. This CRT control device is characterized in that the clock frequency of each shift register can be made lower than the display dot frequency by alternately switching and outputting.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention.

The n-bit parallel data read from the refresh memory is transferred to X shift registers (5ift■ to 5ift■)
Each bit is allocated in order of K, and each shift register is operated by a clock divided by the divider 9 to the period of the display dot clock, and the output data of each shift register is sequentially selected by 10 selectors. , becomes video data. 11 is part of the invention.

〔Effect of the invention〕

In the conventional technology, as the amount of display data on one screen increases and as a result the frequency of the table-dot clock increases, the shift register also needs to operate at high speed.
According to the present invention, even if the frequency of the display dot clock becomes high, by providing multiple stages of shift registers, the display can be operated with a clock slower than the display dot clock, and a shift register with a slower operating speed can be used. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional code format data display control device, and FIG.
The figure is a block diagram of a conventional display control device for bit-compatible format data. 1... Oscillator, 2... Brancher, 3...
・Refresh counter, 4... Processor, 5... Selector, 6...
・Refresh memory, 7...Shift register, 8...CG memory, 9...
- Frequency divider, 10... selector.

Claims (1)

[Claims] 1. A CRT control device that scans and sequentially reads out the contents of a memory buffer in which display dot data is stored in bit correspondence and displays the video signal on the screen, or the contents of a memory buffer in which display dot data is stored in code format. After scanning and sequentially reading out the code data and converting the code data into dot data, the CRT control device that displays the video signal on the screen performs parallel/serial conversion on the parallel dot data read from the memory to generate serial video data. The clock frequency of each shift register can be adjusted from the display dot frequency by providing multiple shift registers, dividing the parallel read data from the memory, performing parallel/direct conversion, and alternately switching and outputting the respective output data. A CRT control device characterized by being able to be made low.