JPS6095771U - Panel type image display device - Google Patents

Panel type image display device

Info

Publication number
JPS6095771U
JPS6095771U JP18693083U JP18693083U JPS6095771U JP S6095771 U JPS6095771 U JP S6095771U JP 18693083 U JP18693083 U JP 18693083U JP 18693083 U JP18693083 U JP 18693083U JP S6095771 U JPS6095771 U JP S6095771U
Authority
JP
Japan
Prior art keywords
circuit
gate
data
type image
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18693083U
Other languages
Japanese (ja)
Other versions
JPH0353273Y2 (en
Inventor
俊二 樫山
三朗 小林
Original Assignee
カシオ計算機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by カシオ計算機株式会社 filed Critical カシオ計算機株式会社
Priority to JP18693083U priority Critical patent/JPS6095771U/en
Publication of JPS6095771U publication Critical patent/JPS6095771U/en
Application granted granted Critical
Publication of JPH0353273Y2 publication Critical patent/JPH0353273Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例、を示す回路構成図、第2図
及び第3図は同実施例の主要ゲート部分の詳細を示す回
路図、第4図は本考案の他の実施例を示す回路構成図、
第5図及び第6図は同実施例におけるオア回路部分の詳
細を示す回路図である。
Fig. 1 is a circuit configuration diagram showing one embodiment of the present invention, Figs. 2 and 3 are circuit diagrams showing details of the main gate portion of the same embodiment, and Fig. 4 is another embodiment of the present invention. A circuit configuration diagram showing
FIGS. 5 and 6 are circuit diagrams showing details of the OR circuit portion in the same embodiment.

Claims (1)

【実用新案登録請求の範囲】 (1j  テレビジョン信号を受信して得られるアナロ
グビデオ信号をディジタルビデオ信号に変換し” で出
力するA/D変換回路と、キー人力データに対する処理
を実行する情報処理回路と、この情報処理回路で作成さ
れた表示データを記憶す゛、  る表示メモリと、上記
A/D変換回路から出力されるディジタルビデオ信号を
データバスラインに出力する第1のゲート回路と、上記
表示メモリから出力される表示データを上記パスライン
に出力する第2のゲート回路と、上記第1及び第2のゲ
ート回路を制御するゲート制御回路と、上記データバス
ラインを介して送られてくるディジタルデータをパネル
表示部に表示する表示制御回路とを具備してなるパネル
型画像表示装置。 (2)上記第1のゲート回路は、Kビットからなる階調
付ディジタルビデオ信号をゲート制御する回路であり、
上記第2のゲート回路は1ビツトからなる表示データを
にビットのディジタルデータに変換する回路を有してい
ることを特徴とする実用新案登録請求の範囲第(1)項
記載のパネル型画像表示装置。 (β)上記ゲート制御回路は、′上記第1のゲート回路
と上記第2のゲート回路を背反的に開閉制御する回路を
有していることを特徴とする実用新案登録請求の範−第
(1)項記載のパネル型画像表示装置。      −
− (4)  上記ゲート制御回路は、上記ディジタルビデ
オ信号と上記表示データを同時に上記パスラインに出力
させる制御回路を有していることを等徴とする実用新案
登録請求の範囲第(1)項記載のパネル型画像表示装置
[Claims for Utility Model Registration] (1j) An A/D conversion circuit that converts an analog video signal obtained by receiving a television signal into a digital video signal and outputs it, and information processing that performs processing on key human data. a display memory that stores display data created by the information processing circuit; a first gate circuit that outputs the digital video signal output from the A/D conversion circuit to the data bus line; A second gate circuit that outputs display data output from the display memory to the pass line, a gate control circuit that controls the first and second gate circuits, and display data that is sent via the data bus line. A panel-type image display device comprising a display control circuit that displays digital data on a panel display section. (2) The first gate circuit is a circuit that gate-controls a gradated digital video signal consisting of K bits. and
The panel type image display according to claim (1) of the utility model registration, characterized in that the second gate circuit has a circuit for converting display data consisting of 1 bit into digital data of 2 bits. Device. (β) The above-mentioned gate control circuit has a circuit that controls the opening and closing of the above-mentioned first gate circuit and the above-mentioned second gate circuit in a contradictory manner. The panel type image display device according to item 1). −
- (4) Utility model registration claim (1) wherein the gate control circuit includes a control circuit that simultaneously outputs the digital video signal and the display data to the pass line. The panel type image display device described above.
JP18693083U 1983-12-05 1983-12-05 Panel type image display device Granted JPS6095771U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18693083U JPS6095771U (en) 1983-12-05 1983-12-05 Panel type image display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18693083U JPS6095771U (en) 1983-12-05 1983-12-05 Panel type image display device

Publications (2)

Publication Number Publication Date
JPS6095771U true JPS6095771U (en) 1985-06-29
JPH0353273Y2 JPH0353273Y2 (en) 1991-11-20

Family

ID=30403628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18693083U Granted JPS6095771U (en) 1983-12-05 1983-12-05 Panel type image display device

Country Status (1)

Country Link
JP (1) JPS6095771U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6335099U (en) * 1986-08-25 1988-03-07

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5450289A (en) * 1977-09-27 1979-04-20 Sharp Corp Multi-gradation image display device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5450289A (en) * 1977-09-27 1979-04-20 Sharp Corp Multi-gradation image display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6335099U (en) * 1986-08-25 1988-03-07

Also Published As

Publication number Publication date
JPH0353273Y2 (en) 1991-11-20

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