JPS609150A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS609150A
JPS609150A JP58117305A JP11730583A JPS609150A JP S609150 A JPS609150 A JP S609150A JP 58117305 A JP58117305 A JP 58117305A JP 11730583 A JP11730583 A JP 11730583A JP S609150 A JPS609150 A JP S609150A
Authority
JP
Japan
Prior art keywords
electrode
gold
drain
layers
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58117305A
Other languages
Japanese (ja)
Inventor
Tatsuo Matsumura
達雄 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58117305A priority Critical patent/JPS609150A/en
Publication of JPS609150A publication Critical patent/JPS609150A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To realize a GaAs MES-FET having a resistance to the external stress and a pad with high wire-bonding strength by a method wherein the surface layers of wiring electrodes formed on the semiinsulative substrate of a compound semiconductor are respectively formed of a gold electrode consisting of two layers, each having a different purity. CONSTITUTION:An active layer 55 is formed at a region in a semiinsulative GaAs substrate 11, where an oxide film window has been opened, and after that, a photo resist is applied, drain and source electrode windows are opened thereon and an AuGe and an Au are successively evaporated from the upper part of the resist film. After then, a drain ohmic electrode 77 is formed. After this, a heating treatment is performed in the atmosphere of N2 and an ohmic contact is formed in between the drain ohmic electrode 77 and the active layer. Then, an aluminum is evaporated and after a Schottky gate electrode 66 was formed, Ti and Pt are successively evaporated on the whole surface as a buffer metal layer 88. After that, first gold-plating layers 100 and 100G are formed, and following that, second gold-plating layers 110 and 110G are formed. Lastly, an unwanted part of the buffer metal layer 88 is removed and a gate electrode 2 and a drain electrode 4 are formed.

Description

【発明の詳細な説明】 （イ）発明の技術分野 本発明は、外部引出電極の最上層が二種以上の金電極膜
構造から成る化合物半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a compound semiconductor device in which the uppermost layer of an external lead electrode has a structure of two or more types of gold electrode films.

一Ω玉と運９に枝）ｊと問題点 Ｘバンド以上のマイクロ波大電力増幅用のガリウム・砒
素（ＧａＡｓ）ショットキー形電界効果トランジスタ（
以下ＧａＡｓ　ＭＥＳ　ＦＢＴ）における最近の構造は
ゲート長を０．７μｍ、にまで短縮しており、集積密度
の向上に伴う放熱をより良好にするため、半導体基板の
厚さを従来１００μｍであったが２０μｍにまで薄クシ
ている。この外部接続線を接続させる配線電極（以降ホ
ンディングバンドと略称）における、ゲート部のポンデ
ィングパッドサイズは５０μｍスクエアで形成されてお
り、接続される金ワイヤ径は２５μφでボンディングに
より広がる金ワイヤの最大幅は４０μとなる。1 ohm ball and luck 9 branches)j and problems Gallium arsenide (GaAs) Schottky field effect transistor for microwave high power amplification above X band (
Recent structures in GaAs MES FBT (hereinafter referred to as GaAs MES FBT) have shortened the gate length to 0.7 μm, and in order to improve heat dissipation due to increased integration density, the thickness of the semiconductor substrate has been reduced from the conventional 100 μm. It is combed as thin as 20 μm. The bonding pad size of the gate part of the wiring electrode (hereinafter abbreviated as "bonding band") to which this external connection wire is connected is formed in a 50μm square, and the diameter of the gold wire to be connected is 25μφ, and the gold wire is expanded by bonding. The maximum width is 40μ.

上記構造を持つ、マイクロ波増幅に使用される。It has the above structure and is used for microwave amplification.

ＧａＡｓ　ＭＥＳ　ＦＥＴの電気的特性は、ゲート幅１
　ｍ＋ｎ当り周波数１２ＧＨｚで出力電力０．５〜０゜
６Ｗ、効率３０％を得ている。The electrical characteristics of GaAs MES FET are as follows:
At a frequency of 12 GHz per m+n, an output power of 0.5 to 0°6 W and an efficiency of 30% are obtained.

かかる構造のＧａＡｓ　ＭＥＳ　ＦＥＴの一例を模式的
に第１図に平面図で、また第２図ｆａ）にＸ−ｘ’断面
図で夫々示す。尚、第２図（ｂｌは本発明に至る改善案
装置のｘ−ｘ　’断面に相当する断面図を示す。An example of a GaAs MES FET having such a structure is schematically shown in a plan view in FIG. 1 and in a sectional view taken along the line X-x' in FIG. Incidentally, FIG. 2 (bl shows a sectional view corresponding to the xx' section of the improved device according to the present invention).

同図において、１は半絶縁性ＧａＡｓ基板、２゜２′は
ゲート電極、３はソース電極、４はドレイン電極、５は
ｎ型能動層、６はシｑ　’７トキ電極を示す。In the figure, 1 is a semi-insulating GaAs substrate, 2°2' is a gate electrode, 3 is a source electrode, 4 is a drain electrode, 5 is an n-type active layer, and 6 is a square electrode.

外部接続線を接続させる配線電極（ボンディングパソド
）２．４は大略下記の構造を持つ。The wiring electrode (bonding pad) 2.4 to which the external connection line is connected has approximately the following structure.

第２図ｔａ）参照 ドレイン電極パッド４の第１層目にドレインオーミック
コンタクト層７が、金、ゲルマニウム（ＡｕＧｅ）を厚
さ２００人、次に金（Ａｕ）を厚さ４０００人真空蒸着
し、その後熱処理して形成されている。次いでドレイン
電極におけるバッファ層８及びゲーｌ〜電極用バッファ
５８Ｇとしてチタン（Ｔｉ）が厚さ２０００人、白金（
ｐ　ｔ）が厚さ１５００人に積層形成され、最上層とし
ては金メッキ１５９．９Ｇを厚さ１μｍに各電極２，４
に形成されている。FIG. 2 ta) The drain ohmic contact layer 7 is formed on the first layer of the reference drain electrode pad 4 by vacuum-depositing gold and germanium (AuGe) to a thickness of 200 layers, and then vacuum-depositing gold (Au) to a thickness of 4000 layers. It is then formed by heat treatment. Next, as the buffer layer 8 in the drain electrode and the electrode buffer 58G, titanium (Ti) is formed to a thickness of 2000 mm, and platinum (
Pt) is laminated to a thickness of 1500 mm, and the top layer is gold plated 159.9G with a thickness of 1 μm and each electrode 2,4
is formed.

以上述べた製造方法によるＧａＡｓ　ＭＥＳＦＥＴは下
記の如き問題点を有する。The GaAs MESFET manufactured by the manufacturing method described above has the following problems.

即ち、電極形成後、電気的良否選別工程でポンディング
パッド部へ測定プローグ（針）で接触チェックを行なう
が（プローブ先端の直径５μｍ。That is, after electrode formation, a contact check is performed on the bonding pad part with a measurement probe (needle) in the electrical quality screening process (the diameter of the probe tip is 5 μm).

加圧重量（２〜３ｇ）、ゲート側のボンディングバソト
２の積層膜９Ｇと８Ｇに突き抜は状の損傷が４０％程発
生し、さらに、バッファｆｆ１８Ｇ又はＧａＡｓ基板面
の露出が１０％程発生ずる。しかしドレインとソース側
のポンディングパッド部４と３には発生しない。このた
め、ゲートポンディングパ・ノド２の５０μｍスクエア
のエリアに金ワイヤ直径２５μφをポンディングすると
、ボンディング強度は、第４図に示す強度分布のごとく
、ドレイン・パッド側の２〜５ｇに対し、ゲートボンデ
ィングパッド側は０．２５〜２．５ｇと低く、バラツキ
も大きく、１ｇ以下の脆弱な強度を示すものが発生する
。さらにバッファ層８Ｇの損傷はＧａＡｓ基板とゲート
金メッキＮ９Ｇ、及びボンディングによる金ワイヤの反
応を招き、信頼度低下の要因となっている。Due to the pressurized weight (2 to 3 g), about 40% of the laminated films 9G and 8G of the bonding base plate 2 on the gate side were damaged in the form of punctures, and about 10% of the buffer ff18G or GaAs substrate surface was exposed. Occurs. However, it does not occur in the bonding pad portions 4 and 3 on the drain and source sides. Therefore, when a gold wire with a diameter of 25μφ is bonded to a 50μm square area of the gate bonding pad node 2, the bonding strength will be 2 to 5g on the drain pad side, as shown in the intensity distribution shown in Figure 4. On the gate bonding pad side, the strength is as low as 0.25 to 2.5 g, and the variation is large, with some exhibiting weak strength of 1 g or less. Furthermore, damage to the buffer layer 8G causes a reaction between the GaAs substrate, the gate gold plating N9G, and the gold wire due to bonding, which causes a decrease in reliability.

上記問題の対策として、ドレーンパッド側４のドレイン
オーミック層７と同様に第２図（ｂｌのごとく、ゲート
側パッド側にも、金ゲルマニウム層（Ａｕｃｅ）７Ｇを
形成して、測定プローブに対する加圧応力を緩衛する方
法が考えられるが、その場合の新たな問題は、ゲート逆
耐圧である約−２０■に満たない−９〜−１２Ｖで約−
１００μＡの漏洩電流が前記Ａ　ｕ　Ｇ　ｅ　Ｎと半絶
縁性基板２０間に流れることがある。As a countermeasure to the above problem, a gold germanium layer (Auce) 7G is formed on the gate side pad side as well as the drain ohmic layer 7 on the drain pad side 4, as shown in FIG. A method to reduce the stress can be considered, but a new problem in that case is that the gate reverse withstand voltage of -20V is less than -9 to -12V, which is about -
A leakage current of 100 μA may flow between the A u G e N and the semi-insulating substrate 20 .

上記現象ば負電圧が印加されるゲートパ・ノドと前記基
板間に発生し、正電圧印加されるドレインパッドと（接
地側のソースバ・ノド）側には起とらない。現在上記現
象は理論的な解明は成されＴいないが、前記基板１が厚
さ２５μｍ以下に薄く加工され、ＡｕＧｅ１ｉ３７と７
Ｇをオーミックコンタクトさせるべく温度４５０℃時間
２分間の加熱を施すと発生することが確かめられている
。上記の状況を第５図にグラフで示してあり、同図にて
ＧａＡｓ基板の厚さを横軸に１００μＡの漏洩電流の発
生率を縦軸に示した。The above phenomenon occurs between the gate pad/node to which a negative voltage is applied and the substrate, and does not occur at the drain pad (source bar/node on the ground side) to which a positive voltage is applied. At present, the above phenomenon has not been theoretically elucidated, but the substrate 1 is thinned to a thickness of 25 μm or less, and AuGe1i37 and 7
It has been confirmed that this occurs when heating is performed at a temperature of 450° C. for 2 minutes to bring G into ohmic contact. The above situation is shown graphically in FIG. 5, in which the thickness of the GaAs substrate is plotted on the horizontal axis and the incidence of leakage current of 100 μA is plotted on the vertical axis.

」乙后衾肌夙ピ肛 本発明は、上記欠点に鑑み、外部応力に対し耐性があり
、ワイヤーポンディング強度の高いパッドを持つＧａＡ
ｓ　ＭＥＳ　ＦＥＴを得ることにある。In view of the above drawbacks, the present invention provides a GaA pad that is resistant to external stress and has a high wire bonding strength.
s MES FET.

」三ｌＪしＦｌ到又 本発明の前記目的は、化合物半導体の半絶縁性基板上に
形成された、外部接続線を接続させる配線電極の表面層
が純度の異なる二層の金電極から成熱半導体装置を提供
することによって達成される。Another object of the present invention is that the surface layer of a wiring electrode to which an external connection line is formed on a semi-insulating substrate of a compound semiconductor is formed from two layers of gold electrodes of different purity. This is achieved by providing a semiconductor device.

」慮１３１坏ηｕ１址 以下本発明を実施例により図面を参照して具体的に説明
する。The present invention will now be described in detail by way of embodiments with reference to the drawings.

第３図（ａ）乃至（Ｃ１は、第１図に示したのと同じ電
極パターンを有するＧａＡｓ　ＭＥＳ　ＦＥＴについて
の本発明実施例の製造工程を示すｘ−ｘ　’断面図であ
る。3(a) to (C1) are xx' cross-sectional views showing the manufacturing process of an embodiment of the present invention for a GaAs MES FET having the same electrode pattern as shown in FIG. 1.

半絶縁性ＧａＡｓ基板１１の酸化膜窓開きされた領域に
イオン注入法を適用し、動作Ｒ５５を形成した後、フォ
トレジストを塗布形成してこれにドレインおよびソース
電極窓開きし、このレジスト膜上方より真空蒸着法によ
り金、ゲルマニウム（ＡｕＧｅ）をｊｏｏ人、金（Ａｕ
）を４０００人の厚さに順次被着形成し、その後レジス
ト膜を除去するリフトオフ法によりドレインオーミンク
電極７７　（第１図のソース電極３も図示しないが同時
に）を形成する。その後動作層との間にオーミック接触
を形成するため、温度４２０°Ｃ１時間次に、アルミニ
ウムを厚さ７０００人真空蒸着し、リストオフ法でショ
ットキゲート電極６６を形成した後、バッファメタル層
８８としてチタン（Ｔｉ）を厚さ２０００人、白金（’
ｐｔ）を厚さ１５００人に順次全面に真空蒸着する。そ
の後、本発明に関する最上層の金メッキ層を形成させる
ための、メッキ用のフォトレジスト膜９９のパターンを
形成し、前記バッファ層８８をメッキ用の導電膜として
、まず、純度９９．９％の金（Ａｕ）を析出形成するメ
ッキ液（市販メッキ液商品名：ニュートロネクス３０９
）を使い、第１層目のメする。続いて、第２のメッキ層
として純度９９．９９％の軟賃金メッキ層を析出形成す
るメッキ液（市販メッキ液商品名：テンペレソクス）に
より、厚さ竿に被着さ１・第２金Ｊ　ｙ　−ｔ−Ｊｉｉ
　１１０及１１１０Ｇを形成する。形成された第１金メ
ッキ層１００及び１００Ｇばヌープ硬度５０〜８０ＨＶ
。After applying the ion implantation method to the oxide film window-opened region of the semi-insulating GaAs substrate 11 to form the operation R55, a photoresist is applied and formed, and the drain and source electrode windows are opened on this. Gold, germanium (AuGe) and gold (AuGe) are deposited using a vacuum evaporation method.
) are sequentially deposited to a thickness of 4,000 mm, and then a drain ohmink electrode 77 (the source electrode 3 in FIG. 1 is also not shown, but at the same time) is formed by a lift-off method in which the resist film is removed. Thereafter, in order to form an ohmic contact with the active layer, aluminum was vacuum-deposited at a temperature of 420° C. for 1 hour to a thickness of 7000 mm, and after forming a Schottky gate electrode 66 using the list-off method, a buffer metal layer 88 was formed. Titanium (Ti) with a thickness of 2000 mm and platinum ('
pt) was sequentially vacuum-deposited on the entire surface to a thickness of 1,500 mm. Thereafter, a pattern of a photoresist film 99 for plating is formed to form the uppermost gold plating layer according to the present invention, and the buffer layer 88 is used as a conductive film for plating. Plating solution that precipitates (Au) (commercially available plating solution product name: Neutronex 309)
) to create the first layer. Subsequently, a plating solution (commercially available plating solution trade name: TEMPERESOX) that precipitates and forms a soft plating layer with a purity of 99.99% as a second plating layer is applied to the rod with a thickness of 1. -t-Jii
110 and 1110G are formed. The formed first gold plating layer 100 and 100G has a Knoop hardness of 50 to 80HV.
.

第２金メツキＮ１１０及び１１０Ｇのそれは１３０〜１
９０ＨＶである。第３図（ａｌばこの第１．第２金メツ
キ工程完了状態を示しである。The second gold plated N110 and 110G are 130-1
It is 90HV. FIG. 3 shows the completed state of the first and second gold plating steps of the aluminum cigarette.

次いで、前記フォトレジスト膜１１０を除去し第３図（
ｂ）を得る。次に、バッファメタル層８８の不要部分を
金メッキ層をマスクとしてエツチングにより除去するこ
とにより、第３図（Ｃ）のごとくゲート電極２及び、ド
レイン電極４　（ソース電極第１図３を形成し、電極工
程が終了する。Next, the photoresist film 110 is removed and the photoresist film 110 is removed as shown in FIG.
b) obtain. Next, unnecessary portions of the buffer metal layer 88 are removed by etching using the gold plating layer as a mask, thereby forming the gate electrode 2 and the drain electrode 4 (source electrode 1) as shown in FIG. 3(C). The electrode process is completed.

第６図に、本実施例によって得られた電極に対するボン
ディング強度を示す。（ボンディングの条件は第５図に
同じ） エユＬλ乳Δ級敦 以上、詳細に説明したように、本発明の純度の異なる二
層の金電極は簡易な構成でありながら、薄い半絶縁半導
体基板の上に形成された微少な電極バットに安定な外部
引出線をボンディング可能ならしめ、信頼度の高いマイ
クロ波及び超高速度半導体装置を供し得るといった効果
がある。FIG. 6 shows the bonding strength for the electrodes obtained in this example. (The bonding conditions are the same as in FIG. 5) As explained in detail above, the two-layer gold electrode with different purity of the present invention has a simple structure, It is possible to bond a stable external lead wire to a minute electrode butt formed on the electrode, and there is an effect that a highly reliable microwave and ultra-high speed semiconductor device can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例を説明する為の平面図、第２図ｆａ）は
第１図のｘ−ｘ　’断面図、第２図（ｂ）は本発明に至
る提案装置に関する断面図、第３図ｆａ）乃至（Ｃ１は
本発明実施例を説明する為の工程要所に於けるｘ−ｘ　
’断面図、第４図は従来構造に於りる電極バットへの金
ワイヤ−ボンディング強度を表す分布図、第５図はＧａ
Ａｓ基板厚さとボンディングバット部の漏洩電流発生率
を表すグラフ、第６図は本発明により得られる電極パッ
ドへの金ワイヤ−ホンディング強度。 図に於いて、１はＧａＡｓ基板、２はゲート部ポンディ
ングパッド、２′はゲート電極、３はソース電極、４は
ドレイン部ボンディングバンド。 ４′はドレイン電極、５と５５は能動層、６と６６はシ
ョットキゲート電極、７と７７はドレインオーミック電
極、８と８８２はドレインバッファ層、８８はバッファ
層、９は金メッキ層、９９はレジスト膜、１００と１０
０Ｇは第１金メッキ層。 １１０と１１０Ｇは第２金メッキ層を示す。Fig. 1 is a plan view for explaining the conventional example, Fig. 2 (fa) is a sectional view taken along the line x-x' in Fig. Figure fa) to (C1 are x-x at key points in the process for explaining the embodiments of the present invention
' Cross-sectional view, Figure 4 is a distribution diagram showing the bonding strength of gold wire to the electrode butt in the conventional structure, Figure 5 is the Ga
A graph showing the leakage current generation rate of the bonding butt portion with respect to the thickness of the As substrate. FIG. 6 shows the bonding strength of the gold wire to the electrode pad obtained by the present invention. In the figure, 1 is a GaAs substrate, 2 is a gate bonding pad, 2' is a gate electrode, 3 is a source electrode, and 4 is a drain bonding band. 4' is a drain electrode, 5 and 55 are active layers, 6 and 66 are Schottky gate electrodes, 7 and 77 are drain ohmic electrodes, 8 and 882 are drain buffer layers, 88 is a buffer layer, 9 is a gold plating layer, 99 is a resist membrane, 100 and 10
0G is the first gold plating layer. 110 and 110G indicate the second gold plating layer.

Claims (1)

【特許請求の範囲】[Claims] 化合物半導体の半絶縁性基板上に形成された外部接続線
を接続させる配線電極の表面層が純度の異なる二層の金
電極膜からなることを特徴とする半導体装置。1. A semiconductor device characterized in that a surface layer of a wiring electrode for connecting an external connection line formed on a semi-insulating compound semiconductor substrate is composed of two layers of gold electrode films of different purity.
JP58117305A 1983-06-29 1983-06-29 Semiconductor device Pending JPS609150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58117305A JPS609150A (en) 1983-06-29 1983-06-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58117305A JPS609150A (en) 1983-06-29 1983-06-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS609150A true JPS609150A (en) 1985-01-18

Family

ID=14708460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58117305A Pending JPS609150A (en) 1983-06-29 1983-06-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS609150A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02103964A (en) * 1988-10-13 1990-04-17 Mitsubishi Electric Corp Semiconductor device
US5299339A (en) * 1990-05-14 1994-04-05 S. Sclayos S.A. Jet dyeing apparatus and method
US5425254A (en) * 1994-07-05 1995-06-20 Fang-Ping; Chen Dyeing machine without rollers
US5566559A (en) * 1995-09-05 1996-10-22 Chen; Fang-Ping Dyeing machine without rollers
JP2008147060A (en) * 2006-12-12 2008-06-26 Denso Corp Relay control device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02103964A (en) * 1988-10-13 1990-04-17 Mitsubishi Electric Corp Semiconductor device
US5299339A (en) * 1990-05-14 1994-04-05 S. Sclayos S.A. Jet dyeing apparatus and method
US5425254A (en) * 1994-07-05 1995-06-20 Fang-Ping; Chen Dyeing machine without rollers
US5566559A (en) * 1995-09-05 1996-10-22 Chen; Fang-Ping Dyeing machine without rollers
JP2008147060A (en) * 2006-12-12 2008-06-26 Denso Corp Relay control device

Similar Documents

Publication Publication Date Title
US5770489A (en) Method of making a compound semiconductor field-effect transistor
JPS609150A (en) Semiconductor device
US5260603A (en) Electrode structure of semiconductor device for use in GaAs compound substrate
JPS5914906B2 (en) Method for manufacturing field effect transistors
JP2822739B2 (en) Semiconductor device
JP2817217B2 (en) Semiconductor device having metal / semiconductor junction and method of manufacturing the same
JPS5950091B2 (en) Manufacturing method of semiconductor device
JPH0249012B2 (en) HANDOTAISOCHINOSEIZOHOHO
JPS5842631B2 (en) Method for manufacturing junction gate field effect transistor
JPH01149461A (en) Semiconductor device
JPS6159782A (en) Semiconductor device
JPS6173381A (en) Manufacture of semiconductor integrated circuit device
US3400308A (en) Metallic contacts for semiconductor devices
JPH06168958A (en) Manufacture of semiconductor device
JPS60189974A (en) Schottky barrier type semiconductor device
JPS62291972A (en) Manufacture of semiconductor device
JPH0294450A (en) Manufacture of semiconductor device
JPS598378A (en) Gaas fet
JPS62224083A (en) High-frequency field-effect transistor
JPH05166748A (en) Manufacture of compound semiconductor device
JPS6252962A (en) Semiconductor device
JPH02220449A (en) Field-effect transistor and manufacture thereof
JPS6179236A (en) Manufacture of semiconductor device
JPS61292952A (en) Gallium arsenide semiconductor element and manufacture thereof
JPS6394639A (en) Manufacture of semiconductor device