JPS6086978U - Printed board testing equipment - Google Patents
Printed board testing equipmentInfo
- Publication number
- JPS6086978U JPS6086978U JP18035683U JP18035683U JPS6086978U JP S6086978 U JPS6086978 U JP S6086978U JP 18035683 U JP18035683 U JP 18035683U JP 18035683 U JP18035683 U JP 18035683U JP S6086978 U JPS6086978 U JP S6086978U
- Authority
- JP
- Japan
- Prior art keywords
- printed board
- circuit
- ground terminals
- arrangement state
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Tests Of Electronic Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案のプリント板試験装置の一実施例構成を示す
ブロック図である。
図において、１はプリント板、２は接続端子盤、２１〜
２ｎは接続端子、２２，２６．２７は接地端子、３はコ
ネクタ、４は検知回路、５は標準信号発生部、６は比較
回路、７はコントローラ、８はディスク部を示している
。The figure is a block diagram showing the configuration of an embodiment of the printed board testing device of the present invention. In the figure, 1 is a printed board, 2 is a connection terminal board, 21-
2n is a connection terminal, 22, 26, 27 are ground terminals, 3 is a connector, 4 is a detection circuit, 5 is a standard signal generator, 6 is a comparison circuit, 7 is a controller, and 8 is a disk unit.
Claims (1)
地端子の配列状態を検知する検知回路と、一方の入力に
前記検知回路からの接地端子の配列状態を示す信号を入
力し、他方の入力に予め試験対象プリント板の形格と対
応づけた接地端子の配列状態を参照する標準信号を順次
入力して両信号の一致を比較する比較回路をそなえ、該
比較回路で両入力の一致が検出された時の標準信号から
被試験プリント板の形格を識別して対応する試量 験を実行するようにしたことを特徴とするプリント板試
験装置。[Claims for Utility Model Registration] A detection circuit that connects a printed circuit board under test having a plurality of terminal arrangements to detect the arrangement state of the ground terminals, and one input indicating the arrangement state of the ground terminals from the detection circuit. The comparison circuit is equipped with a comparison circuit that inputs a signal, and sequentially inputs a standard signal that refers to the arrangement state of ground terminals that has been previously associated with the shape of the printed board to be tested to the other input, and compares the coincidence of both signals. A printed board testing device characterized in that the size of the printed board to be tested is identified from a standard signal when coincidence of both inputs is detected in the circuit, and a corresponding quantity test is executed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18035683U JPS6086978U (en) | 1983-11-21 | 1983-11-21 | Printed board testing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18035683U JPS6086978U (en) | 1983-11-21 | 1983-11-21 | Printed board testing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6086978U true JPS6086978U (en) | 1985-06-14 |
Family
ID=30391077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18035683U Pending JPS6086978U (en) | 1983-11-21 | 1983-11-21 | Printed board testing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6086978U (en) |
-
1983
- 1983-11-21 JP JP18035683U patent/JPS6086978U/en active Pending
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