JPS6086647A - System controller - Google Patents

Abstract

PURPOSE:To eliminate the competition of a memory access buses and to prevent the request from another processing device from waiting improperly, by suppressing input of requests to a precedence discriminating circuit when a memory bank is locked. CONSTITUTION:If a bit of a lock register 60 corresponding to a bank 1 is set when the bank 1 of a memory 3 is read out by a processing device 1-2, input of the request signal from a processing device 1-1 to the precedence discriminating circuit 50 is suppressed in accordance with combination between the output of a lock bit selector 15-1 and the output of a request command register 11-1 by the lock bit selector 15-1, an NAND gate 13-1, and AND gate 14-1, etc. With respect to unlocking, a corresponding bit of the lock register 60 which is designated by the output of a request address selector 16 is reset in accordance with combination of outputs of a request command selector 17 by NAND gates 18-20, an AND gate 21, a decoder 22, etc. Thus, competition for the memory access bus is eliminated to prevent requests from another processing device from waiting improperly.

Description

TECHNICAL FIELD The present invention relates to a system control device in an information processing device, and more particularly to a lock control method when accessing shared information on a memory shared by a plurality of data processing devices. .

Prior Art In an information processing device in which a memory is shared by a plurality of data processing devices and each processing device performs processing using the shared information stored in the memory, one processing device stores the shared information. It is necessary to prevent other processing devices from illegally rewriting the shared information while the shared information is being used to perform processing.

Therefore, conventionally, each processing device uses a read lock command and a write unlock command to access the shared information at the memory location.

That is, when each processing device reads shared information from the memory, it sends a read lock command to the memory via the system control device. The memory has a lock register in which lock information can be set in response to each puncture; When M has already been leaked by another processing unit, the corresponding bit in the lock register is
I'm here.

Jj, if the shared information is not used by another processing device, the lock register corresponding to the puncture in which the shared information is stored is reset. When receiving a request for read lock command (1) from the memory processor, the corresponding bit (1) of the lock register is set, and after the memory access time, the read data and normal readout are performed. A status indicating the status is returned to the processing device.

The processing device that received the above status indicating normal read,
The shared information that has been read is updated, and the existing information (No. 1) is written back to the memory by a write command 770. This command resets the hit in the lock register corresponding to a certain puncture in the shared information.

When this bit is set, upon receiving the REET lock command, the memory returns a status indicating that it is locked to the processing device after the memory access time. The processing device to which the status is returned repeatedly requests the read lock command until the lock is released.

In this way, shared information is prevented from being illegally rewritten.

However, in the above-mentioned conventional method, in order to reduce the amount of hardware, lock control is performed on requests that have undergone priority determination. Therefore, when a read lock command is requested to the memory, if the puncture specified by the command is locked, the read lock command cannot be suppressed. This is because the order of memory access may be disrupted.

Therefore, in response to a read lock command that comes while the lock is in progress, the status indicating that the lock is in progress is returned to the processing device as described above, and the processing device locks the read lock command or locks the read lock command. You need to re-issue it as many times as you like. This has the disadvantage that memory access path conflicts occur and memory accesses from other processing devices are forced to wait unduly.

OBJECTS OF THE INVENTION An object of the present invention is to solve the conventional drawbacks mentioned above, and in response to a read lock command, when the memory puncture specified by the command is locked, the request is sent to the priority determination circuit. By inhibiting input from being input and automatically sending the retlock command to the memory when the lock is released, each processing device does not have to issue the retlock command again and again. An object of the present invention is to provide a system control device capable of controlling memory accesses from other processing devices so as not to wait unduly.

Configuration of the Invention The system control device of the present invention is an information processing device including a memory having a plurality of independently accessible banks and a plurality of data processing devices sharing the memory. In a system control device that determines priorities of requests and controls access to the memory, a plurality of requests for holding request signals inputted from each processing device respectively corresponding to the plurality of data processing devices. a flip-flop, a plurality of request command registers for holding request commands, a plurality of request address registers for holding request addresses, and a plurality of bits holding lock information respectively corresponding to the plurality of banks of the memory. a priority determination circuit that manually receives request signals from the plurality of data processing devices and determines priorities; and the request command register corresponding to the processing device determined by the output of the priority determination circuit. A request command selector that selects and outputs the output of the request address register, a request address selector that similarly selects and outputs the output of the request address register, and a request address selector that selects and outputs the output of the request address register, and a request command selector that selects and outputs the output of the lock register specified by the output of the request address selector. means for setting or resetting the corresponding pin I; a lock bit selector for selectively outputting one bit from a plurality of bit outputs of the lock register according to the output of the request address register; means for suppressing a request signal from the processing device from being input to the priority determination circuit by a combination of the outputs of the request command register, the output of the priority determination circuit and the request address register; Rifnis! - The memory is accessed by the output of the copunt selector.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

The piS1 diagram shows block 1-A representing an embodiment of the present invention.
In this case, two processing devices 1-1 and 1-2 are combined into one memory 3.
The system control device 2 is accessed from each processing device, and the system control device 2 determines the priority order of access from each processing device and controls access to the memory 3. The memory 3 is composed of four banks that can operate simultaneously.

FIG. 2 is a diagram showing the format of a request command from each processing device, and is composed of 8 bits. For a read lotta command, bit o = "o'" and bit 7 = "1" are set, and for a write unlock command, bit 0 = "1" and bit 7 = "1" are set. . Bits 1 through 6 are used for any other functions.

FIG. 3 shows the format of a request command when the system control device 2 accesses the memory 3, and bit 7 is omitted compared to FIG. 2.

FIG. 4 is a diagram showing the format of request addresses from each processing device. That is, bits 0 to 22 specify the address within the puncture, and two bits 23 and 24 identify the four punctures in banks 0 to 3.

FIG. 5 is a block diagram showing details of the system control device 2. As shown in FIG. That is, a request flip-flop 10-1, a request command selector 11-1, and a request command selector 11-1 for respectively storing a request signal a-1, a request frame/F signal b-1, and a request address c-1 sent from the processing device 1-1. A request address register 12-1, a similar request flip-flop 10-2, a request command register 11-2, and a request address register 12-2 corresponding to the processing device 1-2.
2 and request command selector l l-1 and 1
8-pitch 2-way riffist command 1: selector 17 which selects and outputs all the hits (8 bits) output by 1-2 according to the sum of the priority determination circuit 50 described later.
Similarly, the request address selector 16 outputs the outputs of the request address registers 12-1 and 12-2 according to the output of the priority melon determination circuit 50, and the memory 3
A lock register 60 for setting lock information in response to a puncture, and a 4-bit output of the lock register 60 are input, and the request address register 12-
A lock pit selector 15-1 selects and outputs the data by two bits 23 and 24 of pin I of 1 and inputs it to one input of the NAND cable 1-13-1, and similarly, bit 23 of the request address register 12-2. .24 selects and outputs 4 bits of the lock register 60 and outputs NAN.
D game) A lock bit selector 15-2 that is input manually to one input of the request command register 11-1, an inverted signal of the pin 1-0 of the request command register 11-1, an affirmative signal of the hit 7, and the lock pit selector 15-1. A NAND gate 13-1 and a similar NAND gate 13-2, and the request flip-flop 10-
1 and the output of the NAND gate 13-1 and supplies the result to the priority determination circuit 50.
4-1 and a similar AND gate 14-2, and the outputs of AND gates 14-1 and 14-2 are inputted to determine the priority, control the selection of the request address selector 16 and the request command selector 17, and control the selection of the request address selector 16 and request command selector 17. A priority r1 constant circuit 50 that sends the signal d to the memory 3, and an N that manually generates the inverted signal of bit O of the request command selector 17 and the r1 constant signal of bit 7.
an AND gate 18, a NAND gate 19 which receives the input signal of bit 0 of the request command selector 17 and the affirmative signal of bit 7;
and a NAN which inputs the output of the NAND gate 18.
A D gate 20, an AND gate 21 for manually inputting the output of the NAND gate 20 and the Rifnis I signal 5) d output from the priority determination circuit 50, etc.
The corresponding bit of the request address selector register 60 is operated by the output of the NΔAND gate 1.
The decoder 22 sets the output of 9.

The riffist command I signal e output from the request command selector 17 and the request address signal f output from the request address selector 16 are sent to the memory 3 together with the request signal d.

Next, the operation of this embodiment will be explained. Assume that the processing device 1-2 is currently reading bank 1 of the memory 3, and the bit corresponding to bank 1 of the lock register 60 is set to 1''.

At this time, in order to update the shared information in /henkl of the processing device 1-1 or memory 3, the request address signal c-1 specifying the address of the shared information and the bit O of the request command signal b-1 are sent. “0” and bit 7 as “1”
Request signal a-
1 to the system controller 2, these signals are input to the request flip-flops 10-1, respectively.
1.

It is held in the request command register 11-1 and the request address register 12-1.

Now, the combination of bits 23 and 24 of the request address signal (;Cl) stored in the request address register 12-1 is o, i''. The bit to be focused on is 1°. Since the signal supplied from the request address register 12-1 is “0, 1”, the lock pin I selector 15-1 selects /henk 1 of the lock register 60. Select the corresponding bit and use NAND gate 13
-1 human power to one human power. The bit) O of the request command register signal b-1 is "°0'°, and bit 7 is"
i”, the human power of NAND gate 13-1 is
The output of NAND game I・13-1 becomes “°0″. Therefore, AND game 1-1
One input of 4-1 becomes "0"', and the request signal a stored in the request flip-flop 10-1
-1 is inhibited from being manually input to the priority determination circuit 50. In this embodiment, the lock pit selector 1 is
5-1. , NAND game 113-1. AND gate 14
-'LA9 constitutes "a means for inhibiting input of a request signal from the processing device to the priority determination circuit by a combination of the output of the lock hit selector and the output of the request command register."

Next, when the processing unit 1-2 sends a request to the system L/control unit 2 in order to reclaim the common information with a write unlock command, the request signal a-2, the request command signal b-2, and the request address are sent to the system L/control unit 2. Signals c-2 are sent to request flip-flops 10-2 . It is stored in the request command register 11-2 and the request address register 12-2. Therefore, the request command register 0. Both bits 7 become °°1゛, NAND game)
The output of 13-2 becomes "1'°. As a result, the request signal a-2 stored in the request flip-flop 10-2 passes through the AND gate 14-2 and is input to the priority determination circuit 50. Since no other requests are currently input to the priority determination circuit 50, this request has the highest priority, and the request signal d and selection signal g output from the priority determination circuit 50 become "l". , the request address selector 16 and the request command selector 17 select and output the request address selector 2-2 and the request command register 11-2, respectively.Therefore, the human power of the NAND gate 19 is all "1", and the output becomes °゛0°'. Also,
The output of the NAND gate 20 becomes 1, and the AND gate I
・The output of 21 also becomes “1”. In other words, the gate power of the decoder 22 becomes ゛1゛', and the decoder 22 receives the pin output from the request address selector 16.
2 3.

24 (now "o, i") to supply a strobe signal to the hit corresponding to the puncture l of the lock register 60. Now, since the output of the NAND gate 19 is 0, the bit corresponding to the puncture l of the lock register 60 changes from "l" to "0''. In other words, the lock is released. This embodiment , NAND gate 1-1 8 to 20, AND gate 21
．． The decoder 22, etc. constitute means for setting or resetting the corresponding bit of the lock register specified by the output of the Riffnis I/address selector in accordance with the output combination of the request command selector.

On the other hand, a request signal d output from the priority determination circuit 5o and a request command signal e (currently a write unlock command) output from the request command selector 17 are sent to the memory 3, and an output from the request address selector 16 is sent to the memory 3. The shared information at the address indicated by the request address signal f (currently request address signal c-2) is replaced (in FIG. 3, the write data signal is omitted).

In the above operation, when the bit corresponding to the puncture l of the lock register 60 becomes 0°', the output of the lock bit selector 15-1 becomes "0°", and the NAND gate 13
-1 becomes l''', the AND gate 14-1 is opened, the suppression of the request signal a-1 held in the request flip-flop 10-1 is released, and the request signal a-1 is input to the priority determination circuit 50. If this rifnis) is the highest priority, the priority determination circuit 50 sets the selection signal g to "'".
0'', and the request address selector 16 and request command selector 17 selectively output the outputs of the request address register 12-1 and the request command register 111, respectively.
The inputs of the ND gate 18 are all "L", and the NA
ND game I.20.

The Kate power of the decoder 22 is 1 via the AND gate 21.
”. Now, the decode input of the decoder 22, that is, bit 23 of the output of the request address selector 6
．． Since 24 is "°0, 1°", the output of the decoder 22 supplies a strobe signal to the bit corresponding to the puncture l of the lock register 60. Now NAND
Since the output of the gate 19 is l'', the /hencl bit of the lock register 60 is set to l'' again and the lock state is established. Then, for the memory 3, a request signal d, a request command number e (currently a read command), and a request address signal f (a refnis I/address signal c sent from the processing device 1-1) are sent to the memory 3.
-1 indicating the specified address) is sent. Therefore,
Shared information is read from the specified address of the bank specified by the request address signal c-1 on the memory 3 and sent to the processing device i-i (in FIG. 5, the description of the read data is omitted). ).

The read lock and write unlock of other punctures are performed by the same operation as the child chain. The case where the processing device 1-2 issues a read lock is also controlled in the same manner as described above.

Effects of the Invention As described above, in the present invention, a lock register is provided for holding lock information corresponding to each memory puncture, and a request for a locked bank is input to a priority determination circuit. Since the configuration is configured to suppress this, there is no competition in memory access paths, and requests from other processing devices are prevented from being unduly waited, thereby improving performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the format of a request command in the above embodiment, FIG. 3 is a diagram showing the format of a request command from the control device to the memory, and FIG. FIG. 4 is a diagram showing the format of a request address from the processing device, and FIG. 5 is a block diagram showing details of the system control device of the above embodiment. In the figure, 1-1.1-2+processing device, 2・sys y
b, M control device, 3: , II Mo 1, 1.10-
1゜10-2: Request flip-flop, 11-
1.11-2: Request command register, 12-1
．． 12-2: Rifnis I address register, 13-1
．． 13-2: NANI) Gate, 14-1.14-2:
AND gate, 15-1゜15-2: Lock bit selector, 16: Request address selector, 17: Request command selector, 18-20: NAND gate, 21: AND gate, 22: Decoder, 50: Priority determination circuit, 60: Lock register. Applicant NEC Co., Ltd. Agent Patent Attorney Toshimune Sumita Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] An information processing apparatus including a memory having a plurality of independently accessible banks and a plurality of data processing apparatuses sharing the memory determines priorities of requests from the plurality of data processing apparatuses and requests to the memory. A system control device that controls access includes a plurality of request flip-flops for holding request signals respectively inputted from each processing device, and a plurality of request flip-flops for holding request commands, respectively corresponding to the plurality of data processing devices. a lock register having a plurality of request command registers, a plurality of request address registers for holding request addresses, and a plurality of bits holding lock information respectively corresponding to the plurality of banks of the memory;
a priority determination circuit that inputs request signals from the plurality of data processing devices and determines priorities; and a request command that selectively outputs an output of the request command register corresponding to the processing device determined by the priority determination output. A lock lock register designated by the output of the request address selector by a combination of the outputs of the selector, a request address selector that similarly selects and outputs the output of the first I-resist register, and the request command selector described in +iii. M by the output of the QESTA IS-less register which heats one of the plurality of hit outputs of the lock register.
A lock bit selector for outputting a translation, a means for suppressing the output of the request command selector from being manually inputted from the processing device by a combination of the output of the lock bit selector and the output of the request command selector. +iii. 1n A system t and a control device for accessing the memory according to the output of the first judgment W circuit and the outputs of the request address selector and the request command selector.