JPS6085642A - Common channel access control circuit for subscriber equipment in multi-point connection - Google Patents

Abstract

PURPOSE:To control a subscriber equipment in multi-point connection for access of a common channel by providing a common channel access control circuit comprising a data transmission/reception LSI for single point access and a simple accessory circuit to each subscriber equipment. CONSTITUTION:When a frame transmission start/end identification circuit 3 detects the transmission of head of a data frame for data transmission/reception LSI1 and a common channel idle detection circuit 6 does not detect any idle state at the data transmission of a subscriber equipment TEi, the common channel access control circuit CNT stops the supply of transmission clock to the said LSI1 to bring it into standby state. When idle state is detected in the said standby state, the supply of transmission clock is started to start transmission to a common channel of the data frame, missing of data due to transmission collision is prevented by writing the data transmitted by the LSI1 to a transmission buffer at the same time to stop the transmission of a frame subject to collision, and just after the common channel is idle, the buffer 2 transmits automonously again the said data frame.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to access control of a channel shared by a plurality of home devices in a multipoint configuration applied to a digital subscriber system, and in particular to a general-purpose data transmission/reception L
The present invention relates to a circuit that combines an SI and an access control circuit.

Prior Art and Problems In recent years, comprehensive digital service networks [Inte
rated 5 services ctigital
(ISDN)": J is being actively discussed in various countries, and some protocols for user/network interfaces are being standardized internationally.

In the above interface, a multipoint configuration will be applied to the subscriber system, and a method that allows collisions will be adopted as the access control method for the shared channel (called the D channel) from multiple home devices. . This D
As a channel transmission control procedure, HDLC (Ilig
h Level Data Link Control
LAP-B (Link Acc
A procedure based on gzsProtocol-B) is used. When realizing the functions such as 7 lag and CRC control of the transmission control procedure required to realize this, it is possible to achieve this by using the currently available general-purpose data transmission/reception LSI.
A significant reduction in hardware can be achieved. Furthermore, more advanced procedure control, order control, retransmission control, flow control, etc. other than those mentioned above are also possible with some LSIs, and the hardware and software necessary to realize the communication functions of in-home equipment. The amount can be reduced.

However, in the current situation where LSIs for multipoint access have not yet been developed, in order to establish multipoint access technology at an early stage, it is necessary to develop LSIs for single-point access that can reduce hardware and software. It seems appropriate to apply it.

However, these LSIs were developed for home equipment with single-point connections, and for home equipment with multi-point connections, which is the subject of the present invention, LSIs with such procedural control cannot be used. , technology for multipoint access has not been established.

In order to apply the above LSI, control for waiting transmission, retransmission control when a collision occurs, and frame (RR) autonomously generated by the LSI are required.
ty) frames, etc.], there are technical issues such as how to deal with them.

Purpose of the Invention The present invention uses a general-purpose data transmission/reception LSI developed for single-point access to realize shared channel access control in a multipoint configuration, and provides shared channel access control on the home equipment side at the user/network interface of an I5DN. The purpose of this invention is to embody signal channel (D channel) access control, which is a channel, and to realize shared channel access control technology economically and reliably.

Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the connection of an in-home facility in which a plurality of in-home devices each incorporating an access control circuit embodying the present invention are multi-point connected to a bus.

In FIG. 1, TE1 to TEi are in-home equipment, NTr in-home controller, BwR and BuT are receiving and transmitting buses from the in-home controller NT, and L is a subscriber line. The subscriber line connects the home controller NT to a not-shown digital exchange or the like.゛The configuration of only one TEi of the home equipment TE1 is shown in detail, but they all have similar configurations. Control information, B';'-'jl, digitized user information such as call signals, data signals to data terminals, etc. and its receiving terminal, and BT transmits and receives digitized user information. be done.

E is the echo bit. In addition, INI, 14, ox-
→ is a negative circuit.

Note that all the home devices TE to TEi operate in synchronization with the clock supplied from the network side.

FIG. 2 is a diagram showing the format of signals flowing on the paths BUR and BTJT in FIG. 1.

FIG. 2 shows the signal on the receive path BUR.

This signal is, for example, 10 time slots TSo-TS
9 constitutes one frame, each time slot is 1
Time slot TS carries bit information and carries received user information by time slots TS0-TS.

It carries the call control information DR to the receiver by the time slot TS and the echo bit E by the time slot TS. Since all the home devices TEX-TEi operate synchronously, for example, at time slot TS0, all the home devices TEX-TEi operate synchronously.
The bits carried by time slot TSo are received at E, ~TEi. The same applies to information carried by other time slots. However, user information BR (time slot T
S0 to TSq) are received only by the selected home equipment, but other information, namely the call control information DR carried by the time slot TS and the echo bit E carried by the time slot TS.
Information is received by all in-house equipment.

FIG. 2(b) shows the signals on the transmission bus BUT.

This signal is the signal on the receiving bus BUR shown in FIG. 2 (α) and carries call control information DT to the transmitting side. However, time slot TS9 is left blank. Transmission user information BT (time slot) rso-rs, ) tri
It is transmitted from only one selected home device.

time slot) As of TS8, all home equipment T
E, ~TEi can each carry a channel request signal as call control information DT for time slot TSa.

In the home control device NT, the transmission bus BU shown in FIG. 2(b)
The transmission call control information DT carried by the time slot TS is separated from the signal on the time slot T by the separation circuit DMPX, and then sent to the multiplexing circuit M.
Receive path B by PX. Signal on R [Figure 2 (α)]
It is inserted into the data time slot TS as an echo pit E, which will be described later, and returned to all the in-house devices TE□ to TEi.

In Fig. 1, when the home devices TE□ to TEi are empty, they send out the signal DT・1'' as a signal to indicate their status (the home devices TE and TEi are simultaneously transmitted from the home devices to the transmission path B as information DT). .T time slot) TS
, is sent in .

A signal indicating the use of the shared channel for each of the home devices TE1 to TEi, , DTl 7DTi negation DT+
, DTl-DT transmission bus B. The receiving bus B is logically summed by the wiring logic at T, and is logically summed by the multiplexing circuit AIPX. The echo pit is inserted as an echo pit E into the time slot TS of the signal on R, and the echo pit is transmitted to the receiver in each home appliance.

It is received as an E. Here, the logical sum DTl +D? indicated by the above signal DT? 2 ” ””” +DTn is DT+
'DTl'...--D, equal to i. In other words, the above echo bit E is "TI・DT□...
...DTi, that is, a signal D indicating the use of a shared channel
The logical product of T, , DT2 to DTi is shown.

Therefore, if all the home devices TE, -TEi do not use the shared channel, and DTl, DTl, ~DT are all 1", the echo pit Eld becomes "1". However, as mentioned above, If one of the signals DT+, DT2 to D, and i becomes 0.0, the echo pit E indicating the logical product becomes 10''.

In FIG. 1, the present invention is implemented in the shared channel access control circuit indicated by CWT in the home appliance TEi, and an example of its configuration is shown in FIG.

In FIG. 3, 1 is a data transmission/reception LSI that outputs HDLC procedure control, RxD is a data reception terminal, TxD is a data transmission terminal, Rxc is a clock input terminal for data reception, and TxC is a clock input terminal for data transmission. . The data transmission/reception LS 11 performs transmission and reception independently depending on whether or not each clock is supplied.

By stopping the clock supply to the data transmission clock input terminal TxD, the data transmission/reception LSI 1 does not stop reception, but interrupts transmission and changes the data polarity (0 or 1) when the clock is stopped.

The data is held and the subsequent data is transmitted when the clock supply is resumed. The LSI 1 also has a DMA function, and has a function of transmitting data to and from the main memory 9 via the processor CPU 8. LSI 1 always uses the flag (01111110) by clock supply except when transmitting a frame.
) is sent. 2 is a transmission buffer that stores transmission data and retransmits the data only when a collision occurs due to contention. Reference numeral 3 denotes a frame transmission start/end identification circuit (F), which detects the leading position of a data frame transmitted from the LSll and detects the end of frame transmission. A transmission control circuit 4 performs transmission standby control to the LSI 1, retransmission control to the transmission router 2, and the like. Reference numeral 5 denotes a collision detection circuit, which collates the transmitted data bit and the echo bit (E above) returned from the network bit by bit, and considers it to be a collision when they do not match. 6 is a line empty detection circuit which counts the number of '1's in the echo bits E, and detects the number of consecutive 11's in the echo bits (the number of consecutive 11's in the echo bits to be read) by the circuit which counts the number of '1's in the echo bits E, is LS
Selection is made between direct transmission data from I1 and retransmission data from transmission buffer 2. 11 is the second selector (S
EL2) When waiting for transmission or detecting a price collision, use the shared channel [
This is a circuit that sends all 11'' to the time slots TS and DT in FIG. 2(b). Note that 12 is the CPU bus.Terminals DR and E are connected to the separation circuit DMPXT shown in FIG.
The terminal DT is connected to the terminal of the same name of the multiplexing circuit MPXT also shown in FIG.

Next, the operation of this access control circuit CNT will be explained. Prior to frame transmission, the processor CPU 8 first uses the r10 command to set the access priority X1 of the transmission data to the counter comparison value X, and sends it to the I10 interface circuit 7.
A counter (not shown) is provided in the detection circuit 6 and increments every time an echo bit E of 1'' is received.

Based on this, the line empty detection circuit 6, as shown in the shared channel empty detection procedure operation flowchart of FIG. The processor CPU 8 determines that the frame is empty and cannot transmit the frame to the transmission control circuit 4. When the processor CPU 8 has a frame to transmit, it sends a DMA transfer start command to the LSI 1. By omitting it into
The data transmission terminal TXD receives the transmission frame data and starts frame transmission from the data transmission terminal TXD. At this time, the frame transmission start/end identification circuit 3 determines whether the data transmission/reception LS11
The start of frame transmission of the data to be transmitted is detected by detecting a pattern different from the flag, and the transmission control circuit 4 is notified that frame transmission has started, and the line empty detection circuit 6 issues a message indicating that transmission is possible. If so, use L for data transmission/reception.
The transmission clock is continued to be supplied to SI 1, and the data to transmission buffer 2 is started from the flag indicating the 14-person lambda cram school frame. If the line empty detection circuit 6 indicates that line transmission is not possible, the system waits for transmission, stops supplying the transmission clock to the data transmission/reception LSI 1, interrupts transmission data from the data transmission terminal TxD, and
Writing data to the transmission buffer 2 is disabled.

When the shared channel is "empty", the multi-line empty detection circuit 6 starts writing data to the buffer 2 from the flag at the beginning of the frame.

The above has explained the case where data transmission is started by the command of the processor CPU 8, but the data transmission/reception LSI
1 is a frame that is autonomously transmitted without going through the processor CPU 8 (such as an RR frame), the same procedure is followed after the frame is started to be transmitted from the data transmission terminal TxD.

During frame transmission on the shared channel, the collision detection circuit 5 detects the shared channel transmission bit (DT) transmitted from each home device connected to the buses BIJR and BUT.
The logical ANDed duplicate bit (echo ω) pit and the transmission bit (DT) are compared and verified, and if they match, it is considered normal transmission, and if they do not match, it is assumed that a collision has occurred, and the transmission buffer 2 and transmission control circuit 4 (called an interframe time fill) immediately after the collision. At this time, the data transmitting/receiving LSI 1 is not involved in the collision state and continues transmitting the υ frame through the data transmitting terminal TxD, and continues writing to the transmitting buffer 2. The transmission control circuit 4 is a collision detection circuit 5
When it receives a notification (COD) that a collision has occurred from the line empty detection circuit 6, it waits until it is cleared to send because the shared channel is empty. 2 to indicate that retransmission is possible. This causes the transmission buffer 2 to send retransmission from the beginning of the frame where the collision occurred to the first selector 10 (SEL
') Start by opening the gate. Since it is conceivable that the retransmitted frames will collide again, the transmission buffer 2 maintains a configuration in which retransmission is not changed no matter how many times collisions occur, and the details will be described later.

When the frame transmission start/end identification circuit 6 detects the end of frame transmission from the data transmission/reception LS 11, it writes the data to the transmission buffer 2 up to the end flag and stops it. In addition, when the data transmission to the shared channel is completed normally, the channel empty detection circuit 6 increases the counter comparison value and set the bus access privileges of other in-house devices that are waiting for access to a relatively high level. If continuous frame transfer is not to be performed, the counter comparison value X□ is decremented by 1 and returned to its original value.

The overall operation of the access control circuit CRT has been outlined above based on FIG. Next, the circuit configuration and operational outline of the transmission buffer 2, which is one of the features of the present invention, will be explained using FIGS. 5 and 6. FIG. 5 is a configuration diagram of an example of the transmission buffer 2, and FIG. 6 is an operation flow diagram of the transmission buffer described based on FIG. In the transmission buffer configuration shown in FIG. 5, 14 is a transmission buffer memory (SDRFM) for buffering data.
), address control during writing is performed by a write pointer 17 (IP; referred to as an in-pointer), and address control during reading is performed by a read pointer 19 (□P; referred to as an out-pointer). Write and read operations to the transmit buffer are completely independent, and the data line transmission speed (D channel speed is 16 Kb/s) is 1 within the time.
It has one write cycle and one read cycle. In the write operation, as shown in FIG. 5, when the frame transmission start/end identification circuit 3 in FIG. +1 Increment.

2゜Result 1 ~ AIAT 20-c readout 7
When it is equal to the 219 out pointer op value, the buffer has overflowed and the upper processor C
An error is displayed on the PUB, writing is prohibited, and the values of both the in-pointer IP and out-pointer oP are initialized. If rp+oP (Ip>op), one byte of data is written to the address indicated by the out pointer IP of the transmission buffer memory 14.

Writing ends when the frame transmission start/end identification circuit 3 in FIG. 6 detects the end of frame transmission and writes up to the end flag. Next, the read operation starts when a retransmission permission is sent from the transmission control circuit 4 in FIG. 3 after the collision detection circuit 5 in FIG. 3 detects a collision. When the transmission of the frame is completed normally without any collision, when the transmission buffer 2 receives the normal completion signal from the transmission control circuit 4 shown in FIG. Writing and retransmission are not performed, and the data is prepared for writing and reading from the transmission variation memory 2 by transmitting the next frame from the data transmission/reception LSI shown in FIG. When a collision occurs during frame transmission, the transmission control circuit 4 in FIG. 6 starts reading the transmission buffer 2 when it receives that the shared channel is empty and retransmission is possible. First, a sending byte counter (SEC: Sending Bits Count) shown at 22 in FIG.
er) is initialized to 0.

This is provided to enable retransmission no matter how many times collisions occur for the same frame. After completing the initial settings of 5BC22, the set value of 5BC22 is +1 incrementer 23
The out pointer OP of the read pointer 19 is incremented by +1, and the out pointer OP of the read pointer 19 is incremented by +1 incrementer 24f+1, and the data is read from the transmission buffer memory 14 at the address indicated by the out pointer OP of the read pointer 19 and retransmitted to the line. At this time, if a collision occurs, the transmission is stopped and the out pointer o of the read pointer 19 is
The value obtained by subtracting the value of 5Bc22 from the value of p is written to the read pointer 19 as an out pointer OP, and the above out pointer OP value is reset to the retransmission start address, making it possible to retransmit again. If no collision occurs and the in-pointer IP of the sending buffer 14 and the out-pointer OPQ value of the read pointer 19 become equal, it is assumed that up to the final flag part (byte data including even 1 bit of the flag part) of the retransmission frame has been sent. Of the output data, the transmission data to the channel is transmitted up to the final flag.

In the figure, 15.15 is a register, 16 is a parallel/serial conversion circuit, 18.26 is a selector, 21 is an adder, and 26 is a 6-1 selector.

FIG. 7 is a time chart of read and write cycles of the sending buffer 2 of FIG.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention is a general-purpose data transmitting/receiving LSI for single-point access with a fixed circuit for controlling access to a shared channel for household equipment connected to a single bus, etc. at multiple points. The external control device of the data transmitting/receiving LSI, which has a transmission control procedure function, has almost no transmission control procedure function, and is based on the premise of a single-point configuration. Using the conventional data transmission method has the effect of realizing multipoint access. The circuit according to the present invention makes it possible to realize shared signal channel access in a multi-point configuration at the l-3DN user/network interface, which has not been realized yet, and allows users to freely control their home equipment. It has the advantages of portability and the ability to provide a variety of services such as simultaneous communication of telephone and non-telephone home equipment with a simple network configuration using a single subscriber line.Furthermore, in the future, data transmission for multipoint The circuit according to the present invention has the advantage of providing useful suggestions in the development of a commercially available LSI.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the connection of an in-house facility in which multiple in-home devices each incorporating an access control circuit embodying the present invention are connected to a bus at multiple points. 3 is a connection diagram of an example of an access control circuit embodying the present invention, FIG. 4 is an operation flow diagram of a common channel vacant detection procedure, and FIG. 5 is a diagram showing the flow of an access control circuit according to the present invention. This is a time chart. TE, ~TEi...In-home equipment, BUR...Receiving bus, BUT...Transmitting bus, NT...In-home control device, L
...Subscriber line, MPX, MPXT--...Multiplex circuit,
DMPX, DMPX, T... Separation circuit, 1... LSI for data transmission and reception, 2... Transmission buffer, 6...
Frame transmission start/end identification circuit, 4... Transmission control circuit, 5... Collision detection circuit, 6... Line empty detection circuit,
7... I10 interface circuit, 8... Processor (of CP), 9... Main memory (MM), 10...
- First selector (SELl), 11... Second selector (SEL2), 12... Processor bus, 13
...Register (REGl), 14...Transmission buffer memory (SDRFM), 15...Register (REG
2), 16...Parallel/serial conversion (P/S conversion) circuit, 17...1 read pointer (rp; in pointer), 18...2-+1 selector, 19...
Read pointer (OP; out pointer), 20...
・Matcher (MAT), 21... Adder (ΔZ) 7
)), 22...Send notes counter (SBC), 2
'5, 24.25...+1 incrementer -126.
...5-1 selector. Patent applicant Nippon Telegraph and Telephone Public Corporation Patent attorney Gobe Tamamushi (2 others)

Claims (1)

[Claims] A plurality of home devices are multi-point connected to the bus via the home control device, and all the home devices synchronize and exchange data with the home control device, and the home device j' transfers call control information and user information. When accessing a shared channel to be used, in a method that performs access control based on information regarding the usage status of the shared channel from the home control device, each of the above home devices transmits and receives frames in synchronization with an externally supplied clock.IIDLC (high-level data link control) function, a shared channel empty detection circuit, a collision detection circuit, a frame transmission start/end identification circuit, a transmission buffer, and a and a transmission control circuit that controls transmission based on information, and when an in-home device transmits data, the data transmitting/receiving LSI of the in-home device detects the beginning of the data frame following the start flag (a pattern different from the flag). ; address part) is detected by the frame transmission start/end identification circuit, and if the shared channel empty detection circuit detects an empty state, the transmission to the data transmission/reception LSI is performed. The reliable clock supply is immediately stopped, data transmission is made to wait, and if an empty state is detected in the waiting state, the above-mentioned transmission clock supply is immediately started, and the shared channel is placed at the beginning of the data frame (start flag). By starting transmission to ψ and simultaneously writing the data transmitted by the data transmission/reception LSI into the transmission buffer from the start flag, data loss can be avoided in the event of a collision due to contention during data transmission. In order to prevent collisions, data transmission to the shared channel is immediately stopped for frames in which a collision has occurred, and immediately after the shared channel becomes empty, the data frame is retransmitted autonomously from the sofa. A shared channel access control circuit for in-home equipment in a multipoint connection, characterized by the following.